llvm/MCA/Context.h

0001 //===---------------------------- Context.h ---------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// This file defines a class for holding ownership of various simulated
0011 /// hardware units.  A Context also provides a utility routine for constructing
0012 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
0013 /// stages.
0014 ///
0015 //===----------------------------------------------------------------------===//
0016
0017 #ifndef LLVM_MCA_CONTEXT_H
0018 #define LLVM_MCA_CONTEXT_H
0019
0020 #include "llvm/MC/MCRegisterInfo.h"
0021 #include "llvm/MC/MCSubtargetInfo.h"
0022 #include "llvm/MCA/CustomBehaviour.h"
0023 #include "llvm/MCA/HardwareUnits/HardwareUnit.h"
0024 #include "llvm/MCA/Pipeline.h"
0025 #include "llvm/MCA/SourceMgr.h"
0026 #include <memory>
0027
0028 namespace llvm {
0029 namespace mca {
0030
0031 /// This is a convenience struct to hold the parameters necessary for creating
0032 /// the pre-built "default" out-of-order pipeline.
0033 struct PipelineOptions {
0034   PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
0035                   unsigned LQS, unsigned SQS, bool NoAlias,
0036                   bool ShouldEnableBottleneckAnalysis = false)
0037       : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
0038         DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
0039         StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
0040         EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
0041   unsigned MicroOpQueueSize;
0042   unsigned DecodersThroughput; // Instructions per cycle.
0043   unsigned DispatchWidth;
0044   unsigned RegisterFileSize;
0045   unsigned LoadQueueSize;
0046   unsigned StoreQueueSize;
0047   bool AssumeNoAlias;
0048   bool EnableBottleneckAnalysis;
0049 };
0050
0051 class Context {
0052   SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
0053   const MCRegisterInfo &MRI;
0054   const MCSubtargetInfo &STI;
0055
0056 public:
0057   Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
0058   Context(const Context &C) = delete;
0059   Context &operator=(const Context &C) = delete;
0060
0061   const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
0062   const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
0063
0064   void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
0065     Hardware.push_back(std::move(H));
0066   }
0067
0068   /// Construct a basic pipeline for simulating an out-of-order pipeline.
0069   /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
0070   std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
0071                                                   SourceMgr &SrcMgr,
0072                                                   CustomBehaviour &CB);
0073
0074   /// Construct a basic pipeline for simulating an in-order pipeline.
0075   /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
0076   std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
0077                                                   SourceMgr &SrcMgr,
0078                                                   CustomBehaviour &CB);
0079 };
0080
0081 } // namespace mca
0082 } // namespace llvm
0083 #endif // LLVM_MCA_CONTEXT_H