llvm/MCA/Pipeline.h

0001 //===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// This file implements an ordered container of stages that simulate the
0011 /// pipeline of a hardware backend.
0012 ///
0013 //===----------------------------------------------------------------------===//
0014
0015 #ifndef LLVM_MCA_PIPELINE_H
0016 #define LLVM_MCA_PIPELINE_H
0017
0018 #include "llvm/MCA/Stages/Stage.h"
0019 #include "llvm/Support/Error.h"
0020
0021 namespace llvm {
0022 namespace mca {
0023
0024 class HWEventListener;
0025
0026 /// A pipeline for a specific subtarget.
0027 ///
0028 /// It emulates an out-of-order execution of instructions. Instructions are
0029 /// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
0030 /// Instructions are firstly fetched, then dispatched to the schedulers, and
0031 /// then executed.
0032 ///
0033 /// This class tracks the lifetime of an instruction from the moment where
0034 /// it gets dispatched to the schedulers, to the moment where it finishes
0035 /// executing and register writes are architecturally committed.
0036 /// In particular, it monitors changes in the state of every instruction
0037 /// in flight.
0038 ///
0039 /// Instructions are executed in a loop of iterations. The number of iterations
0040 /// is defined by the SourceMgr object, which is managed by the initial stage
0041 /// of the instruction pipeline.
0042 ///
0043 /// The Pipeline entry point is method 'run()' which executes cycles in a loop
0044 /// until there are new instructions to dispatch, and not every instruction
0045 /// has been retired.
0046 ///
0047 /// Internally, the Pipeline collects statistical information in the form of
0048 /// histograms. For example, it tracks how the dispatch group size changes
0049 /// over time.
0050 class Pipeline {
0051   Pipeline(const Pipeline &P) = delete;
0052   Pipeline &operator=(const Pipeline &P) = delete;
0053
0054   enum class State {
0055     Created, // Pipeline was just created. The default state.
0056     Started, // Pipeline has started running.
0057     Paused   // Pipeline is paused.
0058   };
0059   State CurrentState = State::Created;
0060
0061   /// An ordered list of stages that define this instruction pipeline.
0062   SmallVector<std::unique_ptr<Stage>, 8> Stages;
0063   std::set<HWEventListener *> Listeners;
0064   unsigned Cycles = 0;
0065
0066   Error runCycle();
0067   bool hasWorkToProcess();
0068   void notifyCycleBegin();
0069   void notifyCycleEnd();
0070
0071 public:
0072   Pipeline() = default;
0073   void appendStage(std::unique_ptr<Stage> S);
0074
0075   /// Returns the total number of simulated cycles.
0076   Expected<unsigned> run();
0077
0078   void addEventListener(HWEventListener *Listener);
0079
0080   /// Returns whether the pipeline is currently paused.
0081   bool isPaused() const { return CurrentState == State::Paused; }
0082 };
0083 } // namespace mca
0084 } // namespace llvm
0085
0086 #endif // LLVM_MCA_PIPELINE_H