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0001 //== llvm/CodeGen/GlobalISel/LegalizerHelper.h ---------------- -*- C++ -*-==//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 /// \file A pass to convert the target-illegal operations created by IR -> MIR
0010 /// translation into ones the target expects to be able to select. This may
0011 /// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
0012 /// G_ADD <4 x i16>.
0013 ///
0014 /// The LegalizerHelper class is where most of the work happens, and is
0015 /// designed to be callable from other passes that find themselves with an
0016 /// illegal instruction.
0017 //
0018 //===----------------------------------------------------------------------===//
0019 
0020 #ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
0021 #define LLVM_CODEGEN_GLOBALISEL_LEGALIZERHELPER_H
0022 
0023 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
0024 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
0025 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
0026 #include "llvm/CodeGen/RuntimeLibcallUtil.h"
0027 #include "llvm/CodeGen/TargetOpcodes.h"
0028 
0029 namespace llvm {
0030 // Forward declarations.
0031 class APInt;
0032 class GAnyLoad;
0033 class GLoadStore;
0034 class GStore;
0035 class GenericMachineInstr;
0036 class MachineFunction;
0037 class MachineIRBuilder;
0038 class MachineInstr;
0039 class MachineInstrBuilder;
0040 struct MachinePointerInfo;
0041 template <typename T> class SmallVectorImpl;
0042 class LegalizerInfo;
0043 class MachineRegisterInfo;
0044 class GISelChangeObserver;
0045 class LostDebugLocObserver;
0046 class TargetLowering;
0047 
0048 class LegalizerHelper {
0049 public:
0050   /// Expose MIRBuilder so clients can set their own RecordInsertInstruction
0051   /// functions
0052   MachineIRBuilder &MIRBuilder;
0053 
0054   /// To keep track of changes made by the LegalizerHelper.
0055   GISelChangeObserver &Observer;
0056 
0057 private:
0058   MachineRegisterInfo &MRI;
0059   const LegalizerInfo &LI;
0060   const TargetLowering &TLI;
0061   GISelKnownBits *KB;
0062 
0063 public:
0064   enum LegalizeResult {
0065     /// Instruction was already legal and no change was made to the
0066     /// MachineFunction.
0067     AlreadyLegal,
0068 
0069     /// Instruction has been legalized and the MachineFunction changed.
0070     Legalized,
0071 
0072     /// Some kind of error has occurred and we could not legalize this
0073     /// instruction.
0074     UnableToLegalize,
0075   };
0076 
0077   /// Expose LegalizerInfo so the clients can re-use.
0078   const LegalizerInfo &getLegalizerInfo() const { return LI; }
0079   const TargetLowering &getTargetLowering() const { return TLI; }
0080   GISelKnownBits *getKnownBits() const { return KB; }
0081 
0082   LegalizerHelper(MachineFunction &MF, GISelChangeObserver &Observer,
0083                   MachineIRBuilder &B);
0084   LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
0085                   GISelChangeObserver &Observer, MachineIRBuilder &B,
0086                   GISelKnownBits *KB = nullptr);
0087 
0088   /// Replace \p MI by a sequence of legal instructions that can implement the
0089   /// same operation. Note that this means \p MI may be deleted, so any iterator
0090   /// steps should be performed before calling this function. \p Helper should
0091   /// be initialized to the MachineFunction containing \p MI.
0092   ///
0093   /// Considered as an opaque blob, the legal code will use and define the same
0094   /// registers as \p MI.
0095   LegalizeResult legalizeInstrStep(MachineInstr &MI,
0096                                    LostDebugLocObserver &LocObserver);
0097 
0098   /// Legalize an instruction by emiting a runtime library call instead.
0099   LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
0100 
0101   /// Legalize an instruction by reducing the width of the underlying scalar
0102   /// type.
0103   LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
0104 
0105   /// Legalize an instruction by performing the operation on a wider scalar type
0106   /// (for example a 16-bit addition can be safely performed at 32-bits
0107   /// precision, ignoring the unused bits).
0108   LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
0109 
0110   /// Legalize an instruction by replacing the value type
0111   LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0112 
0113   /// Legalize an instruction by splitting it into simpler parts, hopefully
0114   /// understood by the target.
0115   LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0116 
0117   /// Legalize a vector instruction by splitting into multiple components, each
0118   /// acting on the same scalar type as the original but with fewer elements.
0119   LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
0120                                      LLT NarrowTy);
0121 
0122   /// Legalize a vector instruction by increasing the number of vector elements
0123   /// involved and ignoring the added elements later.
0124   LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
0125                                     LLT MoreTy);
0126 
0127   /// Cast the given value to an LLT::scalar with an equivalent size. Returns
0128   /// the register to use if an instruction was inserted. Returns the original
0129   /// register if no coercion was necessary.
0130   //
0131   // This may also fail and return Register() if there is no legal way to cast.
0132   Register coerceToScalar(Register Val);
0133 
0134   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0135   /// Use by extending the operand's type to \p WideTy using the specified \p
0136   /// ExtOpcode for the extension instruction, and replacing the vreg of the
0137   /// operand in place.
0138   void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
0139                       unsigned ExtOpcode);
0140 
0141   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0142   /// Use by truncating the operand's type to \p NarrowTy using G_TRUNC, and
0143   /// replacing the vreg of the operand in place.
0144   void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
0145 
0146   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0147   /// Def by extending the operand's type to \p WideTy and truncating it back
0148   /// with the \p TruncOpcode, and replacing the vreg of the operand in place.
0149   void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
0150                       unsigned TruncOpcode = TargetOpcode::G_TRUNC);
0151 
0152   // Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0153   // Def by truncating the operand's type to \p NarrowTy, replacing in place and
0154   // extending back with \p ExtOpcode.
0155   void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
0156                        unsigned ExtOpcode);
0157   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0158   /// Def by performing it with additional vector elements and extracting the
0159   /// result elements, and replacing the vreg of the operand in place.
0160   void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
0161 
0162   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0163   /// Use by producing a vector with undefined high elements, extracting the
0164   /// original vector type, and replacing the vreg of the operand in place.
0165   void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
0166 
0167   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0168   /// use by inserting a G_BITCAST to \p CastTy
0169   void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
0170 
0171   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
0172   /// def by inserting a G_BITCAST from \p CastTy
0173   void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
0174 
0175 private:
0176   LegalizeResult
0177   widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
0178   LegalizeResult
0179   widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
0180   LegalizeResult
0181   widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
0182   LegalizeResult
0183   widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
0184   LegalizeResult widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
0185                                            LLT WideTy);
0186   LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
0187                                          LLT WideTy);
0188   LegalizeResult widenScalarMulo(MachineInstr &MI, unsigned TypeIdx,
0189                                  LLT WideTy);
0190 
0191   /// Helper function to build a wide generic register \p DstReg of type \p
0192   /// RegTy from smaller parts. This will produce a G_MERGE_VALUES,
0193   /// G_BUILD_VECTOR, G_CONCAT_VECTORS, or sequence of G_INSERT as appropriate
0194   /// for the types.
0195   ///
0196   /// \p PartRegs must be registers of type \p PartTy.
0197   ///
0198   /// If \p ResultTy does not evenly break into \p PartTy sized pieces, the
0199   /// remainder must be specified with \p LeftoverRegs of type \p LeftoverTy.
0200   void insertParts(Register DstReg, LLT ResultTy,
0201                    LLT PartTy, ArrayRef<Register> PartRegs,
0202                    LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
0203 
0204   /// Merge \p PartRegs with different types into \p DstReg.
0205   void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
0206 
0207   void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
0208 
0209   /// Unmerge \p SrcReg into smaller sized values, and append them to \p
0210   /// Parts. The elements of \p Parts will be the greatest common divisor type
0211   /// of \p DstTy, \p NarrowTy and the type of \p SrcReg. This will compute and
0212   /// return the GCD type.
0213   LLT extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
0214                      LLT NarrowTy, Register SrcReg);
0215 
0216   /// Unmerge \p SrcReg into \p GCDTy typed registers. This will append all of
0217   /// the unpacked registers to \p Parts. This version is if the common unmerge
0218   /// type is already known.
0219   void extractGCDType(SmallVectorImpl<Register> &Parts, LLT GCDTy,
0220                       Register SrcReg);
0221 
0222   /// Produce a merge of values in \p VRegs to define \p DstReg. Perform a merge
0223   /// from the least common multiple type, and convert as appropriate to \p
0224   /// DstReg.
0225   ///
0226   /// \p VRegs should each have type \p GCDTy. This type should be greatest
0227   /// common divisor type of \p DstReg, \p NarrowTy, and an undetermined source
0228   /// type.
0229   ///
0230   /// \p NarrowTy is the desired result merge source type. If the source value
0231   /// needs to be widened to evenly cover \p DstReg, inserts high bits
0232   /// corresponding to the extension opcode \p PadStrategy.
0233   ///
0234   /// \p VRegs will be cleared, and the result \p NarrowTy register pieces
0235   /// will replace it. Returns The complete LCMTy that \p VRegs will cover when
0236   /// merged.
0237   LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
0238                           SmallVectorImpl<Register> &VRegs,
0239                           unsigned PadStrategy = TargetOpcode::G_ANYEXT);
0240 
0241   /// Merge the values in \p RemergeRegs to an \p LCMTy typed value. Extract the
0242   /// low bits into \p DstReg. This is intended to use the outputs from
0243   /// buildLCMMergePieces after processing.
0244   void buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
0245                                 ArrayRef<Register> RemergeRegs);
0246 
0247   /// Perform generic multiplication of values held in multiple registers.
0248   /// Generated instructions use only types NarrowTy and i1.
0249   /// Destination can be same or two times size of the source.
0250   void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
0251                          ArrayRef<Register> Src1Regs,
0252                          ArrayRef<Register> Src2Regs, LLT NarrowTy);
0253 
0254   void changeOpcode(MachineInstr &MI, unsigned NewOpcode);
0255 
0256   LegalizeResult tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg,
0257                                         LLT SrcTy, LLT NarrowTy,
0258                                         unsigned ScalarOpc);
0259 
0260   // Memcpy family legalization helpers.
0261   LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
0262                              uint64_t KnownLen, Align Alignment,
0263                              bool IsVolatile);
0264   LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
0265                                    uint64_t KnownLen, Align DstAlign,
0266                                    Align SrcAlign, bool IsVolatile);
0267   LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
0268                              uint64_t KnownLen, uint64_t Limit, Align DstAlign,
0269                              Align SrcAlign, bool IsVolatile);
0270   LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
0271                               uint64_t KnownLen, Align DstAlign, Align SrcAlign,
0272                               bool IsVolatile);
0273 
0274   // Implements floating-point environment read/write via library function call.
0275   LegalizeResult createGetStateLibcall(MachineIRBuilder &MIRBuilder,
0276                                        MachineInstr &MI,
0277                                        LostDebugLocObserver &LocObserver);
0278   LegalizeResult createSetStateLibcall(MachineIRBuilder &MIRBuilder,
0279                                        MachineInstr &MI,
0280                                        LostDebugLocObserver &LocObserver);
0281   LegalizeResult createResetStateLibcall(MachineIRBuilder &MIRBuilder,
0282                                          MachineInstr &MI,
0283                                          LostDebugLocObserver &LocObserver);
0284   LegalizeResult createFCMPLibcall(MachineIRBuilder &MIRBuilder,
0285                                    MachineInstr &MI,
0286                                    LostDebugLocObserver &LocObserver);
0287 
0288   MachineInstrBuilder
0289   getNeutralElementForVecReduce(unsigned Opcode, MachineIRBuilder &MIRBuilder,
0290                                 LLT Ty);
0291 
0292 public:
0293   /// Return the alignment to use for a stack temporary object with the given
0294   /// type.
0295   Align getStackTemporaryAlignment(LLT Type, Align MinAlign = Align()) const;
0296 
0297   /// Create a stack temporary based on the size in bytes and the alignment
0298   MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment,
0299                                            MachinePointerInfo &PtrInfo);
0300 
0301   /// Create a store of \p Val to a stack temporary and return a load as the
0302   /// same type as \p Res.
0303   MachineInstrBuilder createStackStoreLoad(const DstOp &Res, const SrcOp &Val);
0304 
0305   /// Given a store of a boolean vector, scalarize it.
0306   LegalizeResult scalarizeVectorBooleanStore(GStore &MI);
0307 
0308   /// Get a pointer to vector element \p Index located in memory for a vector of
0309   /// type \p VecTy starting at a base address of \p VecPtr. If \p Index is out
0310   /// of bounds the returned pointer is unspecified, but will be within the
0311   /// vector bounds.
0312   Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index);
0313 
0314   /// Handles most opcodes. Split \p MI into same instruction on sub-vectors or
0315   /// scalars with \p NumElts elements (1 for scalar). Supports uneven splits:
0316   /// there can be leftover sub-vector with fewer then \p NumElts or a leftover
0317   /// scalar. To avoid this use moreElements first and set MI number of elements
0318   /// to multiple of \p NumElts. Non-vector operands that should be used on all
0319   /// sub-instructions without split are listed in \p NonVecOpIndices.
0320   LegalizeResult fewerElementsVectorMultiEltType(
0321       GenericMachineInstr &MI, unsigned NumElts,
0322       std::initializer_list<unsigned> NonVecOpIndices = {});
0323 
0324   LegalizeResult fewerElementsVectorPhi(GenericMachineInstr &MI,
0325                                         unsigned NumElts);
0326 
0327   LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
0328                                        LLT MoreTy);
0329   LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
0330                                            LLT MoreTy);
0331 
0332   LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI,
0333                                                   unsigned TypeIdx,
0334                                                   LLT NarrowTy);
0335   LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
0336                                           LLT NarrowTy);
0337   LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
0338                                                            unsigned TypeIdx,
0339                                                            LLT NarrowTy);
0340 
0341   /// Equalize source and destination vector sizes of G_SHUFFLE_VECTOR.
0342   LegalizeResult equalizeVectorShuffleLengths(MachineInstr &MI);
0343 
0344   LegalizeResult reduceLoadStoreWidth(GLoadStore &MI, unsigned TypeIdx,
0345                                       LLT NarrowTy);
0346 
0347   LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
0348                                              LLT HalfTy, LLT ShiftAmtTy);
0349 
0350   LegalizeResult fewerElementsVectorReductions(MachineInstr &MI,
0351                                                unsigned TypeIdx, LLT NarrowTy);
0352   LegalizeResult fewerElementsVectorSeqReductions(MachineInstr &MI,
0353                                                   unsigned TypeIdx,
0354                                                   LLT NarrowTy);
0355 
0356   // Fewer Elements for bitcast, ensuring that the size of the Src and Dst
0357   // registers will be the same
0358   LegalizeResult fewerElementsBitcast(MachineInstr &MI, unsigned TypeIdx,
0359                                       LLT NarrowTy);
0360 
0361   LegalizeResult fewerElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
0362                                             LLT NarrowTy);
0363 
0364   LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0365   LegalizeResult narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
0366                                     LLT NarrowTy);
0367   LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty);
0368   LegalizeResult narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0369   LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0370   LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0371 
0372   LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0373   LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0374   LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0375   LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0376   LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0377   LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0378   LegalizeResult narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
0379 
0380   /// Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
0381   LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
0382                                          LLT CastTy);
0383 
0384   /// Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
0385   LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
0386                                         LLT CastTy);
0387   LegalizeResult bitcastConcatVector(MachineInstr &MI, unsigned TypeIdx,
0388                                      LLT CastTy);
0389   LegalizeResult bitcastShuffleVector(MachineInstr &MI, unsigned TypeIdx,
0390                                       LLT CastTy);
0391   LegalizeResult bitcastExtractSubvector(MachineInstr &MI, unsigned TypeIdx,
0392                                          LLT CastTy);
0393   LegalizeResult bitcastInsertSubvector(MachineInstr &MI, unsigned TypeIdx,
0394                                         LLT CastTy);
0395 
0396   LegalizeResult lowerConstant(MachineInstr &MI);
0397   LegalizeResult lowerFConstant(MachineInstr &MI);
0398   LegalizeResult lowerBitcast(MachineInstr &MI);
0399   LegalizeResult lowerLoad(GAnyLoad &MI);
0400   LegalizeResult lowerStore(GStore &MI);
0401   LegalizeResult lowerBitCount(MachineInstr &MI);
0402   LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI);
0403   LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI);
0404   LegalizeResult lowerFunnelShift(MachineInstr &MI);
0405   LegalizeResult lowerEXT(MachineInstr &MI);
0406   LegalizeResult lowerTRUNC(MachineInstr &MI);
0407   LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI);
0408   LegalizeResult lowerRotate(MachineInstr &MI);
0409 
0410   LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
0411   LegalizeResult lowerU64ToF32WithSITOFP(MachineInstr &MI);
0412   LegalizeResult lowerU64ToF64BitFloatOps(MachineInstr &MI);
0413   LegalizeResult lowerUITOFP(MachineInstr &MI);
0414   LegalizeResult lowerSITOFP(MachineInstr &MI);
0415   LegalizeResult lowerFPTOUI(MachineInstr &MI);
0416   LegalizeResult lowerFPTOSI(MachineInstr &MI);
0417   LegalizeResult lowerFPTOINT_SAT(MachineInstr &MI);
0418 
0419   LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI);
0420   LegalizeResult lowerFPTRUNC(MachineInstr &MI);
0421   LegalizeResult lowerFPOWI(MachineInstr &MI);
0422 
0423   LegalizeResult lowerISFPCLASS(MachineInstr &MI);
0424 
0425   LegalizeResult lowerThreewayCompare(MachineInstr &MI);
0426   LegalizeResult lowerMinMax(MachineInstr &MI);
0427   LegalizeResult lowerFCopySign(MachineInstr &MI);
0428   LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
0429   LegalizeResult lowerFMad(MachineInstr &MI);
0430   LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
0431   LegalizeResult lowerFFloor(MachineInstr &MI);
0432   LegalizeResult lowerMergeValues(MachineInstr &MI);
0433   LegalizeResult lowerUnmergeValues(MachineInstr &MI);
0434   LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI);
0435   LegalizeResult lowerShuffleVector(MachineInstr &MI);
0436   LegalizeResult lowerVECTOR_COMPRESS(MachineInstr &MI);
0437   Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize,
0438                                      Align Alignment, LLT PtrTy);
0439   LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
0440   LegalizeResult lowerStackSave(MachineInstr &MI);
0441   LegalizeResult lowerStackRestore(MachineInstr &MI);
0442   LegalizeResult lowerExtract(MachineInstr &MI);
0443   LegalizeResult lowerInsert(MachineInstr &MI);
0444   LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
0445   LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI);
0446   LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI);
0447   LegalizeResult lowerShlSat(MachineInstr &MI);
0448   LegalizeResult lowerBswap(MachineInstr &MI);
0449   LegalizeResult lowerBitreverse(MachineInstr &MI);
0450   LegalizeResult lowerReadWriteRegister(MachineInstr &MI);
0451   LegalizeResult lowerSMULH_UMULH(MachineInstr &MI);
0452   LegalizeResult lowerSelect(MachineInstr &MI);
0453   LegalizeResult lowerDIVREM(MachineInstr &MI);
0454   LegalizeResult lowerAbsToAddXor(MachineInstr &MI);
0455   LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI);
0456   LegalizeResult lowerAbsToCNeg(MachineInstr &MI);
0457   LegalizeResult lowerFAbs(MachineInstr &MI);
0458   LegalizeResult lowerVectorReduction(MachineInstr &MI);
0459   LegalizeResult lowerMemcpyInline(MachineInstr &MI);
0460   LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
0461   LegalizeResult lowerVAArg(MachineInstr &MI);
0462 };
0463 
0464 /// Helper function that creates a libcall to the given \p Name using the given
0465 /// calling convention \p CC.
0466 LegalizerHelper::LegalizeResult
0467 createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
0468               const CallLowering::ArgInfo &Result,
0469               ArrayRef<CallLowering::ArgInfo> Args, CallingConv::ID CC,
0470               LostDebugLocObserver &LocObserver, MachineInstr *MI = nullptr);
0471 
0472 /// Helper function that creates the given libcall.
0473 LegalizerHelper::LegalizeResult
0474 createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
0475               const CallLowering::ArgInfo &Result,
0476               ArrayRef<CallLowering::ArgInfo> Args,
0477               LostDebugLocObserver &LocObserver, MachineInstr *MI = nullptr);
0478 
0479 /// Create a libcall to memcpy et al.
0480 LegalizerHelper::LegalizeResult
0481 createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
0482                  MachineInstr &MI, LostDebugLocObserver &LocObserver);
0483 
0484 
0485 } // End namespace llvm.
0486 
0487 #endif
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