xsimd/arch/xsimd_avx512vbmi2.hpp

0001 /***************************************************************************
0002  * Copyright (c) Johan Mabille, Sylvain Corlay, Wolf Vollprecht and         *
0003  * Martin Renou                                                             *
0004  * Copyright (c) QuantStack                                                 *
0005  * Copyright (c) Serge Guelton                                              *
0006  *                                                                          *
0007  * Distributed under the terms of the BSD 3-Clause License.                 *
0008  *                                                                          *
0009  * The full license is in the file LICENSE, distributed with this software. *
0010  ****************************************************************************/
0011
0012 #ifndef XSIMD_AVX512VBMI2_HPP
0013 #define XSIMD_AVX512VBMI2_HPP
0014
0015 #include "../types/xsimd_avx512vbmi2_register.hpp"
0016
0017 #include <type_traits>
0018
0019 namespace xsimd
0020 {
0021
0022     namespace kernel
0023     {
0024         using namespace types;
0025
0026         // compress
0027         template <class A>
0028         XSIMD_INLINE batch<int16_t, A> compress(batch<int16_t, A> const& self, batch_bool<int16_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0029         {
0030             return _mm512_maskz_compress_epi16((__mmask32)mask.mask(), self);
0031         }
0032         template <class A>
0033         XSIMD_INLINE batch<uint16_t, A> compress(batch<uint16_t, A> const& self, batch_bool<uint16_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0034         {
0035             return _mm512_maskz_compress_epi16((__mmask32)mask.mask(), self);
0036         }
0037         template <class A>
0038         XSIMD_INLINE batch<int8_t, A> compress(batch<int8_t, A> const& self, batch_bool<int8_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0039         {
0040             return _mm512_maskz_compress_epi8(mask.mask(), self);
0041         }
0042         template <class A>
0043         XSIMD_INLINE batch<uint8_t, A> compress(batch<uint8_t, A> const& self, batch_bool<uint8_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0044         {
0045             return _mm512_maskz_compress_epi8(mask.mask(), self);
0046         }
0047
0048         // expand
0049         template <class A>
0050         XSIMD_INLINE batch<int16_t, A> expand(batch<int16_t, A> const& self, batch_bool<int16_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0051         {
0052             return _mm512_maskz_expand_epi16((__mmask32)mask.mask(), self);
0053         }
0054         template <class A>
0055         XSIMD_INLINE batch<uint16_t, A> expand(batch<uint16_t, A> const& self, batch_bool<uint16_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0056         {
0057             return _mm512_maskz_expand_epi16((__mmask32)mask.mask(), self);
0058         }
0059         template <class A>
0060         XSIMD_INLINE batch<int8_t, A> expand(batch<int8_t, A> const& self, batch_bool<int8_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0061         {
0062             return _mm512_maskz_expand_epi8(mask.mask(), self);
0063         }
0064         template <class A>
0065         XSIMD_INLINE batch<uint8_t, A> expand(batch<uint8_t, A> const& self, batch_bool<uint8_t, A> const& mask, requires_arch<avx512vbmi2>) noexcept
0066         {
0067             return _mm512_maskz_expand_epi8(mask.mask(), self);
0068         }
0069
0070         // rotl
0071         template <class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
0072         XSIMD_INLINE batch<T, A> rotl(batch<T, A> const& self, int32_t other, requires_arch<avx512vbmi2>) noexcept
0073         {
0074             XSIMD_IF_CONSTEXPR(sizeof(T) == 2)
0075             {
0076                 return _mm512_shldv_epi16(self, self, _mm512_set1_epi16(static_cast<uint16_t>(other)));
0077             }
0078             else
0079             {
0080                 return rotl(self, other, avx512bw {});
0081             }
0082         }
0083
0084         template <size_t count, class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
0085         XSIMD_INLINE batch<T, A> rotl(batch<T, A> const& self, requires_arch<avx512vbmi2>) noexcept
0086         {
0087             constexpr auto bits = std::numeric_limits<T>::digits + std::numeric_limits<T>::is_signed;
0088             static_assert(count < bits, "Count must be less than the number of bits in T");
0089             XSIMD_IF_CONSTEXPR(sizeof(T) == 2)
0090             {
0091                 return _mm512_shldi_epi16(self, self, count);
0092             }
0093             else
0094             {
0095                 return rotl<count>(self, avx512bw {});
0096             }
0097         }
0098
0099         // rotr
0100         template <class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
0101         XSIMD_INLINE batch<T, A> rotr(batch<T, A> const& self, int32_t other, requires_arch<avx512vbmi2>) noexcept
0102         {
0103             XSIMD_IF_CONSTEXPR(sizeof(T) == 2)
0104             {
0105                 return _mm512_shrdv_epi16(self, self, _mm512_set1_epi16(static_cast<uint16_t>(other)));
0106             }
0107             else
0108             {
0109                 return rotr(self, other, avx512bw {});
0110             }
0111         }
0112
0113         template <size_t count, class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
0114         XSIMD_INLINE batch<T, A> rotr(batch<T, A> const& self, requires_arch<avx512vbmi2>) noexcept
0115         {
0116             constexpr auto bits = std::numeric_limits<T>::digits + std::numeric_limits<T>::is_signed;
0117             static_assert(count < bits, "count must be less than the number of bits in T");
0118             XSIMD_IF_CONSTEXPR(sizeof(T) == 2)
0119             {
0120                 return _mm512_shrdi_epi16(self, self, count);
0121             }
0122             else
0123             {
0124                 return rotr<count>(self, avx512bw {});
0125             }
0126         }
0127     }
0128 }
0129
0130 #endif