Warning, /include/llvm/TargetParser/RISCVTargetParserDef.inc is written in an unsupported language. File is not indexed.
0001 #ifdef GET_SUPPORTED_EXTENSIONS
0002 #undef GET_SUPPORTED_EXTENSIONS
0003
0004 static const RISCVSupportedExtension SupportedExtensions[] = {
0005 {"a", {2, 1}},
0006 {"b", {1, 0}},
0007 {"c", {2, 0}},
0008 {"d", {2, 2}},
0009 {"e", {2, 0}},
0010 {"f", {2, 2}},
0011 {"h", {1, 0}},
0012 {"i", {2, 1}},
0013 {"m", {2, 0}},
0014 {"sha", {1, 0}},
0015 {"shcounterenw", {1, 0}},
0016 {"shgatpa", {1, 0}},
0017 {"shtvala", {1, 0}},
0018 {"shvsatpa", {1, 0}},
0019 {"shvstvala", {1, 0}},
0020 {"shvstvecd", {1, 0}},
0021 {"smaia", {1, 0}},
0022 {"smcdeleg", {1, 0}},
0023 {"smcsrind", {1, 0}},
0024 {"smdbltrp", {1, 0}},
0025 {"smepmp", {1, 0}},
0026 {"smmpm", {1, 0}},
0027 {"smnpm", {1, 0}},
0028 {"smrnmi", {1, 0}},
0029 {"smstateen", {1, 0}},
0030 {"ssaia", {1, 0}},
0031 {"ssccfg", {1, 0}},
0032 {"ssccptr", {1, 0}},
0033 {"sscofpmf", {1, 0}},
0034 {"sscounterenw", {1, 0}},
0035 {"sscsrind", {1, 0}},
0036 {"ssdbltrp", {1, 0}},
0037 {"ssnpm", {1, 0}},
0038 {"sspm", {1, 0}},
0039 {"ssqosid", {1, 0}},
0040 {"ssstateen", {1, 0}},
0041 {"ssstrict", {1, 0}},
0042 {"sstc", {1, 0}},
0043 {"sstvala", {1, 0}},
0044 {"sstvecd", {1, 0}},
0045 {"ssu64xl", {1, 0}},
0046 {"supm", {1, 0}},
0047 {"svade", {1, 0}},
0048 {"svadu", {1, 0}},
0049 {"svbare", {1, 0}},
0050 {"svinval", {1, 0}},
0051 {"svnapot", {1, 0}},
0052 {"svpbmt", {1, 0}},
0053 {"svvptc", {1, 0}},
0054 {"v", {1, 0}},
0055 {"xcvalu", {1, 0}},
0056 {"xcvbi", {1, 0}},
0057 {"xcvbitmanip", {1, 0}},
0058 {"xcvelw", {1, 0}},
0059 {"xcvmac", {1, 0}},
0060 {"xcvmem", {1, 0}},
0061 {"xcvsimd", {1, 0}},
0062 {"xmipscmove", {1, 0}},
0063 {"xmipslsp", {1, 0}},
0064 {"xsfcease", {1, 0}},
0065 {"xsfvcp", {1, 0}},
0066 {"xsfvfnrclipxfqf", {1, 0}},
0067 {"xsfvfwmaccqqq", {1, 0}},
0068 {"xsfvqmaccdod", {1, 0}},
0069 {"xsfvqmaccqoq", {1, 0}},
0070 {"xsifivecdiscarddlone", {1, 0}},
0071 {"xsifivecflushdlone", {1, 0}},
0072 {"xtheadba", {1, 0}},
0073 {"xtheadbb", {1, 0}},
0074 {"xtheadbs", {1, 0}},
0075 {"xtheadcmo", {1, 0}},
0076 {"xtheadcondmov", {1, 0}},
0077 {"xtheadfmemidx", {1, 0}},
0078 {"xtheadmac", {1, 0}},
0079 {"xtheadmemidx", {1, 0}},
0080 {"xtheadmempair", {1, 0}},
0081 {"xtheadsync", {1, 0}},
0082 {"xtheadvdot", {1, 0}},
0083 {"xventanacondops", {1, 0}},
0084 {"xwchc", {2, 2}},
0085 {"za128rs", {1, 0}},
0086 {"za64rs", {1, 0}},
0087 {"zaamo", {1, 0}},
0088 {"zabha", {1, 0}},
0089 {"zacas", {1, 0}},
0090 {"zalrsc", {1, 0}},
0091 {"zama16b", {1, 0}},
0092 {"zawrs", {1, 0}},
0093 {"zba", {1, 0}},
0094 {"zbb", {1, 0}},
0095 {"zbc", {1, 0}},
0096 {"zbkb", {1, 0}},
0097 {"zbkc", {1, 0}},
0098 {"zbkx", {1, 0}},
0099 {"zbs", {1, 0}},
0100 {"zca", {1, 0}},
0101 {"zcb", {1, 0}},
0102 {"zcd", {1, 0}},
0103 {"zce", {1, 0}},
0104 {"zcf", {1, 0}},
0105 {"zcmop", {1, 0}},
0106 {"zcmp", {1, 0}},
0107 {"zcmt", {1, 0}},
0108 {"zdinx", {1, 0}},
0109 {"zfa", {1, 0}},
0110 {"zfbfmin", {1, 0}},
0111 {"zfh", {1, 0}},
0112 {"zfhmin", {1, 0}},
0113 {"zfinx", {1, 0}},
0114 {"zhinx", {1, 0}},
0115 {"zhinxmin", {1, 0}},
0116 {"zic64b", {1, 0}},
0117 {"zicbom", {1, 0}},
0118 {"zicbop", {1, 0}},
0119 {"zicboz", {1, 0}},
0120 {"ziccamoa", {1, 0}},
0121 {"ziccif", {1, 0}},
0122 {"zicclsm", {1, 0}},
0123 {"ziccrse", {1, 0}},
0124 {"zicntr", {2, 0}},
0125 {"zicond", {1, 0}},
0126 {"zicsr", {2, 0}},
0127 {"zifencei", {2, 0}},
0128 {"zihintntl", {1, 0}},
0129 {"zihintpause", {2, 0}},
0130 {"zihpm", {2, 0}},
0131 {"zimop", {1, 0}},
0132 {"zk", {1, 0}},
0133 {"zkn", {1, 0}},
0134 {"zknd", {1, 0}},
0135 {"zkne", {1, 0}},
0136 {"zknh", {1, 0}},
0137 {"zkr", {1, 0}},
0138 {"zks", {1, 0}},
0139 {"zksed", {1, 0}},
0140 {"zksh", {1, 0}},
0141 {"zkt", {1, 0}},
0142 {"zmmul", {1, 0}},
0143 {"ztso", {1, 0}},
0144 {"zvbb", {1, 0}},
0145 {"zvbc", {1, 0}},
0146 {"zve32f", {1, 0}},
0147 {"zve32x", {1, 0}},
0148 {"zve64d", {1, 0}},
0149 {"zve64f", {1, 0}},
0150 {"zve64x", {1, 0}},
0151 {"zvfbfmin", {1, 0}},
0152 {"zvfbfwma", {1, 0}},
0153 {"zvfh", {1, 0}},
0154 {"zvfhmin", {1, 0}},
0155 {"zvkb", {1, 0}},
0156 {"zvkg", {1, 0}},
0157 {"zvkn", {1, 0}},
0158 {"zvknc", {1, 0}},
0159 {"zvkned", {1, 0}},
0160 {"zvkng", {1, 0}},
0161 {"zvknha", {1, 0}},
0162 {"zvknhb", {1, 0}},
0163 {"zvks", {1, 0}},
0164 {"zvksc", {1, 0}},
0165 {"zvksed", {1, 0}},
0166 {"zvksg", {1, 0}},
0167 {"zvksh", {1, 0}},
0168 {"zvkt", {1, 0}},
0169 {"zvl1024b", {1, 0}},
0170 {"zvl128b", {1, 0}},
0171 {"zvl16384b", {1, 0}},
0172 {"zvl2048b", {1, 0}},
0173 {"zvl256b", {1, 0}},
0174 {"zvl32768b", {1, 0}},
0175 {"zvl32b", {1, 0}},
0176 {"zvl4096b", {1, 0}},
0177 {"zvl512b", {1, 0}},
0178 {"zvl64b", {1, 0}},
0179 {"zvl65536b", {1, 0}},
0180 {"zvl8192b", {1, 0}},
0181 };
0182
0183 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
0184 {"sdext", {1, 0}},
0185 {"sdtrig", {1, 0}},
0186 {"smctr", {1, 0}},
0187 {"ssctr", {1, 0}},
0188 {"svukte", {0, 3}},
0189 {"xqcia", {0, 2}},
0190 {"xqciac", {0, 3}},
0191 {"xqcicli", {0, 2}},
0192 {"xqcicm", {0, 2}},
0193 {"xqcics", {0, 2}},
0194 {"xqcicsr", {0, 2}},
0195 {"xqciint", {0, 2}},
0196 {"xqcilo", {0, 2}},
0197 {"xqcilsm", {0, 2}},
0198 {"xqcisls", {0, 2}},
0199 {"zalasr", {0, 1}},
0200 {"zicfilp", {1, 0}},
0201 {"zicfiss", {1, 0}},
0202 {"zvbc32e", {0, 7}},
0203 {"zvkgs", {0, 7}},
0204 };
0205
0206 #endif // GET_SUPPORTED_EXTENSIONS
0207
0208 #ifdef GET_IMPLIED_EXTENSIONS
0209 #undef GET_IMPLIED_EXTENSIONS
0210
0211
0212 static constexpr ImpliedExtsEntry ImpliedExts[] = {
0213 { {"a"}, "zaamo"},
0214 { {"a"}, "zalrsc"},
0215 { {"b"}, "zba"},
0216 { {"b"}, "zbb"},
0217 { {"b"}, "zbs"},
0218 { {"d"}, "f"},
0219 { {"f"}, "zicsr"},
0220 { {"m"}, "zmmul"},
0221 { {"sha"}, "h"},
0222 { {"sha"}, "ssstateen"},
0223 { {"sha"}, "shcounterenw"},
0224 { {"sha"}, "shvstvala"},
0225 { {"sha"}, "shtvala"},
0226 { {"sha"}, "shvstvecd"},
0227 { {"sha"}, "shvsatpa"},
0228 { {"sha"}, "shgatpa"},
0229 { {"smctr"}, "sscsrind"},
0230 { {"ssctr"}, "sscsrind"},
0231 { {"v"}, "zvl128b"},
0232 { {"v"}, "zve64d"},
0233 { {"xqciac"}, "zca"},
0234 { {"xqcicm"}, "zca"},
0235 { {"xqciint"}, "zca"},
0236 { {"xqcilo"}, "zca"},
0237 { {"xsfvcp"}, "zve32x"},
0238 { {"xsfvfnrclipxfqf"}, "zve32f"},
0239 { {"xsfvfwmaccqqq"}, "zvfbfmin"},
0240 { {"xsfvqmaccdod"}, "zve32x"},
0241 { {"xsfvqmaccqoq"}, "zve32x"},
0242 { {"xtheadvdot"}, "v"},
0243 { {"zabha"}, "zaamo"},
0244 { {"zacas"}, "zaamo"},
0245 { {"zcb"}, "zca"},
0246 { {"zcd"}, "d"},
0247 { {"zcd"}, "zca"},
0248 { {"zce"}, "zcb"},
0249 { {"zce"}, "zcmp"},
0250 { {"zce"}, "zcmt"},
0251 { {"zcf"}, "f"},
0252 { {"zcf"}, "zca"},
0253 { {"zcmop"}, "zca"},
0254 { {"zcmp"}, "zca"},
0255 { {"zcmt"}, "zca"},
0256 { {"zcmt"}, "zicsr"},
0257 { {"zdinx"}, "zfinx"},
0258 { {"zfa"}, "f"},
0259 { {"zfbfmin"}, "f"},
0260 { {"zfh"}, "zfhmin"},
0261 { {"zfhmin"}, "f"},
0262 { {"zfinx"}, "zicsr"},
0263 { {"zhinx"}, "zhinxmin"},
0264 { {"zhinxmin"}, "zfinx"},
0265 { {"zicfilp"}, "zicsr"},
0266 { {"zicfiss"}, "zicsr"},
0267 { {"zicfiss"}, "zimop"},
0268 { {"zicntr"}, "zicsr"},
0269 { {"zihpm"}, "zicsr"},
0270 { {"zk"}, "zkn"},
0271 { {"zk"}, "zkr"},
0272 { {"zk"}, "zkt"},
0273 { {"zkn"}, "zbkb"},
0274 { {"zkn"}, "zbkc"},
0275 { {"zkn"}, "zbkx"},
0276 { {"zkn"}, "zkne"},
0277 { {"zkn"}, "zknd"},
0278 { {"zkn"}, "zknh"},
0279 { {"zks"}, "zbkb"},
0280 { {"zks"}, "zbkc"},
0281 { {"zks"}, "zbkx"},
0282 { {"zks"}, "zksed"},
0283 { {"zks"}, "zksh"},
0284 { {"zvbb"}, "zvkb"},
0285 { {"zvbc"}, "zve64x"},
0286 { {"zvbc32e"}, "zve32x"},
0287 { {"zve32f"}, "zve32x"},
0288 { {"zve32f"}, "f"},
0289 { {"zve32x"}, "zicsr"},
0290 { {"zve32x"}, "zvl32b"},
0291 { {"zve64d"}, "zve64f"},
0292 { {"zve64d"}, "d"},
0293 { {"zve64f"}, "zve32f"},
0294 { {"zve64f"}, "zve64x"},
0295 { {"zve64x"}, "zve32x"},
0296 { {"zve64x"}, "zvl64b"},
0297 { {"zvfbfmin"}, "zve32f"},
0298 { {"zvfbfwma"}, "zvfbfmin"},
0299 { {"zvfbfwma"}, "zfbfmin"},
0300 { {"zvfh"}, "zvfhmin"},
0301 { {"zvfh"}, "zfhmin"},
0302 { {"zvfhmin"}, "zve32f"},
0303 { {"zvkb"}, "zve32x"},
0304 { {"zvkg"}, "zve32x"},
0305 { {"zvkgs"}, "zvkg"},
0306 { {"zvkn"}, "zvkned"},
0307 { {"zvkn"}, "zvknhb"},
0308 { {"zvkn"}, "zvkb"},
0309 { {"zvkn"}, "zvkt"},
0310 { {"zvknc"}, "zvkn"},
0311 { {"zvknc"}, "zvbc"},
0312 { {"zvkned"}, "zve32x"},
0313 { {"zvkng"}, "zvkn"},
0314 { {"zvkng"}, "zvkg"},
0315 { {"zvknha"}, "zve32x"},
0316 { {"zvknhb"}, "zve64x"},
0317 { {"zvks"}, "zvksed"},
0318 { {"zvks"}, "zvksh"},
0319 { {"zvks"}, "zvkb"},
0320 { {"zvks"}, "zvkt"},
0321 { {"zvksc"}, "zvks"},
0322 { {"zvksc"}, "zvbc"},
0323 { {"zvksed"}, "zve32x"},
0324 { {"zvksg"}, "zvks"},
0325 { {"zvksg"}, "zvkg"},
0326 { {"zvksh"}, "zve32x"},
0327 { {"zvl1024b"}, "zvl512b"},
0328 { {"zvl128b"}, "zvl64b"},
0329 { {"zvl16384b"}, "zvl8192b"},
0330 { {"zvl2048b"}, "zvl1024b"},
0331 { {"zvl256b"}, "zvl128b"},
0332 { {"zvl32768b"}, "zvl16384b"},
0333 { {"zvl4096b"}, "zvl2048b"},
0334 { {"zvl512b"}, "zvl256b"},
0335 { {"zvl64b"}, "zvl32b"},
0336 { {"zvl65536b"}, "zvl32768b"},
0337 { {"zvl8192b"}, "zvl4096b"},
0338 };
0339
0340 #endif // GET_IMPLIED_EXTENSIONS
0341
0342 #ifdef GET_SUPPORTED_PROFILES
0343 #undef GET_SUPPORTED_PROFILES
0344
0345 static constexpr RISCVProfile SupportedProfiles[] = {
0346 {"rva20s64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"},
0347 {"rva20u64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_za128rs1p0"},
0348 {"rva22s64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"},
0349 {"rva22u64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zkt1p0"},
0350 {"rva23s64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zcb1p0_zcmop1p0_zkt1p0_zvbb1p0_zvfhmin1p0_zvkt1p0_sha1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"},
0351 {"rva23u64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zcb1p0_zcmop1p0_zkt1p0_zvbb1p0_zvfhmin1p0_zvkt1p0_supm1p0"},
0352 {"rvb23s64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zcb1p0_zcmop1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"},
0353 {"rvb23u64","rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zcb1p0_zcmop1p0_zkt1p0"},
0354 {"rvi20u32","rv32i2p1"},
0355 {"rvi20u64","rv64i2p1"},
0356 };
0357
0358 static constexpr RISCVProfile SupportedExperimentalProfiles[] = {
0359 {"rvm23u32","rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zihintntl1p0_zihintpause2p0_zimop1p0_zce1p0_zcmop1p0"},
0360 };
0361
0362 #endif // GET_SUPPORTED_PROFILES
0363
0364 #ifndef PROC
0365 #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
0366 #endif
0367
0368 PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0369 PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0370 PROC(MIPS_P8700, {"mips-p8700"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0_xmipscmove1p0_xmipslsp1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0371 PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0372 PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0373 PROC(RP2350_HAZARD3, {"rp2350-hazard3"}, {"rv32i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0_zcb1p0_zcmp1p0_zba1p0_zbb1p0_zbkb1p0_zbs1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0374 PROC(SIFIVE_E20, {"sifive-e20"}, {"rv32i2p1_m2p0_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0375 PROC(SIFIVE_E21, {"sifive-e21"}, {"rv32i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0376 PROC(SIFIVE_E24, {"sifive-e24"}, {"rv32i2p1_m2p0_a2p1_f2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0377 PROC(SIFIVE_E31, {"sifive-e31"}, {"rv32i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0378 PROC(SIFIVE_E34, {"sifive-e34"}, {"rv32i2p1_m2p0_a2p1_f2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0379 PROC(SIFIVE_E76, {"sifive-e76"}, {"rv32i2p1_m2p0_a2p1_f2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0380 PROC(SIFIVE_P450, {"sifive-p450"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zkt1p0"}, 1, 1, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0381 PROC(SIFIVE_P470, {"sifive-p470"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zkt1p0_zvbb1p0_zvknc1p0_zvkng1p0_zvksc1p0_zvksg1p0_zvl128b1p0_xsifivecdiscarddlone1p0_xsifivecflushdlone1p0"}, 1, 1, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0382 PROC(SIFIVE_P550, {"sifive-p550"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zifencei2p0_zba1p0_zbb1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0383 PROC(SIFIVE_P670, {"sifive-p670"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zkt1p0_zvbb1p0_zvknc1p0_zvkng1p0_zvksc1p0_zvksg1p0_zvl128b1p0"}, 1, 1, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0384 PROC(SIFIVE_S21, {"sifive-s21"}, {"rv64i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0385 PROC(SIFIVE_S51, {"sifive-s51"}, {"rv64i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0386 PROC(SIFIVE_S54, {"sifive-s54"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0387 PROC(SIFIVE_S76, {"sifive-s76"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zifencei2p0_zihintpause2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0388 PROC(SIFIVE_U54, {"sifive-u54"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0389 PROC(SIFIVE_U74, {"sifive-u74"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0390 PROC(SIFIVE_X280, {"sifive-x280"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zifencei2p0_zfh1p0_zba1p0_zbb1p0_zvfh1p0_zvl512b1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0391 PROC(SPACEMIT_X60, {"spacemit-x60"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfh1p0_zfhmin1p0_zbc1p0_zbkc1p0_zkt1p0_zvfh1p0_zvkt1p0_zvl256b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"}, 1, 0, 0x00000710, 0x8000000058000001, 0x1000000049772200)
0392 PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"}, {"rv32i2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0393 PROC(SYNTACORE_SCR1_MAX, {"syntacore-scr1-max"}, {"rv32i2p1_m2p0_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0394 PROC(SYNTACORE_SCR3_RV32, {"syntacore-scr3-rv32"}, {"rv32i2p1_m2p0_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0395 PROC(SYNTACORE_SCR3_RV64, {"syntacore-scr3-rv64"}, {"rv64i2p1_m2p0_a2p1_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0396 PROC(SYNTACORE_SCR4_RV32, {"syntacore-scr4-rv32"}, {"rv32i2p1_m2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0397 PROC(SYNTACORE_SCR4_RV64, {"syntacore-scr4-rv64"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0398 PROC(SYNTACORE_SCR5_RV32, {"syntacore-scr5-rv32"}, {"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0399 PROC(SYNTACORE_SCR5_RV64, {"syntacore-scr5-rv64"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0400 PROC(SYNTACORE_SCR7, {"syntacore-scr7"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zkn1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0401 PROC(TENSTORRENT_ASCALON_D8, {"tt-ascalon-d8"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zcb1p0_zcmop1p0_zkt1p0_zvbb1p0_zvbc1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkng1p0_zvkt1p0_zvl256b1p0_sha1p0_smaia1p0_ssaia1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstrict1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"}, 1, 1, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0402 PROC(VENTANA_VEYRON_V1, {"veyron-v1"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicbom1p0_zicbop1p0_zicboz1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xventanacondops1p0"}, 0, 0, 0x0000061f, 0x8000000000010000, 0x0000000000000111)
0403 PROC(XIANGSHAN_NANHU, {"xiangshan-nanhu"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicbom1p0_zicboz1p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zkn1p0_zksed1p0_zksh1p0_svinval1p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
0404
0405 #undef PROC
0406
0407 #ifndef TUNE_PROC
0408 #define TUNE_PROC(ENUM, NAME)
0409 #endif
0410
0411 TUNE_PROC(GENERIC, "generic")
0412 TUNE_PROC(ROCKET, "rocket")
0413 TUNE_PROC(SIFIVE_7, "sifive-7-series")
0414
0415 #undef TUNE_PROC
0416 #ifdef GET_RISCVExtensionBitmaskTable_IMPL
0417 static const RISCVExtensionBitmask ExtensionBitmask[]={
0418 {"a", 0, 0ULL},
0419 {"c", 0, 2ULL},
0420 {"d", 0, 3ULL},
0421 {"f", 0, 5ULL},
0422 {"i", 0, 8ULL},
0423 {"m", 0, 12ULL},
0424 {"v", 0, 21ULL},
0425 {"zacas", 0, 26ULL},
0426 {"zba", 0, 27ULL},
0427 {"zbb", 0, 28ULL},
0428 {"zbc", 0, 29ULL},
0429 {"zbkb", 0, 30ULL},
0430 {"zbkc", 0, 31ULL},
0431 {"zbkx", 0, 32ULL},
0432 {"zbs", 0, 33ULL},
0433 {"zfa", 0, 34ULL},
0434 {"zfh", 0, 35ULL},
0435 {"zfhmin", 0, 36ULL},
0436 {"zicboz", 0, 37ULL},
0437 {"zicond", 0, 38ULL},
0438 {"zihintntl", 0, 39ULL},
0439 {"zihintpause", 0, 40ULL},
0440 {"zknd", 0, 41ULL},
0441 {"zkne", 0, 42ULL},
0442 {"zknh", 0, 43ULL},
0443 {"zksed", 0, 44ULL},
0444 {"zksh", 0, 45ULL},
0445 {"zkt", 0, 46ULL},
0446 {"ztso", 0, 47ULL},
0447 {"zvbb", 0, 48ULL},
0448 {"zvbc", 0, 49ULL},
0449 {"zvfh", 0, 50ULL},
0450 {"zvfhmin", 0, 51ULL},
0451 {"zvkb", 0, 52ULL},
0452 {"zvkg", 0, 53ULL},
0453 {"zvkned", 0, 54ULL},
0454 {"zvknha", 0, 55ULL},
0455 {"zvknhb", 0, 56ULL},
0456 {"zvksed", 0, 57ULL},
0457 {"zvksh", 0, 58ULL},
0458 {"zvkt", 0, 59ULL},
0459 };
0460 #endif
