llvm/TargetParser/RISCVTargetParser.h

0001 //===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file implements a target parser to recognise hardware features
0010 // for RISC-V CPUs.
0011 //
0012 //===----------------------------------------------------------------------===//
0013
0014 #ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H
0015 #define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
0016
0017 #include "llvm/ADT/StringRef.h"
0018 #include "llvm/Support/MathExtras.h"
0019 #include "llvm/Support/raw_ostream.h"
0020
0021 namespace llvm {
0022
0023 class Triple;
0024
0025 namespace RISCV {
0026
0027 namespace RISCVExtensionBitmaskTable {
0028 struct RISCVExtensionBitmask {
0029   const char *Name;
0030   unsigned GroupID;
0031   unsigned BitPosition;
0032 };
0033 } // namespace RISCVExtensionBitmaskTable
0034
0035 struct CPUModel {
0036   uint32_t MVendorID;
0037   uint64_t MArchID;
0038   uint64_t MImpID;
0039 };
0040
0041 struct CPUInfo {
0042   StringLiteral Name;
0043   StringLiteral DefaultMarch;
0044   bool FastScalarUnalignedAccess;
0045   bool FastVectorUnalignedAccess;
0046   CPUModel Model;
0047   bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
0048 };
0049
0050 // We use 64 bits as the known part in the scalable vector types.
0051 static constexpr unsigned RVVBitsPerBlock = 64;
0052
0053 void getFeaturesForCPU(StringRef CPU,
0054                        SmallVectorImpl<std::string> &EnabledFeatures,
0055                        bool NeedPlus = false);
0056 bool parseCPU(StringRef CPU, bool IsRV64);
0057 bool parseTuneCPU(StringRef CPU, bool IsRV64);
0058 StringRef getMArchFromMcpu(StringRef CPU);
0059 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
0060 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
0061 bool hasFastScalarUnalignedAccess(StringRef CPU);
0062 bool hasFastVectorUnalignedAccess(StringRef CPU);
0063 bool hasValidCPUModel(StringRef CPU);
0064 CPUModel getCPUModel(StringRef CPU);
0065
0066 } // namespace RISCV
0067
0068 namespace RISCVII {
0069 enum VLMUL : uint8_t {
0070   LMUL_1 = 0,
0071   LMUL_2,
0072   LMUL_4,
0073   LMUL_8,
0074   LMUL_RESERVED,
0075   LMUL_F8,
0076   LMUL_F4,
0077   LMUL_F2
0078 };
0079
0080 enum {
0081   TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
0082   TAIL_AGNOSTIC = 1,
0083   MASK_AGNOSTIC = 2,
0084 };
0085 } // namespace RISCVII
0086
0087 namespace RISCVVType {
0088 // Is this a SEW value that can be encoded into the VTYPE format.
0089 inline static bool isValidSEW(unsigned SEW) {
0090   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
0091 }
0092
0093 // Is this a LMUL value that can be encoded into the VTYPE format.
0094 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
0095   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
0096 }
0097
0098 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
0099                      bool MaskAgnostic);
0100
0101 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
0102   unsigned VLMUL = VType & 0x7;
0103   return static_cast<RISCVII::VLMUL>(VLMUL);
0104 }
0105
0106 // Decode VLMUL into 1,2,4,8 and fractional indicator.
0107 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
0108
0109 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
0110   assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
0111   unsigned LmulLog2 = Log2_32(LMUL);
0112   return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
0113 }
0114
0115 inline static unsigned decodeVSEW(unsigned VSEW) {
0116   assert(VSEW < 8 && "Unexpected VSEW value");
0117   return 1 << (VSEW + 3);
0118 }
0119
0120 inline static unsigned encodeSEW(unsigned SEW) {
0121   assert(isValidSEW(SEW) && "Unexpected SEW value");
0122   return Log2_32(SEW) - 3;
0123 }
0124
0125 inline static unsigned getSEW(unsigned VType) {
0126   unsigned VSEW = (VType >> 3) & 0x7;
0127   return decodeVSEW(VSEW);
0128 }
0129
0130 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
0131
0132 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
0133
0134 void printVType(unsigned VType, raw_ostream &OS);
0135
0136 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
0137
0138 std::optional<RISCVII::VLMUL>
0139 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
0140 } // namespace RISCVVType
0141
0142 } // namespace llvm
0143
0144 #endif