llvm/TargetParser/ARMTargetParser.h

0001 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file implements a target parser to recognise ARM hardware features
0010 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
0011 //
0012 //===----------------------------------------------------------------------===//
0013
0014 #ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
0015 #define LLVM_TARGETPARSER_ARMTARGETPARSER_H
0016
0017 #include "llvm/ADT/StringMap.h"
0018 #include "llvm/ADT/StringRef.h"
0019 #include "llvm/Support/ARMBuildAttributes.h"
0020 #include "llvm/TargetParser/ARMTargetParserCommon.h"
0021 #include <vector>
0022
0023 namespace llvm {
0024
0025 class Triple;
0026
0027 namespace ARM {
0028
0029 // Arch extension modifiers for CPUs.
0030 // Note that this is not the same as the AArch64 list
0031 enum ArchExtKind : uint64_t {
0032   AEK_INVALID = 0,
0033   AEK_NONE = 1,
0034   AEK_CRC = 1 << 1,
0035   AEK_CRYPTO = 1 << 2,
0036   AEK_FP = 1 << 3,
0037   AEK_HWDIVTHUMB = 1 << 4,
0038   AEK_HWDIVARM = 1 << 5,
0039   AEK_MP = 1 << 6,
0040   AEK_SIMD = 1 << 7,
0041   AEK_SEC = 1 << 8,
0042   AEK_VIRT = 1 << 9,
0043   AEK_DSP = 1 << 10,
0044   AEK_FP16 = 1 << 11,
0045   AEK_RAS = 1 << 12,
0046   AEK_DOTPROD = 1 << 13,
0047   AEK_SHA2 = 1 << 14,
0048   AEK_AES = 1 << 15,
0049   AEK_FP16FML = 1 << 16,
0050   AEK_SB = 1 << 17,
0051   AEK_FP_DP = 1 << 18,
0052   AEK_LOB = 1 << 19,
0053   AEK_BF16 = 1 << 20,
0054   AEK_I8MM = 1 << 21,
0055   AEK_CDECP0 = 1 << 22,
0056   AEK_CDECP1 = 1 << 23,
0057   AEK_CDECP2 = 1 << 24,
0058   AEK_CDECP3 = 1 << 25,
0059   AEK_CDECP4 = 1 << 26,
0060   AEK_CDECP5 = 1 << 27,
0061   AEK_CDECP6 = 1 << 28,
0062   AEK_CDECP7 = 1 << 29,
0063   AEK_PACBTI = 1 << 30,
0064   // Unsupported extensions.
0065   AEK_OS = 1ULL << 59,
0066   AEK_IWMMXT = 1ULL << 60,
0067   AEK_IWMMXT2 = 1ULL << 61,
0068   AEK_MAVERICK = 1ULL << 62,
0069   AEK_XSCALE = 1ULL << 63,
0070 };
0071
0072 // List of Arch Extension names.
0073 struct ExtName {
0074   StringRef Name;
0075   uint64_t ID;
0076   StringRef Feature;
0077   StringRef NegFeature;
0078 };
0079
0080 const ExtName ARCHExtNames[] = {
0081 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       \
0082   {NAME, ID, FEATURE, NEGFEATURE},
0083 #include "ARMTargetParser.def"
0084 };
0085
0086 // List of HWDiv names (use getHWDivSynonym) and which architectural
0087 // features they correspond to (use getHWDivFeatures).
0088 const struct {
0089   StringRef Name;
0090   uint64_t ID;
0091 } HWDivNames[] = {
0092 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
0093 #include "ARMTargetParser.def"
0094 };
0095
0096 // Arch names.
0097 enum class ArchKind {
0098 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
0099                  ARCH_BASE_EXT)                                                \
0100   ID,
0101 #include "ARMTargetParser.def"
0102 };
0103
0104 // List of CPU names and their arches.
0105 // The same CPU can have multiple arches and can be default on multiple arches.
0106 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
0107 // When this becomes table-generated, we'd probably need two tables.
0108 struct CpuNames {
0109   StringRef Name;
0110   ArchKind ArchID;
0111   bool Default; // is $Name the default CPU for $ArchID ?
0112   uint64_t DefaultExtensions;
0113 };
0114
0115 const CpuNames CPUNames[] = {
0116 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
0117   {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
0118 #include "ARMTargetParser.def"
0119 };
0120
0121 // FPU names.
0122 enum FPUKind {
0123 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
0124 #include "ARMTargetParser.def"
0125   FK_LAST
0126 };
0127
0128 // FPU Version
0129 enum class FPUVersion {
0130   NONE,
0131   VFPV2,
0132   VFPV3,
0133   VFPV3_FP16,
0134   VFPV4,
0135   VFPV5,
0136   VFPV5_FULLFP16,
0137 };
0138
0139 // An FPU name restricts the FPU in one of three ways:
0140 enum class FPURestriction {
0141   None = 0, ///< No restriction
0142   D16,      ///< Only 16 D registers
0143   SP_D16    ///< Only single-precision instructions, with 16 D registers
0144 };
0145
0146 inline bool isDoublePrecision(const FPURestriction restriction) {
0147   return restriction != FPURestriction::SP_D16;
0148 }
0149
0150 inline bool has32Regs(const FPURestriction restriction) {
0151   return restriction == FPURestriction::None;
0152 }
0153
0154 // An FPU name implies one of three levels of Neon support:
0155 enum class NeonSupportLevel {
0156   None = 0, ///< No Neon
0157   Neon,     ///< Neon
0158   Crypto    ///< Neon with Crypto
0159 };
0160
0161 // v6/v7/v8 Profile
0162 enum class ProfileKind { INVALID = 0, A, R, M };
0163
0164 // List of canonical FPU names (use getFPUSynonym) and which architectural
0165 // features they correspond to (use getFPUFeatures).
0166 // The entries must appear in the order listed in ARM::FPUKind for correct
0167 // indexing
0168 struct FPUName {
0169   StringRef Name;
0170   FPUKind ID;
0171   FPUVersion FPUVer;
0172   NeonSupportLevel NeonSupport;
0173   FPURestriction Restriction;
0174 };
0175
0176 static const FPUName FPUNames[] = {
0177 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                \
0178   {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
0179 #include "llvm/TargetParser/ARMTargetParser.def"
0180 };
0181
0182 // List of canonical arch names (use getArchSynonym).
0183 // This table also provides the build attribute fields for CPU arch
0184 // and Arch ID, according to the Addenda to the ARM ABI, chapters
0185 // 2.4 and 2.3.5.2 respectively.
0186 // FIXME: SubArch values were simplified to fit into the expectations
0187 // of the triples and are not conforming with their official names.
0188 // Check to see if the expectation should be changed.
0189 struct ArchNames {
0190   StringRef Name;
0191   StringRef CPUAttr; // CPU class in build attributes.
0192   StringRef ArchFeature;
0193   FPUKind DefaultFPU;
0194   uint64_t ArchBaseExtensions;
0195   ArchKind ID;
0196   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
0197
0198   // Return ArchFeature without the leading "+".
0199   StringRef getSubArch() const { return ArchFeature.substr(1); }
0200 };
0201
0202 static const ArchNames ARMArchNames[] = {
0203 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
0204                  ARCH_BASE_EXT)                                                \
0205   {NAME,          CPU_ATTR,     ARCH_FEATURE, ARCH_FPU,                        \
0206    ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
0207 #include "llvm/TargetParser/ARMTargetParser.def"
0208 };
0209
0210 inline ArchKind &operator--(ArchKind &Kind) {
0211   assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
0212          "We only expect operator-- to be called with ARMV8/V9");
0213   if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
0214       Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||
0215       Kind == ArchKind::ARMV8R)
0216     Kind = ArchKind::INVALID;
0217   else {
0218     unsigned KindAsInteger = static_cast<unsigned>(Kind);
0219     Kind = static_cast<ArchKind>(--KindAsInteger);
0220   }
0221   return Kind;
0222 }
0223
0224 // Information by ID
0225 StringRef getFPUName(FPUKind FPUKind);
0226 FPUVersion getFPUVersion(FPUKind FPUKind);
0227 NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind);
0228 FPURestriction getFPURestriction(FPUKind FPUKind);
0229
0230 bool getFPUFeatures(FPUKind FPUKind, std::vector<StringRef> &Features);
0231 bool getHWDivFeatures(uint64_t HWDivKind, std::vector<StringRef> &Features);
0232 bool getExtensionFeatures(uint64_t Extensions,
0233                           std::vector<StringRef> &Features);
0234
0235 StringRef getArchName(ArchKind AK);
0236 unsigned getArchAttr(ArchKind AK);
0237 StringRef getCPUAttr(ArchKind AK);
0238 StringRef getSubArch(ArchKind AK);
0239 StringRef getArchExtName(uint64_t ArchExtKind);
0240 StringRef getArchExtFeature(StringRef ArchExt);
0241 bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt,
0242                            std::vector<StringRef> &Features,
0243                            FPUKind &ArgFPUKind);
0244 ArchKind convertV9toV8(ArchKind AK);
0245
0246 // Information by Name
0247 FPUKind getDefaultFPU(StringRef CPU, ArchKind AK);
0248 uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
0249 StringRef getDefaultCPU(StringRef Arch);
0250 StringRef getCanonicalArchName(StringRef Arch);
0251 StringRef getFPUSynonym(StringRef FPU);
0252
0253 // Parser
0254 uint64_t parseHWDiv(StringRef HWDiv);
0255 FPUKind parseFPU(StringRef FPU);
0256 ArchKind parseArch(StringRef Arch);
0257 uint64_t parseArchExt(StringRef ArchExt);
0258 ArchKind parseCPUArch(StringRef CPU);
0259 ProfileKind parseArchProfile(StringRef Arch);
0260 unsigned parseArchVersion(StringRef Arch);
0261
0262 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
0263 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
0264
0265 /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
0266 ///
0267 /// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
0268 /// string then the triple's arch name is used.
0269 StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch = {});
0270
0271 void PrintSupportedExtensions(StringMap<StringRef> DescMap);
0272
0273 } // namespace ARM
0274 } // namespace llvm
0275
0276 #endif