MCA/Stages/RetireStage.h

0001 //===---------------------- RetireStage.h -----------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// This file defines the retire stage of a default instruction pipeline.
0011 /// The RetireStage represents the process logic that interacts with the
0012 /// simulated RetireControlUnit hardware.
0013 //
0014 //===----------------------------------------------------------------------===//
0015
0016 #ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
0017 #define LLVM_MCA_STAGES_RETIRESTAGE_H
0018
0019 #include "llvm/ADT/SmallVector.h"
0020 #include "llvm/MCA/HardwareUnits/LSUnit.h"
0021 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
0022 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
0023 #include "llvm/MCA/Stages/Stage.h"
0024
0025 namespace llvm {
0026 namespace mca {
0027
0028 class RetireStage final : public Stage {
0029   // Owner will go away when we move listeners/eventing to the stages.
0030   RetireControlUnit &RCU;
0031   RegisterFile &PRF;
0032   LSUnitBase &LSU;
0033
0034   RetireStage(const RetireStage &Other) = delete;
0035   RetireStage &operator=(const RetireStage &Other) = delete;
0036
0037 public:
0038   RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
0039       : RCU(R), PRF(F), LSU(LS) {}
0040
0041   bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
0042   Error cycleStart() override;
0043   Error cycleEnd() override;
0044   Error execute(InstRef &IR) override;
0045   void notifyInstructionRetired(const InstRef &IR) const;
0046 };
0047
0048 } // namespace mca
0049 } // namespace llvm
0050
0051 #endif // LLVM_MCA_STAGES_RETIRESTAGE_H