MCA/Stages/InOrderIssueStage.h

0001 //===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// InOrderIssueStage implements an in-order execution pipeline.
0011 ///
0012 //===----------------------------------------------------------------------===//
0013
0014 #ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H
0015 #define LLVM_MCA_STAGES_INORDERISSUESTAGE_H
0016
0017 #include "llvm/MCA/CustomBehaviour.h"
0018 #include "llvm/MCA/HardwareUnits/ResourceManager.h"
0019 #include "llvm/MCA/SourceMgr.h"
0020 #include "llvm/MCA/Stages/Stage.h"
0021
0022 namespace llvm {
0023 namespace mca {
0024 class LSUnitBase;
0025 class RegisterFile;
0026
0027 struct StallInfo {
0028   enum class StallKind {
0029     DEFAULT,
0030     REGISTER_DEPS,
0031     DISPATCH,
0032     DELAY,
0033     LOAD_STORE,
0034     CUSTOM_STALL
0035   };
0036
0037   InstRef IR;
0038   unsigned CyclesLeft = 0;
0039   StallKind Kind = StallKind::DEFAULT;
0040
0041   StallInfo() = default;
0042
0043   StallKind getStallKind() const { return Kind; }
0044   unsigned getCyclesLeft() const { return CyclesLeft; }
0045   const InstRef &getInstruction() const { return IR; }
0046   InstRef &getInstruction() { return IR; }
0047
0048   bool isValid() const { return (bool)IR; }
0049   void clear();
0050   void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
0051   void cycleEnd();
0052 };
0053
0054 class InOrderIssueStage final : public Stage {
0055   const MCSubtargetInfo &STI;
0056   RegisterFile &PRF;
0057   ResourceManager RM;
0058   CustomBehaviour &CB;
0059   LSUnitBase &LSU;
0060
0061   /// Instructions that were issued, but not executed yet.
0062   SmallVector<InstRef, 4> IssuedInst;
0063
0064   /// Number of instructions issued in the current cycle.
0065   unsigned NumIssued;
0066
0067   StallInfo SI;
0068
0069   /// Instruction that is issued in more than 1 cycle.
0070   InstRef CarriedOver;
0071   /// Number of CarriedOver uops left to issue.
0072   unsigned CarryOver;
0073
0074   /// Number of instructions that can be issued in the current cycle.
0075   unsigned Bandwidth;
0076
0077   /// Number of cycles (counted from the current cycle) until the last write is
0078   /// committed. This is taken into account to ensure that writes commit in the
0079   /// program order.
0080   unsigned LastWriteBackCycle;
0081
0082   InOrderIssueStage(const InOrderIssueStage &Other) = delete;
0083   InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
0084
0085   /// Returns true if IR can execute during this cycle.
0086   /// In case of stall, it updates SI with information about the stalled
0087   /// instruction and the stall reason.
0088   bool canExecute(const InstRef &IR);
0089
0090   /// Issue the instruction, or update the StallInfo.
0091   Error tryIssue(InstRef &IR);
0092
0093   /// Update status of instructions from IssuedInst.
0094   void updateIssuedInst();
0095
0096   /// Continue to issue the CarriedOver instruction.
0097   void updateCarriedOver();
0098
0099   /// Notifies a stall event to the Stage listener. Stall information is
0100   /// obtained from the internal StallInfo field.
0101   void notifyStallEvent();
0102
0103   void notifyInstructionIssued(const InstRef &IR,
0104                                ArrayRef<ResourceUse> UsedRes);
0105   void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
0106                                    ArrayRef<unsigned> UsedRegs);
0107   void notifyInstructionExecuted(const InstRef &IR);
0108   void notifyInstructionRetired(const InstRef &IR,
0109                                 ArrayRef<unsigned> FreedRegs);
0110
0111   /// Retire instruction once it is executed.
0112   void retireInstruction(InstRef &IR);
0113
0114 public:
0115   InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
0116                     CustomBehaviour &CB, LSUnitBase &LSU);
0117
0118   unsigned getIssueWidth() const;
0119   bool isAvailable(const InstRef &) const override;
0120   bool hasWorkToComplete() const override;
0121   Error execute(InstRef &IR) override;
0122   Error cycleStart() override;
0123   Error cycleEnd() override;
0124 };
0125
0126 } // namespace mca
0127 } // namespace llvm
0128
0129 #endif // LLVM_MCA_STAGES_INORDERISSUESTAGE_H