MCA/Stages/ExecuteStage.h

0001 //===---------------------- ExecuteStage.h ----------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// This file defines the execution stage of a default instruction pipeline.
0011 ///
0012 /// The ExecuteStage is responsible for managing the hardware scheduler
0013 /// and issuing notifications that an instruction has been executed.
0014 ///
0015 //===----------------------------------------------------------------------===//
0016
0017 #ifndef LLVM_MCA_STAGES_EXECUTESTAGE_H
0018 #define LLVM_MCA_STAGES_EXECUTESTAGE_H
0019
0020 #include "llvm/ADT/ArrayRef.h"
0021 #include "llvm/MCA/HardwareUnits/Scheduler.h"
0022 #include "llvm/MCA/Instruction.h"
0023 #include "llvm/MCA/Stages/Stage.h"
0024
0025 namespace llvm {
0026 namespace mca {
0027
0028 class ExecuteStage final : public Stage {
0029   Scheduler &HWS;
0030
0031   unsigned NumDispatchedOpcodes;
0032   unsigned NumIssuedOpcodes;
0033
0034   // True if this stage should notify listeners of HWPressureEvents.
0035   bool EnablePressureEvents;
0036
0037   Error issueInstruction(InstRef &IR);
0038
0039   // Called at the beginning of each cycle to issue already dispatched
0040   // instructions to the underlying pipelines.
0041   Error issueReadyInstructions();
0042
0043   // Used to notify instructions eliminated at register renaming stage.
0044   Error handleInstructionEliminated(InstRef &IR);
0045
0046   ExecuteStage(const ExecuteStage &Other) = delete;
0047   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
0048
0049 public:
0050   ExecuteStage(Scheduler &S) : ExecuteStage(S, false) {}
0051   ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)
0052       : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),
0053         EnablePressureEvents(ShouldPerformBottleneckAnalysis) {}
0054
0055   // This stage works under the assumption that the Pipeline will eventually
0056   // execute a retire stage. We don't need to check if pipelines and/or
0057   // schedulers have instructions to process, because those instructions are
0058   // also tracked by the retire control unit. That means,
0059   // RetireControlUnit::hasWorkToComplete() is responsible for checking if there
0060   // are still instructions in-flight in the out-of-order backend.
0061   bool hasWorkToComplete() const override { return false; }
0062   bool isAvailable(const InstRef &IR) const override;
0063
0064   // Notifies the scheduler that a new cycle just started.
0065   //
0066   // This method notifies the scheduler that a new cycle started.
0067   // This method is also responsible for notifying listeners about instructions
0068   // state changes, and processor resources freed by the scheduler.
0069   // Instructions that transitioned to the 'Executed' state are automatically
0070   // moved to the next stage (i.e. RetireStage).
0071   Error cycleStart() override;
0072   Error cycleEnd() override;
0073   Error execute(InstRef &IR) override;
0074
0075   void notifyInstructionIssued(const InstRef &IR,
0076                                MutableArrayRef<ResourceUse> Used) const;
0077   void notifyInstructionExecuted(const InstRef &IR) const;
0078   void notifyInstructionPending(const InstRef &IR) const;
0079   void notifyInstructionReady(const InstRef &IR) const;
0080   void notifyResourceAvailable(const ResourceRef &RR) const;
0081
0082   // Notify listeners that buffered resources have been consumed or freed.
0083   void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
0084 };
0085
0086 } // namespace mca
0087 } // namespace llvm
0088
0089 #endif // LLVM_MCA_STAGES_EXECUTESTAGE_H