MCA/Stages/DispatchStage.h

0001 //===----------------------- DispatchStage.h --------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 /// \file
0009 ///
0010 /// This file models the dispatch component of an instruction pipeline.
0011 ///
0012 /// The DispatchStage is responsible for updating instruction dependencies
0013 /// and communicating to the simulated instruction scheduler that an instruction
0014 /// is ready to be scheduled for execution.
0015 ///
0016 //===----------------------------------------------------------------------===//
0017
0018 #ifndef LLVM_MCA_STAGES_DISPATCHSTAGE_H
0019 #define LLVM_MCA_STAGES_DISPATCHSTAGE_H
0020
0021 #include "llvm/MC/MCRegisterInfo.h"
0022 #include "llvm/MC/MCSubtargetInfo.h"
0023 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
0024 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
0025 #include "llvm/MCA/Instruction.h"
0026 #include "llvm/MCA/Stages/Stage.h"
0027
0028 namespace llvm {
0029 namespace mca {
0030
0031 // Implements the hardware dispatch logic.
0032 //
0033 // This class is responsible for the dispatch stage, in which instructions are
0034 // dispatched in groups to the Scheduler.  An instruction can be dispatched if
0035 // the following conditions are met:
0036 //  1) There are enough entries in the reorder buffer (see class
0037 //     RetireControlUnit) to write the opcodes associated with the instruction.
0038 //  2) There are enough physical registers to rename output register operands.
0039 //  3) There are enough entries available in the used buffered resource(s).
0040 //
0041 // The number of micro opcodes that can be dispatched in one cycle is limited by
0042 // the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when
0043 // processor resources are not available. Dispatch stall events are counted
0044 // during the entire execution of the code, and displayed by the performance
0045 // report when flag '-dispatch-stats' is specified.
0046 //
0047 // If the number of micro opcodes exceedes DispatchWidth, then the instruction
0048 // is dispatched in multiple cycles.
0049 class DispatchStage final : public Stage {
0050   unsigned DispatchWidth;
0051   unsigned AvailableEntries;
0052   unsigned CarryOver;
0053   InstRef CarriedOver;
0054   const MCSubtargetInfo &STI;
0055   RetireControlUnit &RCU;
0056   RegisterFile &PRF;
0057
0058   bool checkRCU(const InstRef &IR) const;
0059   bool checkPRF(const InstRef &IR) const;
0060   bool canDispatch(const InstRef &IR) const;
0061   Error dispatch(InstRef IR);
0062
0063   void notifyInstructionDispatched(const InstRef &IR,
0064                                    ArrayRef<unsigned> UsedPhysRegs,
0065                                    unsigned uOps) const;
0066
0067 public:
0068   DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI,
0069                 unsigned MaxDispatchWidth, RetireControlUnit &R,
0070                 RegisterFile &F);
0071
0072   bool isAvailable(const InstRef &IR) const override;
0073
0074   // The dispatch logic internally doesn't buffer instructions. So there is
0075   // never work to do at the beginning of every cycle.
0076   bool hasWorkToComplete() const override { return false; }
0077   Error cycleStart() override;
0078   Error execute(InstRef &IR) override;
0079
0080 #ifndef NDEBUG
0081   void dump() const;
0082 #endif
0083 };
0084 } // namespace mca
0085 } // namespace llvm
0086
0087 #endif // LLVM_MCA_STAGES_DISPATCHSTAGE_H