Warning, /include/llvm/IR/VPIntrinsics.def is written in an unsupported language. File is not indexed.
0001 //===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file contains descriptions of the various Vector Predication intrinsics.
0010 // This is used as a central place for enumerating the different instructions
0011 // and should eventually be the place to put comments about the instructions.
0012 //
0013 //===----------------------------------------------------------------------===//
0014
0015 // NOTE: NO INCLUDE GUARD DESIRED!
0016
0017 // Provide definitions of macros so that users of this file do not have to
0018 // define everything to use it...
0019 //
0020 // Register a VP intrinsic and begin its property scope.
0021 // All VP intrinsic scopes are top level, ie it is illegal to place a
0022 // BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope.
0023 // \p VPID The VP intrinsic id.
0024 // \p MASKPOS The mask operand position.
0025 // \p EVLPOS The explicit vector length operand position.
0026 #ifndef BEGIN_REGISTER_VP_INTRINSIC
0027 #define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS)
0028 #endif
0029
0030 // End the property scope of a VP intrinsic.
0031 #ifndef END_REGISTER_VP_INTRINSIC
0032 #define END_REGISTER_VP_INTRINSIC(VPID)
0033 #endif
0034
0035 // Register a new VP SDNode and begin its property scope.
0036 // When the SDNode scope is nested within a VP intrinsic scope, it is
0037 // implicitly registered as the canonical SDNode for this VP intrinsic. There
0038 // is one VP intrinsic that maps directly to one SDNode that goes by the
0039 // same name. Since the operands are also the same, we open the property
0040 // scopes for both the VPIntrinsic and the SDNode at once.
0041 // \p VPSD The SelectionDAG Node id (eg VP_ADD).
0042 // \p LEGALPOS The operand position of the SDNode that is used for legalizing.
0043 // If LEGALPOS < 0, then the return type given by
0044 // TheNode->getValueType(-1-LEGALPOS) is used.
0045 // \p TDNAME The name of the TableGen definition of this SDNode.
0046 // \p MASKPOS The mask operand position.
0047 // \p EVLPOS The explicit vector length operand position.
0048 #ifndef BEGIN_REGISTER_VP_SDNODE
0049 #define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS)
0050 #endif
0051
0052 // End the property scope of a new VP SDNode.
0053 #ifndef END_REGISTER_VP_SDNODE
0054 #define END_REGISTER_VP_SDNODE(VPSD)
0055 #endif
0056
0057 // Helper macro to set up the mapping from VP intrinsic to ISD opcode.
0058 // Note: More than one VP intrinsic may map to one ISD opcode.
0059 #ifndef HELPER_MAP_VPID_TO_VPSD
0060 #define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
0061 #endif
0062
0063 // Helper macros for the common "1:1 - Intrinsic : SDNode" case.
0064 //
0065 // There is one VP intrinsic that maps directly to one SDNode that goes by the
0066 // same name. Since the operands are also the same, we open the property
0067 // scopes for both the VPIntrinsic and the SDNode at once.
0068 //
0069 // \p VPID The canonical name (eg `vp_add`, which at the same time is the
0070 // name of the intrinsic and the TableGen def of the SDNode).
0071 // \p MASKPOS The mask operand position.
0072 // \p EVLPOS The explicit vector length operand position.
0073 // \p VPSD The SelectionDAG Node id (eg VP_ADD).
0074 // \p LEGALPOS The operand position of the SDNode that is used for legalizing
0075 // this SDNode. This can be `-1`, in which case the return type of
0076 // the SDNode is used.
0077 #define BEGIN_REGISTER_VP(VPID, MASKPOS, EVLPOS, VPSD, LEGALPOS) \
0078 BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS) \
0079 BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, VPID, MASKPOS, EVLPOS) \
0080 HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
0081
0082 #define END_REGISTER_VP(VPID, VPSD) \
0083 END_REGISTER_VP_INTRINSIC(VPID) \
0084 END_REGISTER_VP_SDNODE(VPSD)
0085
0086 // The following macros attach properties to the scope they are placed in. This
0087 // assigns the property to the VP Intrinsic and/or SDNode that belongs to the
0088 // scope.
0089 //
0090 // Property Macros {
0091
0092 // The intrinsic and/or SDNode has the same function as this LLVM IR Opcode.
0093 // \p OPC The opcode of the instruction with the same function.
0094 #ifndef VP_PROPERTY_FUNCTIONAL_OPC
0095 #define VP_PROPERTY_FUNCTIONAL_OPC(OPC)
0096 #endif
0097
0098 // If operation can have rounding or fp exceptions, maps to corresponding
0099 // constrained fp intrinsic.
0100 #ifndef VP_PROPERTY_CONSTRAINEDFP
0101 #define VP_PROPERTY_CONSTRAINEDFP(INTRINID)
0102 #endif
0103
0104 // The intrinsic and/or SDNode has the same function as this ISD Opcode.
0105 // \p SDOPC The opcode of the instruction with the same function.
0106 #ifndef VP_PROPERTY_FUNCTIONAL_SDOPC
0107 #define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC)
0108 #endif
0109
0110 // Map this VP intrinsic to its canonical functional intrinsic.
0111 // \p INTRIN The non-VP intrinsics with the same function.
0112 #ifndef VP_PROPERTY_FUNCTIONAL_INTRINSIC
0113 #define VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN)
0114 #endif
0115
0116 // This VP Intrinsic has no functionally-equivalent non-VP opcode or intrinsic.
0117 #ifndef VP_PROPERTY_NO_FUNCTIONAL
0118 #define VP_PROPERTY_NO_FUNCTIONAL
0119 #endif
0120
0121 // A property to infer VP binary-op SDNode opcodes automatically.
0122 #ifndef VP_PROPERTY_BINARYOP
0123 #define VP_PROPERTY_BINARYOP
0124 #endif
0125
0126 /// } Property Macros
0127
0128 ///// Integer Arithmetic {
0129
0130 // Specialized helper macro for integer binary operators (%x, %y, %mask, %evl).
0131 #ifdef HELPER_REGISTER_BINARY_INT_VP
0132 #error \
0133 "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
0134 #endif
0135 #define HELPER_REGISTER_BINARY_INT_VP(VPID, VPSD, IROPC, SDOPC) \
0136 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, -1) \
0137 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
0138 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0139 VP_PROPERTY_BINARYOP \
0140 END_REGISTER_VP(VPID, VPSD)
0141
0142 // llvm.vp.add(x,y,mask,vlen)
0143 HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD)
0144
0145 // llvm.vp.and(x,y,mask,vlen)
0146 HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And, AND)
0147
0148 // llvm.vp.ashr(x,y,mask,vlen)
0149 HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_SRA, AShr, SRA)
0150
0151 // llvm.vp.lshr(x,y,mask,vlen)
0152 HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_SRL, LShr, SRL)
0153
0154 // llvm.vp.mul(x,y,mask,vlen)
0155 HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL)
0156
0157 // llvm.vp.or(x,y,mask,vlen)
0158 HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or, OR)
0159
0160 // llvm.vp.sdiv(x,y,mask,vlen)
0161 HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
0162
0163 // llvm.vp.shl(x,y,mask,vlen)
0164 HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl, SHL)
0165
0166 // llvm.vp.srem(x,y,mask,vlen)
0167 HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
0168
0169 // llvm.vp.sub(x,y,mask,vlen)
0170 HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub, SUB)
0171
0172 // llvm.vp.udiv(x,y,mask,vlen)
0173 HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv, UDIV)
0174
0175 // llvm.vp.urem(x,y,mask,vlen)
0176 HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
0177
0178 // llvm.vp.xor(x,y,mask,vlen)
0179 HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR)
0180
0181 #undef HELPER_REGISTER_BINARY_INT_VP
0182
0183 // llvm.vp.smin(x,y,mask,vlen)
0184 BEGIN_REGISTER_VP(vp_smin, 2, 3, VP_SMIN, -1)
0185 VP_PROPERTY_BINARYOP
0186 VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
0187 VP_PROPERTY_FUNCTIONAL_INTRINSIC(smin)
0188 END_REGISTER_VP(vp_smin, VP_SMIN)
0189
0190 // llvm.vp.smax(x,y,mask,vlen)
0191 BEGIN_REGISTER_VP(vp_smax, 2, 3, VP_SMAX, -1)
0192 VP_PROPERTY_BINARYOP
0193 VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX)
0194 VP_PROPERTY_FUNCTIONAL_INTRINSIC(smax)
0195 END_REGISTER_VP(vp_smax, VP_SMAX)
0196
0197 // llvm.vp.umin(x,y,mask,vlen)
0198 BEGIN_REGISTER_VP(vp_umin, 2, 3, VP_UMIN, -1)
0199 VP_PROPERTY_BINARYOP
0200 VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
0201 VP_PROPERTY_FUNCTIONAL_INTRINSIC(umin)
0202 END_REGISTER_VP(vp_umin, VP_UMIN)
0203
0204 // llvm.vp.umax(x,y,mask,vlen)
0205 BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1)
0206 VP_PROPERTY_BINARYOP
0207 VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
0208 VP_PROPERTY_FUNCTIONAL_INTRINSIC(umax)
0209 END_REGISTER_VP(vp_umax, VP_UMAX)
0210
0211 // llvm.vp.abs(x,is_int_min_poison,mask,vlen)
0212 BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3)
0213 BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2)
0214 HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS)
0215 VP_PROPERTY_FUNCTIONAL_INTRINSIC(abs)
0216 VP_PROPERTY_FUNCTIONAL_SDOPC(ABS)
0217 END_REGISTER_VP(vp_abs, VP_ABS)
0218
0219 // llvm.vp.bswap(x,mask,vlen)
0220 BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1)
0221 VP_PROPERTY_FUNCTIONAL_INTRINSIC(bswap)
0222 VP_PROPERTY_FUNCTIONAL_SDOPC(BSWAP)
0223 END_REGISTER_VP(vp_bswap, VP_BSWAP)
0224
0225 // llvm.vp.bitreverse(x,mask,vlen)
0226 BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1)
0227 VP_PROPERTY_FUNCTIONAL_INTRINSIC(bitreverse)
0228 VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE)
0229 END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE)
0230
0231 // llvm.vp.ctpop(x,mask,vlen)
0232 BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1)
0233 VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctpop)
0234 VP_PROPERTY_FUNCTIONAL_SDOPC(CTPOP)
0235 END_REGISTER_VP(vp_ctpop, VP_CTPOP)
0236
0237 // llvm.vp.ctlz(x,is_zero_poison,mask,vlen)
0238 BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3)
0239 BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
0240 VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz)
0241 VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
0242 END_REGISTER_VP_SDNODE(VP_CTLZ)
0243 BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2)
0244 VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_UNDEF)
0245 END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF)
0246 END_REGISTER_VP_INTRINSIC(vp_ctlz)
0247
0248 // llvm.vp.cttz(x,is_zero_poison,mask,vlen)
0249 BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3)
0250 BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
0251 VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz)
0252 VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
0253 END_REGISTER_VP_SDNODE(VP_CTTZ)
0254 BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2)
0255 END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF)
0256 END_REGISTER_VP_INTRINSIC(vp_cttz)
0257
0258 // llvm.vp.cttz.elts(x,is_zero_poison,mask,vl)
0259 BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3)
0260 VP_PROPERTY_NO_FUNCTIONAL
0261 BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS, 0, vp_cttz_elts, 1, 2)
0262 END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS)
0263 BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF, 0, vp_cttz_elts_zero_undef, 1, 2)
0264 END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF)
0265 END_REGISTER_VP_INTRINSIC(vp_cttz_elts)
0266
0267 // llvm.vp.fshl(x,y,z,mask,vlen)
0268 BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1)
0269 VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshl)
0270 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
0271 END_REGISTER_VP(vp_fshl, VP_FSHL)
0272
0273 // llvm.vp.fshr(x,y,z,mask,vlen)
0274 BEGIN_REGISTER_VP(vp_fshr, 3, 4, VP_FSHR, -1)
0275 VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshr)
0276 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
0277 END_REGISTER_VP(vp_fshr, VP_FSHR)
0278
0279 // llvm.vp.sadd.sat(x,y,mask,vlen)
0280 BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1)
0281 VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat)
0282 VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
0283 END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT)
0284
0285 // llvm.vp.uadd.sat(x,y,mask,vlen)
0286 BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1)
0287 VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat)
0288 VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
0289 END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT)
0290
0291 // llvm.vp.ssub.sat(x,y,mask,vlen)
0292 BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1)
0293 VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat)
0294 VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
0295 END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT)
0296
0297 // llvm.vp.usub.sat(x,y,mask,vlen)
0298 BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1)
0299 VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat)
0300 VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
0301 END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
0302 ///// } Integer Arithmetic
0303
0304 ///// Floating-Point Arithmetic {
0305
0306 // Specialized helper macro for floating-point binary operators
0307 // <operation>(%x, %y, %mask, %evl).
0308 #ifdef HELPER_REGISTER_BINARY_FP_VP
0309 #error \
0310 "The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!"
0311 #endif
0312 #define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
0313 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 2, 3, VPSD, -1) \
0314 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
0315 VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
0316 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0317 VP_PROPERTY_BINARYOP \
0318 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
0319
0320 // llvm.vp.fadd(x,y,mask,vlen)
0321 HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD)
0322
0323 // llvm.vp.fsub(x,y,mask,vlen)
0324 HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub, FSUB)
0325
0326 // llvm.vp.fmul(x,y,mask,vlen)
0327 HELPER_REGISTER_BINARY_FP_VP(fmul, VP_FMUL, FMul, FMUL)
0328
0329 // llvm.vp.fdiv(x,y,mask,vlen)
0330 HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
0331
0332 // llvm.vp.frem(x,y,mask,vlen)
0333 HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
0334
0335 #undef HELPER_REGISTER_BINARY_FP_VP
0336
0337 // llvm.vp.fneg(x,mask,vlen)
0338 BEGIN_REGISTER_VP(vp_fneg, 1, 2, VP_FNEG, -1)
0339 VP_PROPERTY_FUNCTIONAL_OPC(FNeg)
0340 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
0341 END_REGISTER_VP(vp_fneg, VP_FNEG)
0342
0343 // llvm.vp.fabs(x,mask,vlen)
0344 BEGIN_REGISTER_VP(vp_fabs, 1, 2, VP_FABS, -1)
0345 VP_PROPERTY_FUNCTIONAL_INTRINSIC(fabs)
0346 VP_PROPERTY_FUNCTIONAL_SDOPC(FABS)
0347 END_REGISTER_VP(vp_fabs, VP_FABS)
0348
0349 // llvm.vp.sqrt(x,mask,vlen)
0350 BEGIN_REGISTER_VP(vp_sqrt, 1, 2, VP_SQRT, -1)
0351 VP_PROPERTY_FUNCTIONAL_INTRINSIC(sqrt)
0352 VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
0353 END_REGISTER_VP(vp_sqrt, VP_SQRT)
0354
0355 // llvm.vp.fma(x,y,z,mask,vlen)
0356 BEGIN_REGISTER_VP(vp_fma, 3, 4, VP_FMA, -1)
0357 VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fma)
0358 VP_PROPERTY_FUNCTIONAL_INTRINSIC(fma)
0359 VP_PROPERTY_FUNCTIONAL_SDOPC(FMA)
0360 END_REGISTER_VP(vp_fma, VP_FMA)
0361
0362 // llvm.vp.fmuladd(x,y,z,mask,vlen)
0363 BEGIN_REGISTER_VP(vp_fmuladd, 3, 4, VP_FMULADD, -1)
0364 VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fmuladd)
0365 VP_PROPERTY_FUNCTIONAL_INTRINSIC(fmuladd)
0366 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
0367 END_REGISTER_VP(vp_fmuladd, VP_FMULADD)
0368
0369 // llvm.vp.copysign(x,y,mask,vlen)
0370 BEGIN_REGISTER_VP(vp_copysign, 2, 3, VP_FCOPYSIGN, -1)
0371 VP_PROPERTY_BINARYOP
0372 VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN)
0373 VP_PROPERTY_FUNCTIONAL_INTRINSIC(copysign)
0374 END_REGISTER_VP(vp_copysign, VP_FCOPYSIGN)
0375
0376 // llvm.vp.minnum(x,y,mask,vlen)
0377 BEGIN_REGISTER_VP(vp_minnum, 2, 3, VP_FMINNUM, -1)
0378 VP_PROPERTY_BINARYOP
0379 VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM)
0380 VP_PROPERTY_FUNCTIONAL_INTRINSIC(minnum)
0381 END_REGISTER_VP(vp_minnum, VP_FMINNUM)
0382
0383 // llvm.vp.maxnum(x,y,mask,vlen)
0384 BEGIN_REGISTER_VP(vp_maxnum, 2, 3, VP_FMAXNUM, -1)
0385 VP_PROPERTY_BINARYOP
0386 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
0387 VP_PROPERTY_FUNCTIONAL_INTRINSIC(maxnum)
0388 END_REGISTER_VP(vp_maxnum, VP_FMAXNUM)
0389
0390 // llvm.vp.minimum(x,y,mask,vlen)
0391 BEGIN_REGISTER_VP(vp_minimum, 2, 3, VP_FMINIMUM, -1)
0392 VP_PROPERTY_BINARYOP
0393 VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM)
0394 VP_PROPERTY_FUNCTIONAL_INTRINSIC(minimum)
0395 END_REGISTER_VP(vp_minimum, VP_FMINIMUM)
0396
0397 // llvm.vp.maximum(x,y,mask,vlen)
0398 BEGIN_REGISTER_VP(vp_maximum, 2, 3, VP_FMAXIMUM, -1)
0399 VP_PROPERTY_BINARYOP
0400 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM)
0401 VP_PROPERTY_FUNCTIONAL_INTRINSIC(maximum)
0402 END_REGISTER_VP(vp_maximum, VP_FMAXIMUM)
0403
0404 // llvm.vp.ceil(x,mask,vlen)
0405 BEGIN_REGISTER_VP(vp_ceil, 1, 2, VP_FCEIL, -1)
0406 VP_PROPERTY_FUNCTIONAL_INTRINSIC(ceil)
0407 VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL)
0408 END_REGISTER_VP(vp_ceil, VP_FCEIL)
0409
0410 // llvm.vp.floor(x,mask,vlen)
0411 BEGIN_REGISTER_VP(vp_floor, 1, 2, VP_FFLOOR, -1)
0412 VP_PROPERTY_FUNCTIONAL_INTRINSIC(floor)
0413 VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
0414 END_REGISTER_VP(vp_floor, VP_FFLOOR)
0415
0416 // llvm.vp.round(x,mask,vlen)
0417 BEGIN_REGISTER_VP(vp_round, 1, 2, VP_FROUND, -1)
0418 VP_PROPERTY_FUNCTIONAL_INTRINSIC(round)
0419 VP_PROPERTY_FUNCTIONAL_SDOPC(FROUND)
0420 END_REGISTER_VP(vp_round, VP_FROUND)
0421
0422 // llvm.vp.roundeven(x,mask,vlen)
0423 BEGIN_REGISTER_VP(vp_roundeven, 1, 2, VP_FROUNDEVEN, -1)
0424 VP_PROPERTY_FUNCTIONAL_INTRINSIC(roundeven)
0425 VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN)
0426 END_REGISTER_VP(vp_roundeven, VP_FROUNDEVEN)
0427
0428 // llvm.vp.roundtozero(x,mask,vlen)
0429 BEGIN_REGISTER_VP(vp_roundtozero, 1, 2, VP_FROUNDTOZERO, -1)
0430 VP_PROPERTY_FUNCTIONAL_INTRINSIC(trunc)
0431 VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC)
0432 END_REGISTER_VP(vp_roundtozero, VP_FROUNDTOZERO)
0433
0434 // llvm.vp.rint(x,mask,vlen)
0435 BEGIN_REGISTER_VP(vp_rint, 1, 2, VP_FRINT, -1)
0436 VP_PROPERTY_FUNCTIONAL_INTRINSIC(rint)
0437 VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT)
0438 END_REGISTER_VP(vp_rint, VP_FRINT)
0439
0440 // llvm.vp.nearbyint(x,mask,vlen)
0441 BEGIN_REGISTER_VP(vp_nearbyint, 1, 2, VP_FNEARBYINT, -1)
0442 VP_PROPERTY_FUNCTIONAL_INTRINSIC(nearbyint)
0443 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
0444 END_REGISTER_VP(vp_nearbyint, VP_FNEARBYINT)
0445
0446 // llvm.vp.lrint(x,mask,vlen)
0447 BEGIN_REGISTER_VP(vp_lrint, 1, 2, VP_LRINT, 0)
0448 VP_PROPERTY_FUNCTIONAL_INTRINSIC(lrint)
0449 VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
0450 END_REGISTER_VP(vp_lrint, VP_LRINT)
0451
0452 // llvm.vp.llrint(x,mask,vlen)
0453 BEGIN_REGISTER_VP(vp_llrint, 1, 2, VP_LLRINT, 0)
0454 VP_PROPERTY_FUNCTIONAL_INTRINSIC(llrint)
0455 VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
0456 END_REGISTER_VP(vp_llrint, VP_LLRINT)
0457
0458 ///// } Floating-Point Arithmetic
0459
0460 ///// Type Casts {
0461 // Specialized helper macro for type conversions.
0462 // <operation>(%x, %mask, %evl).
0463 #ifdef HELPER_REGISTER_FP_CAST_VP
0464 #error \
0465 "The internal helper macro HELPER_REGISTER_FP_CAST_VP is already defined!"
0466 #endif
0467 #define HELPER_REGISTER_FP_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
0468 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
0469 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
0470 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0471 VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
0472 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
0473
0474 // llvm.vp.fptoui(x,mask,vlen)
0475 HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, FP_TO_UINT)
0476
0477 // llvm.vp.fptosi(x,mask,vlen)
0478 HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT)
0479
0480 // llvm.vp.uitofp(x,mask,vlen)
0481 HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP)
0482
0483 // llvm.vp.sitofp(x,mask,vlen)
0484 HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP)
0485
0486 // llvm.vp.fptrunc(x,mask,vlen)
0487 HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND)
0488
0489 // llvm.vp.fpext(x,mask,vlen)
0490 HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND)
0491
0492 #undef HELPER_REGISTER_FP_CAST_VP
0493
0494 // Specialized helper macro for integer type conversions.
0495 // <operation>(%x, %mask, %evl).
0496 #ifdef HELPER_REGISTER_INT_CAST_VP
0497 #error \
0498 "The internal helper macro HELPER_REGISTER_INT_CAST_VP is already defined!"
0499 #endif
0500 #define HELPER_REGISTER_INT_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
0501 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
0502 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
0503 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0504 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
0505
0506 // llvm.vp.trunc(x,mask,vlen)
0507 HELPER_REGISTER_INT_CAST_VP(trunc, VP_TRUNCATE, Trunc, TRUNCATE)
0508
0509 // llvm.vp.zext(x,mask,vlen)
0510 HELPER_REGISTER_INT_CAST_VP(zext, VP_ZERO_EXTEND, ZExt, ZERO_EXTEND)
0511
0512 // llvm.vp.sext(x,mask,vlen)
0513 HELPER_REGISTER_INT_CAST_VP(sext, VP_SIGN_EXTEND, SExt, SIGN_EXTEND)
0514
0515 // llvm.vp.ptrtoint(x,mask,vlen)
0516 BEGIN_REGISTER_VP(vp_ptrtoint, 1, 2, VP_PTRTOINT, -1)
0517 VP_PROPERTY_FUNCTIONAL_OPC(PtrToInt)
0518 END_REGISTER_VP(vp_ptrtoint, VP_PTRTOINT)
0519
0520 // llvm.vp.inttoptr(x,mask,vlen)
0521 BEGIN_REGISTER_VP(vp_inttoptr, 1, 2, VP_INTTOPTR, -1)
0522 VP_PROPERTY_FUNCTIONAL_OPC(IntToPtr)
0523 END_REGISTER_VP(vp_inttoptr, VP_INTTOPTR)
0524
0525 #undef HELPER_REGISTER_INT_CAST_VP
0526
0527 ///// } Type Casts
0528
0529 ///// Comparisons {
0530
0531 // VP_SETCC (ISel only)
0532 BEGIN_REGISTER_VP_SDNODE(VP_SETCC, 0, vp_setcc, 3, 4)
0533 END_REGISTER_VP_SDNODE(VP_SETCC)
0534
0535 // llvm.vp.fcmp(x,y,cc,mask,vlen)
0536 BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
0537 HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
0538 VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
0539 VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fcmp)
0540 END_REGISTER_VP_INTRINSIC(vp_fcmp)
0541
0542 // llvm.vp.icmp(x,y,cc,mask,vlen)
0543 BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
0544 HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
0545 VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
0546 END_REGISTER_VP_INTRINSIC(vp_icmp)
0547
0548 ///// } Comparisons
0549
0550 // llvm.vp.is.fpclass(on_true,on_false,mask,vlen)
0551 BEGIN_REGISTER_VP(vp_is_fpclass, 2, 3, VP_IS_FPCLASS, 0)
0552 VP_PROPERTY_FUNCTIONAL_INTRINSIC(is_fpclass)
0553 END_REGISTER_VP(vp_is_fpclass, VP_IS_FPCLASS)
0554
0555 ///// Memory Operations {
0556 // llvm.vp.store(val,ptr,mask,vlen)
0557 BEGIN_REGISTER_VP_INTRINSIC(vp_store, 2, 3)
0558 // chain = VP_STORE chain,val,base,offset,mask,evl
0559 BEGIN_REGISTER_VP_SDNODE(VP_STORE, 1, vp_store, 4, 5)
0560 HELPER_MAP_VPID_TO_VPSD(vp_store, VP_STORE)
0561 VP_PROPERTY_FUNCTIONAL_OPC(Store)
0562 VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_store)
0563 END_REGISTER_VP(vp_store, VP_STORE)
0564
0565 // llvm.experimental.vp.strided.store(val,ptr,stride,mask,vlen)
0566 BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_store, 3, 4)
0567 // chain = EXPERIMENTAL_VP_STRIDED_STORE chain,val,base,offset,stride,mask,evl
0568 VP_PROPERTY_NO_FUNCTIONAL
0569 BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_STORE, 1, experimental_vp_strided_store, 5, 6)
0570 HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE)
0571 END_REGISTER_VP(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE)
0572
0573 // llvm.vp.scatter(ptr,val,mask,vlen)
0574 BEGIN_REGISTER_VP_INTRINSIC(vp_scatter, 2, 3)
0575 // chain = VP_SCATTER chain,val,base,indices,scale,mask,evl
0576 BEGIN_REGISTER_VP_SDNODE(VP_SCATTER, 1, vp_scatter, 5, 6)
0577 HELPER_MAP_VPID_TO_VPSD(vp_scatter, VP_SCATTER)
0578 VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_scatter)
0579 END_REGISTER_VP(vp_scatter, VP_SCATTER)
0580
0581 // llvm.vp.load(ptr,mask,vlen)
0582 BEGIN_REGISTER_VP_INTRINSIC(vp_load, 1, 2)
0583 // val,chain = VP_LOAD chain,base,offset,mask,evl
0584 BEGIN_REGISTER_VP_SDNODE(VP_LOAD, -1, vp_load, 3, 4)
0585 HELPER_MAP_VPID_TO_VPSD(vp_load, VP_LOAD)
0586 VP_PROPERTY_FUNCTIONAL_OPC(Load)
0587 VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_load)
0588 END_REGISTER_VP(vp_load, VP_LOAD)
0589
0590 // llvm.experimental.vp.strided.load(ptr,stride,mask,vlen)
0591 BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_load, 2, 3)
0592 // chain = EXPERIMENTAL_VP_STRIDED_LOAD chain,base,offset,stride,mask,evl
0593 VP_PROPERTY_NO_FUNCTIONAL
0594 BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_LOAD, -1, experimental_vp_strided_load, 4, 5)
0595 HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD)
0596 END_REGISTER_VP(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD)
0597
0598 // llvm.vp.gather(ptr,mask,vlen)
0599 BEGIN_REGISTER_VP_INTRINSIC(vp_gather, 1, 2)
0600 // val,chain = VP_GATHER chain,base,indices,scale,mask,evl
0601 BEGIN_REGISTER_VP_SDNODE(VP_GATHER, -1, vp_gather, 4, 5)
0602 HELPER_MAP_VPID_TO_VPSD(vp_gather, VP_GATHER)
0603 VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_gather)
0604 END_REGISTER_VP(vp_gather, VP_GATHER)
0605
0606 ///// } Memory Operations
0607
0608 ///// Reductions {
0609
0610 // Specialized helper macro for VP reductions (%start, %x, %mask, %evl).
0611 #ifdef HELPER_REGISTER_REDUCTION_VP
0612 #error \
0613 "The internal helper macro HELPER_REGISTER_REDUCTION_VP is already defined!"
0614 #endif
0615 #define HELPER_REGISTER_REDUCTION_VP(VPID, VPSD, INTRIN, SDOPC) \
0616 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \
0617 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
0618 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0619 END_REGISTER_VP(VPID, VPSD)
0620
0621 // llvm.vp.reduce.add(start,x,mask,vlen)
0622 HELPER_REGISTER_REDUCTION_VP(vp_reduce_add, VP_REDUCE_ADD,
0623 vector_reduce_add, VECREDUCE_ADD)
0624
0625 // llvm.vp.reduce.mul(start,x,mask,vlen)
0626 HELPER_REGISTER_REDUCTION_VP(vp_reduce_mul, VP_REDUCE_MUL,
0627 vector_reduce_mul, VECREDUCE_MUL)
0628
0629 // llvm.vp.reduce.and(start,x,mask,vlen)
0630 HELPER_REGISTER_REDUCTION_VP(vp_reduce_and, VP_REDUCE_AND,
0631 vector_reduce_and, VECREDUCE_AND)
0632
0633 // llvm.vp.reduce.or(start,x,mask,vlen)
0634 HELPER_REGISTER_REDUCTION_VP(vp_reduce_or, VP_REDUCE_OR,
0635 vector_reduce_or, VECREDUCE_OR)
0636
0637 // llvm.vp.reduce.xor(start,x,mask,vlen)
0638 HELPER_REGISTER_REDUCTION_VP(vp_reduce_xor, VP_REDUCE_XOR,
0639 vector_reduce_xor, VECREDUCE_XOR)
0640
0641 // llvm.vp.reduce.smax(start,x,mask,vlen)
0642 HELPER_REGISTER_REDUCTION_VP(vp_reduce_smax, VP_REDUCE_SMAX,
0643 vector_reduce_smax, VECREDUCE_SMAX)
0644
0645 // llvm.vp.reduce.smin(start,x,mask,vlen)
0646 HELPER_REGISTER_REDUCTION_VP(vp_reduce_smin, VP_REDUCE_SMIN,
0647 vector_reduce_smin, VECREDUCE_SMIN)
0648
0649 // llvm.vp.reduce.umax(start,x,mask,vlen)
0650 HELPER_REGISTER_REDUCTION_VP(vp_reduce_umax, VP_REDUCE_UMAX,
0651 vector_reduce_umax, VECREDUCE_UMAX)
0652
0653 // llvm.vp.reduce.umin(start,x,mask,vlen)
0654 HELPER_REGISTER_REDUCTION_VP(vp_reduce_umin, VP_REDUCE_UMIN,
0655 vector_reduce_umin, VECREDUCE_UMIN)
0656
0657 // llvm.vp.reduce.fmax(start,x,mask,vlen)
0658 HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmax, VP_REDUCE_FMAX,
0659 vector_reduce_fmax, VECREDUCE_FMAX)
0660
0661 // llvm.vp.reduce.fmin(start,x,mask,vlen)
0662 HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmin, VP_REDUCE_FMIN,
0663 vector_reduce_fmin, VECREDUCE_FMIN)
0664
0665 // llvm.vp.reduce.fmaximum(start,x,mask,vlen)
0666 HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmaximum, VP_REDUCE_FMAXIMUM,
0667 vector_reduce_fmaximum, VECREDUCE_FMAXIMUM)
0668
0669 // llvm.vp.reduce.fminimum(start,x,mask,vlen)
0670 HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM,
0671 vector_reduce_fminimum, VECREDUCE_FMINIMUM)
0672
0673 #undef HELPER_REGISTER_REDUCTION_VP
0674
0675 // Specialized helper macro for VP reductions as above but with two forms:
0676 // sequential and reassociative. These manifest as the presence of 'reassoc'
0677 // fast-math flags in the IR and as two distinct ISD opcodes in the
0678 // SelectionDAG.
0679 // Note we by default map from the VP intrinsic to the SEQ ISD opcode, which
0680 // can then be relaxed to the non-SEQ ISD opcode if the 'reassoc' flag is set.
0681 #ifdef HELPER_REGISTER_REDUCTION_SEQ_VP
0682 #error \
0683 "The internal helper macro HELPER_REGISTER_REDUCTION_SEQ_VP is already defined!"
0684 #endif
0685 #define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, SDOPC, SEQ_SDOPC, INTRIN) \
0686 BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
0687 BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
0688 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
0689 END_REGISTER_VP_SDNODE(VPSD) \
0690 BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
0691 HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
0692 VP_PROPERTY_FUNCTIONAL_SDOPC(SEQ_SDOPC) \
0693 END_REGISTER_VP_SDNODE(SEQ_VPSD) \
0694 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
0695 END_REGISTER_VP_INTRINSIC(VPID)
0696
0697 // llvm.vp.reduce.fadd(start,x,mask,vlen)
0698 HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fadd, VP_REDUCE_FADD,
0699 VP_REDUCE_SEQ_FADD, VECREDUCE_FADD,
0700 VECREDUCE_SEQ_FADD, vector_reduce_fadd)
0701
0702 // llvm.vp.reduce.fmul(start,x,mask,vlen)
0703 HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL,
0704 VP_REDUCE_SEQ_FMUL, VECREDUCE_FMUL,
0705 VECREDUCE_SEQ_FMUL, vector_reduce_fmul)
0706
0707 #undef HELPER_REGISTER_REDUCTION_SEQ_VP
0708
0709 ///// } Reduction
0710
0711 ///// Shuffles {
0712
0713 // The mask 'cond' operand of llvm.vp.select and llvm.vp.merge are not reported
0714 // as masks with the BEGIN_REGISTER_VP_* macros. This is because, unlike other
0715 // VP intrinsics, these two have a defined result on lanes where the mask is
0716 // false.
0717 //
0718 // llvm.vp.select(cond,on_true,on_false,vlen)
0719 BEGIN_REGISTER_VP(vp_select, std::nullopt, 3, VP_SELECT, -1)
0720 VP_PROPERTY_FUNCTIONAL_OPC(Select)
0721 VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
0722 END_REGISTER_VP(vp_select, VP_SELECT)
0723
0724 // llvm.vp.merge(cond,on_true,on_false,pivot)
0725 BEGIN_REGISTER_VP(vp_merge, std::nullopt, 3, VP_MERGE, -1)
0726 VP_PROPERTY_NO_FUNCTIONAL
0727 END_REGISTER_VP(vp_merge, VP_MERGE)
0728
0729 BEGIN_REGISTER_VP(experimental_vp_splice, 3, 5, EXPERIMENTAL_VP_SPLICE, -1)
0730 VP_PROPERTY_NO_FUNCTIONAL
0731 END_REGISTER_VP(experimental_vp_splice, EXPERIMENTAL_VP_SPLICE)
0732
0733 // llvm.experimental.vp.reverse(x,mask,vlen)
0734 BEGIN_REGISTER_VP(experimental_vp_reverse, 1, 2,
0735 EXPERIMENTAL_VP_REVERSE, -1)
0736 VP_PROPERTY_NO_FUNCTIONAL
0737 END_REGISTER_VP(experimental_vp_reverse, EXPERIMENTAL_VP_REVERSE)
0738
0739 ///// } Shuffles
0740
0741 // llvm.vp.splat(val,mask,vlen)
0742 BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_splat, 1, 2)
0743 BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_SPLAT, -1, experimental_vp_splat, 1, 2)
0744 VP_PROPERTY_NO_FUNCTIONAL
0745 HELPER_MAP_VPID_TO_VPSD(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT)
0746 END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT)
0747
0748 #undef BEGIN_REGISTER_VP
0749 #undef BEGIN_REGISTER_VP_INTRINSIC
0750 #undef BEGIN_REGISTER_VP_SDNODE
0751 #undef END_REGISTER_VP
0752 #undef END_REGISTER_VP_INTRINSIC
0753 #undef END_REGISTER_VP_SDNODE
0754 #undef HELPER_MAP_VPID_TO_VPSD
0755 #undef VP_PROPERTY_BINARYOP
0756 #undef VP_PROPERTY_CONSTRAINEDFP
0757 #undef VP_PROPERTY_FUNCTIONAL_INTRINSIC
0758 #undef VP_PROPERTY_FUNCTIONAL_OPC
0759 #undef VP_PROPERTY_FUNCTIONAL_SDOPC
0760 #undef VP_PROPERTY_NO_FUNCTIONAL
