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0001 //===--- NVVMIntrinsicUtils.h -----------------------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 /// \file
0010 /// This file contains the definitions of the enumerations and flags
0011 /// associated with NVVM Intrinsics, along with some helper functions.
0012 //
0013 //===----------------------------------------------------------------------===//
0014 
0015 #ifndef LLVM_IR_NVVMINTRINSICUTILS_H
0016 #define LLVM_IR_NVVMINTRINSICUTILS_H
0017 
0018 #include <stdint.h>
0019 
0020 #include "llvm/ADT/APFloat.h"
0021 #include "llvm/IR/Intrinsics.h"
0022 #include "llvm/IR/IntrinsicsNVPTX.h"
0023 
0024 namespace llvm {
0025 namespace nvvm {
0026 
0027 // Reduction Ops supported with TMA Copy from Shared
0028 // to Global Memory for the "cp.reduce.async.bulk.tensor.*"
0029 // family of PTX instructions.
0030 enum class TMAReductionOp : uint8_t {
0031   ADD = 0,
0032   MIN = 1,
0033   MAX = 2,
0034   INC = 3,
0035   DEC = 4,
0036   AND = 5,
0037   OR = 6,
0038   XOR = 7,
0039 };
0040 
0041 inline bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
0042   switch (IntrinsicID) {
0043   case Intrinsic::nvvm_f2i_rm_ftz:
0044   case Intrinsic::nvvm_f2i_rn_ftz:
0045   case Intrinsic::nvvm_f2i_rp_ftz:
0046   case Intrinsic::nvvm_f2i_rz_ftz:
0047 
0048   case Intrinsic::nvvm_f2ui_rm_ftz:
0049   case Intrinsic::nvvm_f2ui_rn_ftz:
0050   case Intrinsic::nvvm_f2ui_rp_ftz:
0051   case Intrinsic::nvvm_f2ui_rz_ftz:
0052 
0053   case Intrinsic::nvvm_f2ll_rm_ftz:
0054   case Intrinsic::nvvm_f2ll_rn_ftz:
0055   case Intrinsic::nvvm_f2ll_rp_ftz:
0056   case Intrinsic::nvvm_f2ll_rz_ftz:
0057 
0058   case Intrinsic::nvvm_f2ull_rm_ftz:
0059   case Intrinsic::nvvm_f2ull_rn_ftz:
0060   case Intrinsic::nvvm_f2ull_rp_ftz:
0061   case Intrinsic::nvvm_f2ull_rz_ftz:
0062     return true;
0063 
0064   case Intrinsic::nvvm_f2i_rm:
0065   case Intrinsic::nvvm_f2i_rn:
0066   case Intrinsic::nvvm_f2i_rp:
0067   case Intrinsic::nvvm_f2i_rz:
0068 
0069   case Intrinsic::nvvm_f2ui_rm:
0070   case Intrinsic::nvvm_f2ui_rn:
0071   case Intrinsic::nvvm_f2ui_rp:
0072   case Intrinsic::nvvm_f2ui_rz:
0073 
0074   case Intrinsic::nvvm_d2i_rm:
0075   case Intrinsic::nvvm_d2i_rn:
0076   case Intrinsic::nvvm_d2i_rp:
0077   case Intrinsic::nvvm_d2i_rz:
0078 
0079   case Intrinsic::nvvm_d2ui_rm:
0080   case Intrinsic::nvvm_d2ui_rn:
0081   case Intrinsic::nvvm_d2ui_rp:
0082   case Intrinsic::nvvm_d2ui_rz:
0083 
0084   case Intrinsic::nvvm_f2ll_rm:
0085   case Intrinsic::nvvm_f2ll_rn:
0086   case Intrinsic::nvvm_f2ll_rp:
0087   case Intrinsic::nvvm_f2ll_rz:
0088 
0089   case Intrinsic::nvvm_f2ull_rm:
0090   case Intrinsic::nvvm_f2ull_rn:
0091   case Intrinsic::nvvm_f2ull_rp:
0092   case Intrinsic::nvvm_f2ull_rz:
0093 
0094   case Intrinsic::nvvm_d2ll_rm:
0095   case Intrinsic::nvvm_d2ll_rn:
0096   case Intrinsic::nvvm_d2ll_rp:
0097   case Intrinsic::nvvm_d2ll_rz:
0098 
0099   case Intrinsic::nvvm_d2ull_rm:
0100   case Intrinsic::nvvm_d2ull_rn:
0101   case Intrinsic::nvvm_d2ull_rp:
0102   case Intrinsic::nvvm_d2ull_rz:
0103     return false;
0104   }
0105   llvm_unreachable("Checking FTZ flag for invalid f2i/d2i intrinsic");
0106   return false;
0107 }
0108 
0109 inline bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID) {
0110   switch (IntrinsicID) {
0111   // f2i
0112   case Intrinsic::nvvm_f2i_rm:
0113   case Intrinsic::nvvm_f2i_rm_ftz:
0114   case Intrinsic::nvvm_f2i_rn:
0115   case Intrinsic::nvvm_f2i_rn_ftz:
0116   case Intrinsic::nvvm_f2i_rp:
0117   case Intrinsic::nvvm_f2i_rp_ftz:
0118   case Intrinsic::nvvm_f2i_rz:
0119   case Intrinsic::nvvm_f2i_rz_ftz:
0120   // d2i
0121   case Intrinsic::nvvm_d2i_rm:
0122   case Intrinsic::nvvm_d2i_rn:
0123   case Intrinsic::nvvm_d2i_rp:
0124   case Intrinsic::nvvm_d2i_rz:
0125   // f2ll
0126   case Intrinsic::nvvm_f2ll_rm:
0127   case Intrinsic::nvvm_f2ll_rm_ftz:
0128   case Intrinsic::nvvm_f2ll_rn:
0129   case Intrinsic::nvvm_f2ll_rn_ftz:
0130   case Intrinsic::nvvm_f2ll_rp:
0131   case Intrinsic::nvvm_f2ll_rp_ftz:
0132   case Intrinsic::nvvm_f2ll_rz:
0133   case Intrinsic::nvvm_f2ll_rz_ftz:
0134   // d2ll
0135   case Intrinsic::nvvm_d2ll_rm:
0136   case Intrinsic::nvvm_d2ll_rn:
0137   case Intrinsic::nvvm_d2ll_rp:
0138   case Intrinsic::nvvm_d2ll_rz:
0139     return true;
0140 
0141   // f2ui
0142   case Intrinsic::nvvm_f2ui_rm:
0143   case Intrinsic::nvvm_f2ui_rm_ftz:
0144   case Intrinsic::nvvm_f2ui_rn:
0145   case Intrinsic::nvvm_f2ui_rn_ftz:
0146   case Intrinsic::nvvm_f2ui_rp:
0147   case Intrinsic::nvvm_f2ui_rp_ftz:
0148   case Intrinsic::nvvm_f2ui_rz:
0149   case Intrinsic::nvvm_f2ui_rz_ftz:
0150   // d2ui
0151   case Intrinsic::nvvm_d2ui_rm:
0152   case Intrinsic::nvvm_d2ui_rn:
0153   case Intrinsic::nvvm_d2ui_rp:
0154   case Intrinsic::nvvm_d2ui_rz:
0155   // f2ull
0156   case Intrinsic::nvvm_f2ull_rm:
0157   case Intrinsic::nvvm_f2ull_rm_ftz:
0158   case Intrinsic::nvvm_f2ull_rn:
0159   case Intrinsic::nvvm_f2ull_rn_ftz:
0160   case Intrinsic::nvvm_f2ull_rp:
0161   case Intrinsic::nvvm_f2ull_rp_ftz:
0162   case Intrinsic::nvvm_f2ull_rz:
0163   case Intrinsic::nvvm_f2ull_rz_ftz:
0164   // d2ull
0165   case Intrinsic::nvvm_d2ull_rm:
0166   case Intrinsic::nvvm_d2ull_rn:
0167   case Intrinsic::nvvm_d2ull_rp:
0168   case Intrinsic::nvvm_d2ull_rz:
0169     return false;
0170   }
0171   llvm_unreachable(
0172       "Checking invalid f2i/d2i intrinsic for signed int conversion");
0173   return false;
0174 }
0175 
0176 inline APFloat::roundingMode
0177 GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID) {
0178   switch (IntrinsicID) {
0179   // RM:
0180   case Intrinsic::nvvm_f2i_rm:
0181   case Intrinsic::nvvm_f2ui_rm:
0182   case Intrinsic::nvvm_f2i_rm_ftz:
0183   case Intrinsic::nvvm_f2ui_rm_ftz:
0184   case Intrinsic::nvvm_d2i_rm:
0185   case Intrinsic::nvvm_d2ui_rm:
0186 
0187   case Intrinsic::nvvm_f2ll_rm:
0188   case Intrinsic::nvvm_f2ull_rm:
0189   case Intrinsic::nvvm_f2ll_rm_ftz:
0190   case Intrinsic::nvvm_f2ull_rm_ftz:
0191   case Intrinsic::nvvm_d2ll_rm:
0192   case Intrinsic::nvvm_d2ull_rm:
0193     return APFloat::rmTowardNegative;
0194 
0195   // RN:
0196   case Intrinsic::nvvm_f2i_rn:
0197   case Intrinsic::nvvm_f2ui_rn:
0198   case Intrinsic::nvvm_f2i_rn_ftz:
0199   case Intrinsic::nvvm_f2ui_rn_ftz:
0200   case Intrinsic::nvvm_d2i_rn:
0201   case Intrinsic::nvvm_d2ui_rn:
0202 
0203   case Intrinsic::nvvm_f2ll_rn:
0204   case Intrinsic::nvvm_f2ull_rn:
0205   case Intrinsic::nvvm_f2ll_rn_ftz:
0206   case Intrinsic::nvvm_f2ull_rn_ftz:
0207   case Intrinsic::nvvm_d2ll_rn:
0208   case Intrinsic::nvvm_d2ull_rn:
0209     return APFloat::rmNearestTiesToEven;
0210 
0211   // RP:
0212   case Intrinsic::nvvm_f2i_rp:
0213   case Intrinsic::nvvm_f2ui_rp:
0214   case Intrinsic::nvvm_f2i_rp_ftz:
0215   case Intrinsic::nvvm_f2ui_rp_ftz:
0216   case Intrinsic::nvvm_d2i_rp:
0217   case Intrinsic::nvvm_d2ui_rp:
0218 
0219   case Intrinsic::nvvm_f2ll_rp:
0220   case Intrinsic::nvvm_f2ull_rp:
0221   case Intrinsic::nvvm_f2ll_rp_ftz:
0222   case Intrinsic::nvvm_f2ull_rp_ftz:
0223   case Intrinsic::nvvm_d2ll_rp:
0224   case Intrinsic::nvvm_d2ull_rp:
0225     return APFloat::rmTowardPositive;
0226 
0227   // RZ:
0228   case Intrinsic::nvvm_f2i_rz:
0229   case Intrinsic::nvvm_f2ui_rz:
0230   case Intrinsic::nvvm_f2i_rz_ftz:
0231   case Intrinsic::nvvm_f2ui_rz_ftz:
0232   case Intrinsic::nvvm_d2i_rz:
0233   case Intrinsic::nvvm_d2ui_rz:
0234 
0235   case Intrinsic::nvvm_f2ll_rz:
0236   case Intrinsic::nvvm_f2ull_rz:
0237   case Intrinsic::nvvm_f2ll_rz_ftz:
0238   case Intrinsic::nvvm_f2ull_rz_ftz:
0239   case Intrinsic::nvvm_d2ll_rz:
0240   case Intrinsic::nvvm_d2ull_rz:
0241     return APFloat::rmTowardZero;
0242   }
0243   llvm_unreachable("Checking rounding mode for invalid f2i/d2i intrinsic");
0244   return APFloat::roundingMode::Invalid;
0245 }
0246 
0247 inline bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID) {
0248   switch (IntrinsicID) {
0249   case Intrinsic::nvvm_fmax_ftz_f:
0250   case Intrinsic::nvvm_fmax_ftz_nan_f:
0251   case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
0252   case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
0253 
0254   case Intrinsic::nvvm_fmin_ftz_f:
0255   case Intrinsic::nvvm_fmin_ftz_nan_f:
0256   case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
0257   case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
0258     return true;
0259 
0260   case Intrinsic::nvvm_fmax_d:
0261   case Intrinsic::nvvm_fmax_f:
0262   case Intrinsic::nvvm_fmax_nan_f:
0263   case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
0264   case Intrinsic::nvvm_fmax_xorsign_abs_f:
0265 
0266   case Intrinsic::nvvm_fmin_d:
0267   case Intrinsic::nvvm_fmin_f:
0268   case Intrinsic::nvvm_fmin_nan_f:
0269   case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
0270   case Intrinsic::nvvm_fmin_xorsign_abs_f:
0271     return false;
0272   }
0273   llvm_unreachable("Checking FTZ flag for invalid fmin/fmax intrinsic");
0274   return false;
0275 }
0276 
0277 inline bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID) {
0278   switch (IntrinsicID) {
0279   case Intrinsic::nvvm_fmax_ftz_nan_f:
0280   case Intrinsic::nvvm_fmax_nan_f:
0281   case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
0282   case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
0283 
0284   case Intrinsic::nvvm_fmin_ftz_nan_f:
0285   case Intrinsic::nvvm_fmin_nan_f:
0286   case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
0287   case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
0288     return true;
0289 
0290   case Intrinsic::nvvm_fmax_d:
0291   case Intrinsic::nvvm_fmax_f:
0292   case Intrinsic::nvvm_fmax_ftz_f:
0293   case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
0294   case Intrinsic::nvvm_fmax_xorsign_abs_f:
0295 
0296   case Intrinsic::nvvm_fmin_d:
0297   case Intrinsic::nvvm_fmin_f:
0298   case Intrinsic::nvvm_fmin_ftz_f:
0299   case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
0300   case Intrinsic::nvvm_fmin_xorsign_abs_f:
0301     return false;
0302   }
0303   llvm_unreachable("Checking NaN flag for invalid fmin/fmax intrinsic");
0304   return false;
0305 }
0306 
0307 inline bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID) {
0308   switch (IntrinsicID) {
0309   case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
0310   case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
0311   case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
0312   case Intrinsic::nvvm_fmax_xorsign_abs_f:
0313 
0314   case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
0315   case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
0316   case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
0317   case Intrinsic::nvvm_fmin_xorsign_abs_f:
0318     return true;
0319 
0320   case Intrinsic::nvvm_fmax_d:
0321   case Intrinsic::nvvm_fmax_f:
0322   case Intrinsic::nvvm_fmax_ftz_f:
0323   case Intrinsic::nvvm_fmax_ftz_nan_f:
0324   case Intrinsic::nvvm_fmax_nan_f:
0325 
0326   case Intrinsic::nvvm_fmin_d:
0327   case Intrinsic::nvvm_fmin_f:
0328   case Intrinsic::nvvm_fmin_ftz_f:
0329   case Intrinsic::nvvm_fmin_ftz_nan_f:
0330   case Intrinsic::nvvm_fmin_nan_f:
0331     return false;
0332   }
0333   llvm_unreachable("Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
0334   return false;
0335 }
0336 
0337 } // namespace nvvm
0338 } // namespace llvm
0339 #endif // LLVM_IR_NVVMINTRINSICUTILS_H
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