Warning, /include/llvm/IR/IntrinsicsRISCVXsf.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsRISCVXsf.td - SiFive intrinsics -----------*- tablegen -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines all of the SiFive vendor intrinsics for RISC-V.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013 let TargetPrefix = "riscv" in {
0014 // Output: (vector_out)
0015 // Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or
0016 class RISCVSFCustomVC_X<bit HasSE, bit ImmScalar>
0017 : Intrinsic<[llvm_anyvector_ty],
0018 [llvm_anyint_ty, LLVMMatchType<1>, llvm_any_ty, llvm_anyint_ty],
0019 !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
0020 !if(ImmScalar, [ImmArg<ArgIndex<2>>], []), // ScalarOperand
0021 !if(HasSE, [IntrHasSideEffects], []))>,
0022 RISCVVIntrinsic {
0023 let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
0024 true: 2);
0025 let VLOperand = 3;
0026 }
0027 // Output: ()
0028 // Input: (bit<27-26>, bit<24-20>, bit<11-7>, scalar_in, sew, log2lmul, vl)
0029 class RISCVSFCustomVC_X_WO_Suffix<bit ImmScalar>
0030 : Intrinsic<[],
0031 [llvm_anyint_ty, LLVMMatchType<0>, LLVMMatchType<0>,
0032 llvm_any_ty, LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
0033 !listconcat([IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>,
0034 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>,
0035 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], // bit<27-26>, bit<24-20>, bit<11-7>, sew, log2lmul
0036 !if(ImmScalar, [ImmArg<ArgIndex<3>>], []))>, // ScalarOperand
0037 RISCVVIntrinsic {
0038 let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
0039 true: 3);
0040 let VLOperand = 6;
0041 }
0042 // Output: (vector_out) or ()
0043 // Input: (bit<27-26>, vector_in, vector_in/scalar_in, vl) or
0044 // (bit<27-26>, bit<11-7>, vector_in, vector_in/scalar_in, vl)
0045 class RISCVSFCustomVC_XV<bit HasDst, bit HasSE, bit ImmScalar>
0046 : Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
0047 !listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty],
0048 [llvm_anyint_ty, LLVMMatchType<0>, llvm_anyvector_ty]),
0049 [llvm_any_ty, llvm_anyint_ty]),
0050 !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
0051 !if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
0052 !if(ImmScalar, !if(HasDst, [ImmArg<ArgIndex<2>>],
0053 [ImmArg<ArgIndex<3>>]), []), // ScalarOperand
0054 !if(HasSE, [IntrHasSideEffects], []))>,
0055 RISCVVIntrinsic {
0056 let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
0057 HasDst: 2,
0058 true: 3);
0059 let VLOperand = !if(HasDst, 3, 4);
0060 }
0061 // Output: (vector_out) or ()
0062 // Input: (bit<27-26>, passthru, vector_in, vector_in/scalar_in, vl) or
0063 // (bit<27-26>, vector_in, vector_in, vector_in/scalar_in, vl)
0064 class RISCVSFCustomVC_XVV<bit HasDst, bit HasSE, bit ImmScalar>
0065 : Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
0066 !listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty],
0067 [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty]),
0068 [llvm_any_ty, llvm_anyint_ty]),
0069 !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
0070 !if(ImmScalar, [ImmArg<ArgIndex<3>>], []), // ScalarOperand
0071 !if(HasSE, [IntrHasSideEffects], []))>,
0072 RISCVVIntrinsic {
0073 let ScalarOperand = !if(ImmScalar, NoScalarOperand, 3);
0074 let VLOperand = 4;
0075 }
0076 // Output: (wvector_out) or ()
0077 // Input: (bit<27-26>, passthru, vector_in, vector_in/scalar_in, vl) or
0078 // (bit<27-26>, wvector_in, vector_in, vector_in/scalar_in, vl)
0079 class RISCVSFCustomVC_XVW<bit HasDst, bit HasSE, bit ImmScalar>
0080 : Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
0081 !listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty],
0082 [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty]),
0083 [llvm_any_ty, llvm_anyint_ty]),
0084 !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
0085 !if(ImmScalar, [ImmArg<ArgIndex<3>>], []), // ScalarOperand
0086 !if(HasSE, [IntrHasSideEffects], []))>,
0087 RISCVVIntrinsic {
0088 let ScalarOperand = !if(ImmScalar, NoScalarOperand, 3);
0089 let VLOperand = 4;
0090 }
0091
0092 multiclass RISCVSFCustomVC_X<list<string> type> {
0093 foreach t = type in {
0094 defvar ImmScalar = !eq(t, "i");
0095 def "int_riscv_sf_vc_" # t # "_se" : RISCVSFCustomVC_X_WO_Suffix<ImmScalar=ImmScalar>;
0096 def "int_riscv_sf_vc_v_" # t # "_se" : RISCVSFCustomVC_X<HasSE=1, ImmScalar=ImmScalar>;
0097 def "int_riscv_sf_vc_v_" # t : RISCVSFCustomVC_X<HasSE=0, ImmScalar=ImmScalar>;
0098 }
0099 }
0100
0101 multiclass RISCVSFCustomVC_XV<list<string> type> {
0102 foreach t = type in {
0103 defvar ImmScalar = !eq(t, "i");
0104 def "int_riscv_sf_vc_" # t # "v_se" : RISCVSFCustomVC_XV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
0105 def "int_riscv_sf_vc_v_" # t # "v_se" : RISCVSFCustomVC_XV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
0106 def "int_riscv_sf_vc_v_" # t # "v" : RISCVSFCustomVC_XV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
0107 }
0108 }
0109
0110 multiclass RISCVSFCustomVC_XVV<list<string> type> {
0111 foreach t = type in {
0112 defvar ImmScalar = !eq(t, "i");
0113 def "int_riscv_sf_vc_" # t # "vv_se" : RISCVSFCustomVC_XVV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
0114 def "int_riscv_sf_vc_v_" # t # "vv_se" : RISCVSFCustomVC_XVV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
0115 def "int_riscv_sf_vc_v_" # t # "vv" : RISCVSFCustomVC_XVV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
0116 }
0117 }
0118
0119 multiclass RISCVSFCustomVC_XVW<list<string> type> {
0120 foreach t = type in {
0121 defvar ImmScalar = !eq(t, "i");
0122 def "int_riscv_sf_vc_" # t # "vw_se" : RISCVSFCustomVC_XVW<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
0123 def "int_riscv_sf_vc_v_" # t # "vw_se" : RISCVSFCustomVC_XVW<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
0124 def "int_riscv_sf_vc_v_" # t # "vw" : RISCVSFCustomVC_XVW<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
0125 }
0126 }
0127
0128 class RISCVSFCustomVMACC
0129 : DefaultAttrsIntrinsic< [llvm_anyvector_ty],
0130 [LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyvector_ty,
0131 llvm_anyint_ty, LLVMMatchType<3>],
0132 [ImmArg<ArgIndex<4>>, IntrNoMem] >, RISCVVIntrinsic {
0133 let VLOperand = 3;
0134 }
0135
0136 // Input: (passthru, vector_in, scalar_in, frm, vl)
0137 class RISCVSFCustomVFNRCLIPUnMasked
0138 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0139 [LLVMMatchType<0>, llvm_anyfloat_ty, LLVMVectorElementType<1>,
0140 llvm_anyint_ty, LLVMMatchType<2>],
0141 [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
0142 let VLOperand = 4;
0143 }
0144
0145 // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
0146 class RISCVSFCustomVFNRCLIPMasked
0147 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0148 [LLVMMatchType<0>, llvm_anyfloat_ty, LLVMVectorElementType<1>,
0149 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
0150 LLVMMatchType<2>, LLVMMatchType<2>],
0151 [ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
0152 let VLOperand = 5;
0153 }
0154
0155 multiclass RISCVSFCustomVFNRCLIP {
0156 def NAME : RISCVSFCustomVFNRCLIPUnMasked;
0157 def NAME # "_mask" : RISCVSFCustomVFNRCLIPMasked;
0158 }
0159
0160 defm "" : RISCVSFCustomVC_X<["x", "i"]>;
0161 defm "" : RISCVSFCustomVC_XV<["x", "i", "v", "f"]>;
0162 defm "" : RISCVSFCustomVC_XVV<["x", "i", "v", "f"]>;
0163 defm "" : RISCVSFCustomVC_XVW<["x", "i", "v", "f"]>;
0164
0165 // XSfvqmaccdod
0166 def int_riscv_sf_vqmaccu_2x8x2 : RISCVSFCustomVMACC;
0167 def int_riscv_sf_vqmacc_2x8x2 : RISCVSFCustomVMACC;
0168 def int_riscv_sf_vqmaccus_2x8x2 : RISCVSFCustomVMACC;
0169 def int_riscv_sf_vqmaccsu_2x8x2 : RISCVSFCustomVMACC;
0170
0171 // XSfvqmaccqoq
0172 def int_riscv_sf_vqmaccu_4x8x4 : RISCVSFCustomVMACC;
0173 def int_riscv_sf_vqmacc_4x8x4 : RISCVSFCustomVMACC;
0174 def int_riscv_sf_vqmaccus_4x8x4 : RISCVSFCustomVMACC;
0175 def int_riscv_sf_vqmaccsu_4x8x4 : RISCVSFCustomVMACC;
0176
0177 // XSfvfwmaccqqq
0178 def int_riscv_sf_vfwmacc_4x4x4 : RISCVSFCustomVMACC;
0179
0180 // XSfvfnrclipxfqf
0181 defm int_riscv_sf_vfnrclip_x_f_qf : RISCVSFCustomVFNRCLIP;
0182 defm int_riscv_sf_vfnrclip_xu_f_qf : RISCVSFCustomVFNRCLIP;
0183 } // TargetPrefix = "riscv"
