Warning, /include/llvm/IR/IntrinsicsRISCVXTHead.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsRISCVXTHead.td - T-Head intrinsics --------*- tablegen -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines all of the T-Head vendor intrinsics for RISC-V.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013 let TargetPrefix = "riscv" in {
0014
0015 class TH_VdotTernaryWideMasked
0016 : DefaultAttrsIntrinsic< [llvm_anyvector_ty],
0017 [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
0018 LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>,
0019 llvm_anyint_ty, LLVMMatchType<3>],
0020 [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
0021 let ScalarOperand = 1;
0022 let VLOperand = 4;
0023 }
0024
0025 multiclass TH_VdotTernaryWide {
0026 def "int_riscv_" # NAME : RISCVTernaryWideUnMasked;
0027 def "int_riscv_" # NAME # "_mask" : TH_VdotTernaryWideMasked;
0028 }
0029
0030 defm th_vmaqa : TH_VdotTernaryWide;
0031 defm th_vmaqau : TH_VdotTernaryWide;
0032 defm th_vmaqasu : TH_VdotTernaryWide;
0033 defm th_vmaqaus : TH_VdotTernaryWide;
0034 }
