Warning, /include/llvm/IR/IntrinsicsRISCVXCV.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines all of the CORE-V vendor intrinsics for RISC-V.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013 class ScalarCoreVBitManipGprGprIntrinsic
0014 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0015 [IntrNoMem, IntrSpeculatable]>;
0016
0017 class ScalarCoreVBitManipGprIntrinsic
0018 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
0019 [IntrNoMem, IntrSpeculatable]>;
0020
0021 class ScalarCoreVAluGprIntrinsic
0022 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
0023 [IntrNoMem, IntrSpeculatable]>;
0024
0025 class ScalarCoreVAluGprGprIntrinsic
0026 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0027 [IntrNoMem, IntrSpeculatable]>;
0028
0029 class ScalarCoreVAluGprGprGprIntrinsic
0030 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0031 [IntrNoMem, IntrSpeculatable]>;
0032
0033 class ScalarCoreVMacGprGprGprIntrinsic
0034 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0035 [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
0036
0037 class ScalarCoreVMacGprGPRImmIntrinsic
0038 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0039 [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
0040
0041 class ScalarCoreVMacGprGprGprImmIntrinsic
0042 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0043 [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;
0044
0045 let TargetPrefix = "riscv" in {
0046 def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
0047 def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
0048 def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic;
0049 def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic;
0050
0051 def int_riscv_cv_bitmanip_insert
0052 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0053 [IntrNoMem, IntrSpeculatable]>;
0054
0055 def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic;
0056
0057 def int_riscv_cv_bitmanip_bitrev
0058 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0059 [IntrNoMem, IntrWillReturn, IntrSpeculatable,
0060 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
0061
0062 def int_riscv_cv_alu_clip : ScalarCoreVAluGprGprIntrinsic;
0063 def int_riscv_cv_alu_clipu : ScalarCoreVAluGprGprIntrinsic;
0064 def int_riscv_cv_alu_addN : ScalarCoreVAluGprGprGprIntrinsic;
0065 def int_riscv_cv_alu_adduN : ScalarCoreVAluGprGprGprIntrinsic;
0066 def int_riscv_cv_alu_addRN : ScalarCoreVAluGprGprGprIntrinsic;
0067 def int_riscv_cv_alu_adduRN : ScalarCoreVAluGprGprGprIntrinsic;
0068 def int_riscv_cv_alu_subN : ScalarCoreVAluGprGprGprIntrinsic;
0069 def int_riscv_cv_alu_subuN : ScalarCoreVAluGprGprGprIntrinsic;
0070 def int_riscv_cv_alu_subRN : ScalarCoreVAluGprGprGprIntrinsic;
0071 def int_riscv_cv_alu_subuRN : ScalarCoreVAluGprGprGprIntrinsic;
0072
0073 def int_riscv_cv_mac_mac : ScalarCoreVMacGprGprGprIntrinsic;
0074 def int_riscv_cv_mac_msu : ScalarCoreVMacGprGprGprIntrinsic;
0075
0076 def int_riscv_cv_mac_muluN : ScalarCoreVMacGprGPRImmIntrinsic;
0077 def int_riscv_cv_mac_mulhhuN : ScalarCoreVMacGprGPRImmIntrinsic;
0078 def int_riscv_cv_mac_mulsN : ScalarCoreVMacGprGPRImmIntrinsic;
0079 def int_riscv_cv_mac_mulhhsN : ScalarCoreVMacGprGPRImmIntrinsic;
0080 def int_riscv_cv_mac_muluRN : ScalarCoreVMacGprGPRImmIntrinsic;
0081 def int_riscv_cv_mac_mulhhuRN : ScalarCoreVMacGprGPRImmIntrinsic;
0082 def int_riscv_cv_mac_mulsRN : ScalarCoreVMacGprGPRImmIntrinsic;
0083 def int_riscv_cv_mac_mulhhsRN : ScalarCoreVMacGprGPRImmIntrinsic;
0084
0085 def int_riscv_cv_mac_macuN : ScalarCoreVMacGprGprGprImmIntrinsic;
0086 def int_riscv_cv_mac_machhuN : ScalarCoreVMacGprGprGprImmIntrinsic;
0087 def int_riscv_cv_mac_macsN : ScalarCoreVMacGprGprGprImmIntrinsic;
0088 def int_riscv_cv_mac_machhsN : ScalarCoreVMacGprGprGprImmIntrinsic;
0089 def int_riscv_cv_mac_macuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
0090 def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
0091 def int_riscv_cv_mac_macsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
0092 def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
0093 } // TargetPrefix = "riscv"
