Warning, /include/llvm/IR/IntrinsicsLoongArch.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsLoongArch.td - Defines LoongArch intrinsics *- tablegen -*===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines all of the LoongArch-specific intrinsics.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013 let TargetPrefix = "loongarch" in {
0014
0015 //===----------------------------------------------------------------------===//
0016 // Atomics
0017
0018 // T @llvm.<name>.T.<p>(any*, T, T, T imm);
0019 class MaskedAtomicRMW<LLVMType itype>
0020 : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype],
0021 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
0022
0023 // We define 32-bit and 64-bit variants of the above, where T stands for i32
0024 // or i64 respectively:
0025 multiclass MaskedAtomicRMWIntrinsics {
0026 // i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm);
0027 def _i32 : MaskedAtomicRMW<llvm_i32_ty>;
0028 // i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm);
0029 def _i64 : MaskedAtomicRMW<llvm_i64_ty>;
0030 }
0031
0032 multiclass MaskedAtomicRMWFiveOpIntrinsics {
0033 // TODO: Support cmpxchg on LA32.
0034 // i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm);
0035 def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>;
0036 }
0037
0038 defm int_loongarch_masked_atomicrmw_xchg : MaskedAtomicRMWIntrinsics;
0039 defm int_loongarch_masked_atomicrmw_add : MaskedAtomicRMWIntrinsics;
0040 defm int_loongarch_masked_atomicrmw_sub : MaskedAtomicRMWIntrinsics;
0041 defm int_loongarch_masked_atomicrmw_nand : MaskedAtomicRMWIntrinsics;
0042 defm int_loongarch_masked_atomicrmw_umax : MaskedAtomicRMWIntrinsics;
0043 defm int_loongarch_masked_atomicrmw_umin : MaskedAtomicRMWIntrinsics;
0044 defm int_loongarch_masked_atomicrmw_max : MaskedAtomicRMWFiveOpIntrinsics;
0045 defm int_loongarch_masked_atomicrmw_min : MaskedAtomicRMWFiveOpIntrinsics;
0046
0047 // @llvm.loongarch.masked.cmpxchg.i64.<p>(
0048 // ptr addr, grlen cmpval, grlen newval, grlen mask, grlenimm ordering)
0049 defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics;
0050
0051 //===----------------------------------------------------------------------===//
0052 // LoongArch BASE
0053
0054 class BaseInt<list<LLVMType> ret_types, list<LLVMType> param_types,
0055 list<IntrinsicProperty> intr_properties = []>
0056 : Intrinsic<ret_types, param_types, intr_properties>,
0057 ClangBuiltin<!subst("int_loongarch", "__builtin_loongarch", NAME)>;
0058
0059 def int_loongarch_break : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
0060 def int_loongarch_cacop_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
0061 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
0062 def int_loongarch_cacop_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0063 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
0064 def int_loongarch_dbar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
0065
0066 def int_loongarch_ibar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
0067 def int_loongarch_movfcsr2gr : BaseInt<[llvm_i32_ty], [llvm_i32_ty],
0068 [ImmArg<ArgIndex<0>>]>;
0069 def int_loongarch_movgr2fcsr : BaseInt<[], [llvm_i32_ty, llvm_i32_ty],
0070 [ImmArg<ArgIndex<0>>]>;
0071 def int_loongarch_syscall : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
0072
0073 def int_loongarch_crc_w_b_w : BaseInt<[llvm_i32_ty],
0074 [llvm_i32_ty, llvm_i32_ty]>;
0075 def int_loongarch_crc_w_h_w : BaseInt<[llvm_i32_ty],
0076 [llvm_i32_ty, llvm_i32_ty]>;
0077 def int_loongarch_crc_w_w_w : BaseInt<[llvm_i32_ty],
0078 [llvm_i32_ty, llvm_i32_ty]>;
0079 def int_loongarch_crc_w_d_w : BaseInt<[llvm_i32_ty],
0080 [llvm_i64_ty, llvm_i32_ty]>;
0081
0082 def int_loongarch_crcc_w_b_w : BaseInt<[llvm_i32_ty],
0083 [llvm_i32_ty, llvm_i32_ty]>;
0084 def int_loongarch_crcc_w_h_w : BaseInt<[llvm_i32_ty],
0085 [llvm_i32_ty, llvm_i32_ty]>;
0086 def int_loongarch_crcc_w_w_w : BaseInt<[llvm_i32_ty],
0087 [llvm_i32_ty, llvm_i32_ty]>;
0088 def int_loongarch_crcc_w_d_w : BaseInt<[llvm_i32_ty],
0089 [llvm_i64_ty, llvm_i32_ty]>;
0090
0091 def int_loongarch_csrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty],
0092 [ImmArg<ArgIndex<0>>]>;
0093 def int_loongarch_csrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty],
0094 [ImmArg<ArgIndex<0>>]>;
0095 def int_loongarch_csrwr_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0096 [ImmArg<ArgIndex<1>>]>;
0097 def int_loongarch_csrwr_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty],
0098 [ImmArg<ArgIndex<1>>]>;
0099 def int_loongarch_csrxchg_w : BaseInt<[llvm_i32_ty],
0100 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
0101 [ImmArg<ArgIndex<2>>]>;
0102 def int_loongarch_csrxchg_d : BaseInt<[llvm_i64_ty],
0103 [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
0104 [ImmArg<ArgIndex<2>>]>;
0105
0106 def int_loongarch_iocsrrd_b : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>;
0107 def int_loongarch_iocsrrd_h : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>;
0108 def int_loongarch_iocsrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>;
0109 def int_loongarch_iocsrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty]>;
0110
0111 def int_loongarch_iocsrwr_b : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>;
0112 def int_loongarch_iocsrwr_h : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>;
0113 def int_loongarch_iocsrwr_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>;
0114 def int_loongarch_iocsrwr_d : BaseInt<[], [llvm_i64_ty, llvm_i32_ty]>;
0115
0116 def int_loongarch_cpucfg : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>;
0117
0118 def int_loongarch_asrtle_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>;
0119 def int_loongarch_asrtgt_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>;
0120
0121 def int_loongarch_lddir_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
0122 [ImmArg<ArgIndex<1>>]>;
0123 def int_loongarch_ldpte_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty],
0124 [ImmArg<ArgIndex<1>>]>;
0125
0126 def int_loongarch_frecipe_s : BaseInt<[llvm_float_ty], [llvm_float_ty],
0127 [IntrNoMem]>;
0128 def int_loongarch_frecipe_d : BaseInt<[llvm_double_ty], [llvm_double_ty],
0129 [IntrNoMem]>;
0130 def int_loongarch_frsqrte_s : BaseInt<[llvm_float_ty], [llvm_float_ty],
0131 [IntrNoMem]>;
0132 def int_loongarch_frsqrte_d : BaseInt<[llvm_double_ty], [llvm_double_ty],
0133 [IntrNoMem]>;
0134 } // TargetPrefix = "loongarch"
0135
0136 /// Vector intrinsic
0137
0138 class VecInt<list<LLVMType> ret_types, list<LLVMType> param_types,
0139 list<IntrinsicProperty> intr_properties = []>
0140 : Intrinsic<ret_types, param_types, intr_properties>,
0141 ClangBuiltin<!subst("int_loongarch", "__builtin", NAME)>;
0142
0143 class DefaultAttrsVecInt<list<LLVMType> ret_types, list<LLVMType> param_types,
0144 list<IntrinsicProperty> intr_properties = []>
0145 : DefaultAttrsIntrinsic<ret_types, param_types, intr_properties>,
0146 ClangBuiltin<!subst("int_loongarch", "__builtin", NAME)>;
0147
0148 //===----------------------------------------------------------------------===//
0149 // LSX
0150
0151 let TargetPrefix = "loongarch" in {
0152
0153 foreach inst = ["vadd_b", "vsub_b",
0154 "vsadd_b", "vsadd_bu", "vssub_b", "vssub_bu",
0155 "vavg_b", "vavg_bu", "vavgr_b", "vavgr_bu",
0156 "vabsd_b", "vabsd_bu", "vadda_b",
0157 "vmax_b", "vmax_bu", "vmin_b", "vmin_bu",
0158 "vmul_b", "vmuh_b", "vmuh_bu",
0159 "vdiv_b", "vdiv_bu", "vmod_b", "vmod_bu", "vsigncov_b",
0160 "vand_v", "vor_v", "vxor_v", "vnor_v", "vandn_v", "vorn_v",
0161 "vsll_b", "vsrl_b", "vsra_b", "vrotr_b", "vsrlr_b", "vsrar_b",
0162 "vbitclr_b", "vbitset_b", "vbitrev_b",
0163 "vseq_b", "vsle_b", "vsle_bu", "vslt_b", "vslt_bu",
0164 "vpackev_b", "vpackod_b", "vpickev_b", "vpickod_b",
0165 "vilvl_b", "vilvh_b"] in
0166 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty],
0167 [llvm_v16i8_ty, llvm_v16i8_ty],
0168 [IntrNoMem]>;
0169
0170 foreach inst = ["vadd_h", "vsub_h",
0171 "vsadd_h", "vsadd_hu", "vssub_h", "vssub_hu",
0172 "vavg_h", "vavg_hu", "vavgr_h", "vavgr_hu",
0173 "vabsd_h", "vabsd_hu", "vadda_h",
0174 "vmax_h", "vmax_hu", "vmin_h", "vmin_hu",
0175 "vmul_h", "vmuh_h", "vmuh_hu",
0176 "vdiv_h", "vdiv_hu", "vmod_h", "vmod_hu", "vsigncov_h",
0177 "vsll_h", "vsrl_h", "vsra_h", "vrotr_h", "vsrlr_h", "vsrar_h",
0178 "vbitclr_h", "vbitset_h", "vbitrev_h",
0179 "vseq_h", "vsle_h", "vsle_hu", "vslt_h", "vslt_hu",
0180 "vpackev_h", "vpackod_h", "vpickev_h", "vpickod_h",
0181 "vilvl_h", "vilvh_h"] in
0182 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0183 [llvm_v8i16_ty, llvm_v8i16_ty],
0184 [IntrNoMem]>;
0185
0186 foreach inst = ["vadd_w", "vsub_w",
0187 "vsadd_w", "vsadd_wu", "vssub_w", "vssub_wu",
0188 "vavg_w", "vavg_wu", "vavgr_w", "vavgr_wu",
0189 "vabsd_w", "vabsd_wu", "vadda_w",
0190 "vmax_w", "vmax_wu", "vmin_w", "vmin_wu",
0191 "vmul_w", "vmuh_w", "vmuh_wu",
0192 "vdiv_w", "vdiv_wu", "vmod_w", "vmod_wu", "vsigncov_w",
0193 "vsll_w", "vsrl_w", "vsra_w", "vrotr_w", "vsrlr_w", "vsrar_w",
0194 "vbitclr_w", "vbitset_w", "vbitrev_w",
0195 "vseq_w", "vsle_w", "vsle_wu", "vslt_w", "vslt_wu",
0196 "vpackev_w", "vpackod_w", "vpickev_w", "vpickod_w",
0197 "vilvl_w", "vilvh_w"] in
0198 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0199 [llvm_v4i32_ty, llvm_v4i32_ty],
0200 [IntrNoMem]>;
0201
0202 foreach inst = ["vadd_d", "vadd_q", "vsub_d", "vsub_q",
0203 "vsadd_d", "vsadd_du", "vssub_d", "vssub_du",
0204 "vhaddw_q_d", "vhaddw_qu_du", "vhsubw_q_d", "vhsubw_qu_du",
0205 "vaddwev_q_d", "vaddwod_q_d", "vsubwev_q_d", "vsubwod_q_d",
0206 "vaddwev_q_du", "vaddwod_q_du", "vsubwev_q_du", "vsubwod_q_du",
0207 "vaddwev_q_du_d", "vaddwod_q_du_d",
0208 "vavg_d", "vavg_du", "vavgr_d", "vavgr_du",
0209 "vabsd_d", "vabsd_du", "vadda_d",
0210 "vmax_d", "vmax_du", "vmin_d", "vmin_du",
0211 "vmul_d", "vmuh_d", "vmuh_du",
0212 "vmulwev_q_d", "vmulwod_q_d", "vmulwev_q_du", "vmulwod_q_du",
0213 "vmulwev_q_du_d", "vmulwod_q_du_d",
0214 "vdiv_d", "vdiv_du", "vmod_d", "vmod_du", "vsigncov_d",
0215 "vsll_d", "vsrl_d", "vsra_d", "vrotr_d", "vsrlr_d", "vsrar_d",
0216 "vbitclr_d", "vbitset_d", "vbitrev_d",
0217 "vseq_d", "vsle_d", "vsle_du", "vslt_d", "vslt_du",
0218 "vpackev_d", "vpackod_d", "vpickev_d", "vpickod_d",
0219 "vilvl_d", "vilvh_d"] in
0220 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
0221 [llvm_v2i64_ty, llvm_v2i64_ty],
0222 [IntrNoMem]>;
0223
0224 foreach inst = ["vaddi_bu", "vsubi_bu",
0225 "vmaxi_b", "vmaxi_bu", "vmini_b", "vmini_bu",
0226 "vsat_b", "vsat_bu",
0227 "vandi_b", "vori_b", "vxori_b", "vnori_b",
0228 "vslli_b", "vsrli_b", "vsrai_b", "vrotri_b",
0229 "vsrlri_b", "vsrari_b",
0230 "vbitclri_b", "vbitseti_b", "vbitrevi_b",
0231 "vseqi_b", "vslei_b", "vslei_bu", "vslti_b", "vslti_bu",
0232 "vreplvei_b", "vbsll_v", "vbsrl_v", "vshuf4i_b"] in
0233 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty],
0234 [llvm_v16i8_ty, llvm_i32_ty],
0235 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0236 foreach inst = ["vaddi_hu", "vsubi_hu",
0237 "vmaxi_h", "vmaxi_hu", "vmini_h", "vmini_hu",
0238 "vsat_h", "vsat_hu",
0239 "vslli_h", "vsrli_h", "vsrai_h", "vrotri_h",
0240 "vsrlri_h", "vsrari_h",
0241 "vbitclri_h", "vbitseti_h", "vbitrevi_h",
0242 "vseqi_h", "vslei_h", "vslei_hu", "vslti_h", "vslti_hu",
0243 "vreplvei_h", "vshuf4i_h"] in
0244 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0245 [llvm_v8i16_ty, llvm_i32_ty],
0246 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0247 foreach inst = ["vaddi_wu", "vsubi_wu",
0248 "vmaxi_w", "vmaxi_wu", "vmini_w", "vmini_wu",
0249 "vsat_w", "vsat_wu",
0250 "vslli_w", "vsrli_w", "vsrai_w", "vrotri_w",
0251 "vsrlri_w", "vsrari_w",
0252 "vbitclri_w", "vbitseti_w", "vbitrevi_w",
0253 "vseqi_w", "vslei_w", "vslei_wu", "vslti_w", "vslti_wu",
0254 "vreplvei_w", "vshuf4i_w"] in
0255 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0256 [llvm_v4i32_ty, llvm_i32_ty],
0257 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0258 foreach inst = ["vaddi_du", "vsubi_du",
0259 "vmaxi_d", "vmaxi_du", "vmini_d", "vmini_du",
0260 "vsat_d", "vsat_du",
0261 "vslli_d", "vsrli_d", "vsrai_d", "vrotri_d",
0262 "vsrlri_d", "vsrari_d",
0263 "vbitclri_d", "vbitseti_d", "vbitrevi_d",
0264 "vseqi_d", "vslei_d", "vslei_du", "vslti_d", "vslti_du",
0265 "vreplvei_d"] in
0266 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
0267 [llvm_v2i64_ty, llvm_i32_ty],
0268 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0269
0270 foreach inst = ["vhaddw_h_b", "vhaddw_hu_bu", "vhsubw_h_b", "vhsubw_hu_bu",
0271 "vaddwev_h_b", "vaddwod_h_b", "vsubwev_h_b", "vsubwod_h_b",
0272 "vaddwev_h_bu", "vaddwod_h_bu", "vsubwev_h_bu", "vsubwod_h_bu",
0273 "vaddwev_h_bu_b", "vaddwod_h_bu_b",
0274 "vmulwev_h_b", "vmulwod_h_b", "vmulwev_h_bu", "vmulwod_h_bu",
0275 "vmulwev_h_bu_b", "vmulwod_h_bu_b"] in
0276 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0277 [llvm_v16i8_ty, llvm_v16i8_ty],
0278 [IntrNoMem]>;
0279
0280 foreach inst = ["vhaddw_w_h", "vhaddw_wu_hu", "vhsubw_w_h", "vhsubw_wu_hu",
0281 "vaddwev_w_h", "vaddwod_w_h", "vsubwev_w_h", "vsubwod_w_h",
0282 "vaddwev_w_hu", "vaddwod_w_hu", "vsubwev_w_hu", "vsubwod_w_hu",
0283 "vaddwev_w_hu_h", "vaddwod_w_hu_h",
0284 "vmulwev_w_h", "vmulwod_w_h", "vmulwev_w_hu", "vmulwod_w_hu",
0285 "vmulwev_w_hu_h", "vmulwod_w_hu_h"] in
0286 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0287 [llvm_v8i16_ty, llvm_v8i16_ty],
0288 [IntrNoMem]>;
0289
0290 foreach inst = ["vhaddw_d_w", "vhaddw_du_wu", "vhsubw_d_w", "vhsubw_du_wu",
0291 "vaddwev_d_w", "vaddwod_d_w", "vsubwev_d_w", "vsubwod_d_w",
0292 "vaddwev_d_wu", "vaddwod_d_wu", "vsubwev_d_wu", "vsubwod_d_wu",
0293 "vaddwev_d_wu_w", "vaddwod_d_wu_w",
0294 "vmulwev_d_w", "vmulwod_d_w", "vmulwev_d_wu", "vmulwod_d_wu",
0295 "vmulwev_d_wu_w", "vmulwod_d_wu_w"] in
0296 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
0297 [llvm_v4i32_ty, llvm_v4i32_ty],
0298 [IntrNoMem]>;
0299
0300 foreach inst = ["vsrln_b_h", "vsran_b_h", "vsrlrn_b_h", "vsrarn_b_h",
0301 "vssrln_b_h", "vssran_b_h", "vssrln_bu_h", "vssran_bu_h",
0302 "vssrlrn_b_h", "vssrarn_b_h", "vssrlrn_bu_h", "vssrarn_bu_h"] in
0303 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty],
0304 [llvm_v8i16_ty, llvm_v8i16_ty],
0305 [IntrNoMem]>;
0306
0307 foreach inst = ["vsrln_h_w", "vsran_h_w", "vsrlrn_h_w", "vsrarn_h_w",
0308 "vssrln_h_w", "vssran_h_w", "vssrln_hu_w", "vssran_hu_w",
0309 "vssrlrn_h_w", "vssrarn_h_w", "vssrlrn_hu_w", "vssrarn_hu_w"] in
0310 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0311 [llvm_v4i32_ty, llvm_v4i32_ty],
0312 [IntrNoMem]>;
0313
0314 foreach inst = ["vsrln_w_d", "vsran_w_d", "vsrlrn_w_d", "vsrarn_w_d",
0315 "vssrln_w_d", "vssran_w_d", "vssrln_wu_d", "vssran_wu_d",
0316 "vssrlrn_w_d", "vssrarn_w_d", "vssrlrn_wu_d", "vssrarn_wu_d"] in
0317 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0318 [llvm_v2i64_ty, llvm_v2i64_ty],
0319 [IntrNoMem]>;
0320
0321 foreach inst = ["vmadd_b", "vmsub_b", "vfrstp_b", "vbitsel_v", "vshuf_b"] in
0322 def int_loongarch_lsx_#inst
0323 : VecInt<[llvm_v16i8_ty],
0324 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
0325 [IntrNoMem]>;
0326 foreach inst = ["vmadd_h", "vmsub_h", "vfrstp_h", "vshuf_h"] in
0327 def int_loongarch_lsx_#inst
0328 : VecInt<[llvm_v8i16_ty],
0329 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
0330 [IntrNoMem]>;
0331 foreach inst = ["vmadd_w", "vmsub_w", "vshuf_w"] in
0332 def int_loongarch_lsx_#inst
0333 : VecInt<[llvm_v4i32_ty],
0334 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
0335 [IntrNoMem]>;
0336 foreach inst = ["vmadd_d", "vmsub_d", "vshuf_d"] in
0337 def int_loongarch_lsx_#inst
0338 : VecInt<[llvm_v2i64_ty],
0339 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
0340 [IntrNoMem]>;
0341
0342 foreach inst = ["vsrlni_b_h", "vsrani_b_h", "vsrlrni_b_h", "vsrarni_b_h",
0343 "vssrlni_b_h", "vssrani_b_h", "vssrlni_bu_h", "vssrani_bu_h",
0344 "vssrlrni_b_h", "vssrarni_b_h", "vssrlrni_bu_h", "vssrarni_bu_h",
0345 "vfrstpi_b", "vbitseli_b", "vextrins_b"] in
0346 def int_loongarch_lsx_#inst
0347 : VecInt<[llvm_v16i8_ty],
0348 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
0349 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0350 foreach inst = ["vsrlni_h_w", "vsrani_h_w", "vsrlrni_h_w", "vsrarni_h_w",
0351 "vssrlni_h_w", "vssrani_h_w", "vssrlni_hu_w", "vssrani_hu_w",
0352 "vssrlrni_h_w", "vssrarni_h_w", "vssrlrni_hu_w", "vssrarni_hu_w",
0353 "vfrstpi_h", "vextrins_h"] in
0354 def int_loongarch_lsx_#inst
0355 : VecInt<[llvm_v8i16_ty],
0356 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
0357 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0358 foreach inst = ["vsrlni_w_d", "vsrani_w_d", "vsrlrni_w_d", "vsrarni_w_d",
0359 "vssrlni_w_d", "vssrani_w_d", "vssrlni_wu_d", "vssrani_wu_d",
0360 "vssrlrni_w_d", "vssrarni_w_d", "vssrlrni_wu_d", "vssrarni_wu_d",
0361 "vpermi_w", "vextrins_w"] in
0362 def int_loongarch_lsx_#inst
0363 : VecInt<[llvm_v4i32_ty],
0364 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
0365 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0366 foreach inst = ["vsrlni_d_q", "vsrani_d_q", "vsrlrni_d_q", "vsrarni_d_q",
0367 "vssrlni_d_q", "vssrani_d_q", "vssrlni_du_q", "vssrani_du_q",
0368 "vssrlrni_d_q", "vssrarni_d_q", "vssrlrni_du_q", "vssrarni_du_q",
0369 "vshuf4i_d", "vextrins_d"] in
0370 def int_loongarch_lsx_#inst
0371 : VecInt<[llvm_v2i64_ty],
0372 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty],
0373 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0374
0375 foreach inst = ["vmaddwev_h_b", "vmaddwod_h_b", "vmaddwev_h_bu",
0376 "vmaddwod_h_bu", "vmaddwev_h_bu_b", "vmaddwod_h_bu_b"] in
0377 def int_loongarch_lsx_#inst
0378 : VecInt<[llvm_v8i16_ty],
0379 [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
0380 [IntrNoMem]>;
0381 foreach inst = ["vmaddwev_w_h", "vmaddwod_w_h", "vmaddwev_w_hu",
0382 "vmaddwod_w_hu", "vmaddwev_w_hu_h", "vmaddwod_w_hu_h"] in
0383 def int_loongarch_lsx_#inst
0384 : VecInt<[llvm_v4i32_ty],
0385 [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
0386 [IntrNoMem]>;
0387 foreach inst = ["vmaddwev_d_w", "vmaddwod_d_w", "vmaddwev_d_wu",
0388 "vmaddwod_d_wu", "vmaddwev_d_wu_w", "vmaddwod_d_wu_w"] in
0389 def int_loongarch_lsx_#inst
0390 : VecInt<[llvm_v2i64_ty],
0391 [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty],
0392 [IntrNoMem]>;
0393 foreach inst = ["vmaddwev_q_d", "vmaddwod_q_d", "vmaddwev_q_du",
0394 "vmaddwod_q_du", "vmaddwev_q_du_d", "vmaddwod_q_du_d"] in
0395 def int_loongarch_lsx_#inst
0396 : VecInt<[llvm_v2i64_ty],
0397 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
0398 [IntrNoMem]>;
0399
0400 foreach inst = ["vsllwil_h_b", "vsllwil_hu_bu"] in
0401 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0402 [llvm_v16i8_ty, llvm_i32_ty],
0403 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0404 foreach inst = ["vsllwil_w_h", "vsllwil_wu_hu"] in
0405 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0406 [llvm_v8i16_ty, llvm_i32_ty],
0407 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0408 foreach inst = ["vsllwil_d_w", "vsllwil_du_wu"] in
0409 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
0410 [llvm_v4i32_ty, llvm_i32_ty],
0411 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0412
0413 foreach inst = ["vneg_b", "vmskltz_b", "vmskgez_b", "vmsknz_b",
0414 "vclo_b", "vclz_b", "vpcnt_b"] in
0415 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty],
0416 [IntrNoMem]>;
0417 foreach inst = ["vneg_h", "vmskltz_h", "vclo_h", "vclz_h", "vpcnt_h"] in
0418 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty],
0419 [IntrNoMem]>;
0420 foreach inst = ["vneg_w", "vmskltz_w", "vclo_w", "vclz_w", "vpcnt_w"] in
0421 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty],
0422 [IntrNoMem]>;
0423 foreach inst = ["vneg_d", "vexth_q_d", "vexth_qu_du", "vmskltz_d",
0424 "vextl_q_d", "vextl_qu_du", "vclo_d", "vclz_d", "vpcnt_d"] in
0425 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty],
0426 [IntrNoMem]>;
0427
0428 foreach inst = ["vexth_h_b", "vexth_hu_bu"] in
0429 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v16i8_ty],
0430 [IntrNoMem]>;
0431 foreach inst = ["vexth_w_h", "vexth_wu_hu"] in
0432 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v8i16_ty],
0433 [IntrNoMem]>;
0434 foreach inst = ["vexth_d_w", "vexth_du_wu"] in
0435 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4i32_ty],
0436 [IntrNoMem]>;
0437
0438 def int_loongarch_lsx_vldi : VecInt<[llvm_v2i64_ty], [llvm_i32_ty],
0439 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0440 def int_loongarch_lsx_vrepli_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty],
0441 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0442 def int_loongarch_lsx_vrepli_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty],
0443 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0444 def int_loongarch_lsx_vrepli_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty],
0445 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0446 def int_loongarch_lsx_vrepli_d : VecInt<[llvm_v2i64_ty], [llvm_i32_ty],
0447 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0448
0449 def int_loongarch_lsx_vreplgr2vr_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty],
0450 [IntrNoMem]>;
0451 def int_loongarch_lsx_vreplgr2vr_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty],
0452 [IntrNoMem]>;
0453 def int_loongarch_lsx_vreplgr2vr_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty],
0454 [IntrNoMem]>;
0455 def int_loongarch_lsx_vreplgr2vr_d : VecInt<[llvm_v2i64_ty], [llvm_i64_ty],
0456 [IntrNoMem]>;
0457
0458 def int_loongarch_lsx_vinsgr2vr_b
0459 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
0460 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0461 def int_loongarch_lsx_vinsgr2vr_h
0462 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
0463 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0464 def int_loongarch_lsx_vinsgr2vr_w
0465 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
0466 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0467 def int_loongarch_lsx_vinsgr2vr_d
0468 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
0469 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0470
0471 def int_loongarch_lsx_vreplve_b
0472 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
0473 def int_loongarch_lsx_vreplve_h
0474 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
0475 def int_loongarch_lsx_vreplve_w
0476 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
0477 def int_loongarch_lsx_vreplve_d
0478 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
0479
0480 foreach inst = ["vpickve2gr_b", "vpickve2gr_bu" ] in
0481 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty],
0482 [llvm_v16i8_ty, llvm_i32_ty],
0483 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0484 foreach inst = ["vpickve2gr_h", "vpickve2gr_hu" ] in
0485 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty],
0486 [llvm_v8i16_ty, llvm_i32_ty],
0487 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0488 foreach inst = ["vpickve2gr_w", "vpickve2gr_wu" ] in
0489 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty],
0490 [llvm_v4i32_ty, llvm_i32_ty],
0491 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0492 foreach inst = ["vpickve2gr_d", "vpickve2gr_du" ] in
0493 def int_loongarch_lsx_#inst : VecInt<[llvm_i64_ty],
0494 [llvm_v2i64_ty, llvm_i32_ty],
0495 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0496
0497 def int_loongarch_lsx_bz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty],
0498 [IntrNoMem]>;
0499 def int_loongarch_lsx_bz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty],
0500 [IntrNoMem]>;
0501 def int_loongarch_lsx_bz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty],
0502 [IntrNoMem]>;
0503 def int_loongarch_lsx_bz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty],
0504 [IntrNoMem]>;
0505 def int_loongarch_lsx_bz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty],
0506 [IntrNoMem]>;
0507
0508 def int_loongarch_lsx_bnz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty],
0509 [IntrNoMem]>;
0510 def int_loongarch_lsx_bnz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty],
0511 [IntrNoMem]>;
0512 def int_loongarch_lsx_bnz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty],
0513 [IntrNoMem]>;
0514 def int_loongarch_lsx_bnz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty],
0515 [IntrNoMem]>;
0516 def int_loongarch_lsx_bnz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty],
0517 [IntrNoMem]>;
0518
0519 // LSX Float
0520
0521 foreach inst = ["vfadd_s", "vfsub_s", "vfmul_s", "vfdiv_s",
0522 "vfmax_s", "vfmin_s", "vfmaxa_s", "vfmina_s"] in
0523 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty],
0524 [llvm_v4f32_ty, llvm_v4f32_ty],
0525 [IntrNoMem]>;
0526 foreach inst = ["vfadd_d", "vfsub_d", "vfmul_d", "vfdiv_d",
0527 "vfmax_d", "vfmin_d", "vfmaxa_d", "vfmina_d"] in
0528 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty],
0529 [llvm_v2f64_ty, llvm_v2f64_ty],
0530 [IntrNoMem]>;
0531
0532 foreach inst = ["vfmadd_s", "vfmsub_s", "vfnmadd_s", "vfnmsub_s"] in
0533 def int_loongarch_lsx_#inst
0534 : VecInt<[llvm_v4f32_ty],
0535 [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
0536 [IntrNoMem]>;
0537 foreach inst = ["vfmadd_d", "vfmsub_d", "vfnmadd_d", "vfnmsub_d"] in
0538 def int_loongarch_lsx_#inst
0539 : VecInt<[llvm_v2f64_ty],
0540 [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
0541 [IntrNoMem]>;
0542
0543 foreach inst = ["vflogb_s", "vfsqrt_s", "vfrecip_s", "vfrsqrt_s", "vfrint_s",
0544 "vfrecipe_s", "vfrsqrte_s",
0545 "vfrintrne_s", "vfrintrz_s", "vfrintrp_s", "vfrintrm_s"] in
0546 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4f32_ty],
0547 [IntrNoMem]>;
0548 foreach inst = ["vflogb_d", "vfsqrt_d", "vfrecip_d", "vfrsqrt_d", "vfrint_d",
0549 "vfrecipe_d", "vfrsqrte_d",
0550 "vfrintrne_d", "vfrintrz_d", "vfrintrp_d", "vfrintrm_d"] in
0551 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2f64_ty],
0552 [IntrNoMem]>;
0553
0554 foreach inst = ["vfcvtl_s_h", "vfcvth_s_h"] in
0555 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v8i16_ty],
0556 [IntrNoMem]>;
0557 foreach inst = ["vfcvtl_d_s", "vfcvth_d_s"] in
0558 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4f32_ty],
0559 [IntrNoMem]>;
0560
0561 foreach inst = ["vftintrne_w_s", "vftintrz_w_s", "vftintrp_w_s", "vftintrm_w_s",
0562 "vftint_w_s", "vftintrz_wu_s", "vftint_wu_s", "vfclass_s"] in
0563 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4f32_ty],
0564 [IntrNoMem]>;
0565 foreach inst = ["vftintrne_l_d", "vftintrz_l_d", "vftintrp_l_d", "vftintrm_l_d",
0566 "vftint_l_d", "vftintrz_lu_d", "vftint_lu_d", "vfclass_d"] in
0567 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2f64_ty],
0568 [IntrNoMem]>;
0569
0570 foreach inst = ["vftintrnel_l_s", "vftintrneh_l_s", "vftintrzl_l_s",
0571 "vftintrzh_l_s", "vftintrpl_l_s", "vftintrph_l_s",
0572 "vftintrml_l_s", "vftintrmh_l_s", "vftintl_l_s",
0573 "vftinth_l_s"] in
0574 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4f32_ty],
0575 [IntrNoMem]>;
0576
0577 foreach inst = ["vffint_s_w", "vffint_s_wu"] in
0578 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4i32_ty],
0579 [IntrNoMem]>;
0580 foreach inst = ["vffint_d_l", "vffint_d_lu"] in
0581 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2i64_ty],
0582 [IntrNoMem]>;
0583
0584 foreach inst = ["vffintl_d_w", "vffinth_d_w"] in
0585 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4i32_ty],
0586 [IntrNoMem]>;
0587
0588 foreach inst = ["vffint_s_l"] in
0589 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty],
0590 [llvm_v2i64_ty, llvm_v2i64_ty],
0591 [IntrNoMem]>;
0592 foreach inst = ["vftintrne_w_d", "vftintrz_w_d", "vftintrp_w_d", "vftintrm_w_d",
0593 "vftint_w_d"] in
0594 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0595 [llvm_v2f64_ty, llvm_v2f64_ty],
0596 [IntrNoMem]>;
0597
0598 foreach inst = ["vfcvt_h_s"] in
0599 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
0600 [llvm_v4f32_ty, llvm_v4f32_ty],
0601 [IntrNoMem]>;
0602 foreach inst = ["vfcvt_s_d"] in
0603 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty],
0604 [llvm_v2f64_ty, llvm_v2f64_ty],
0605 [IntrNoMem]>;
0606
0607 foreach inst = ["vfcmp_caf_s", "vfcmp_cun_s", "vfcmp_ceq_s", "vfcmp_cueq_s",
0608 "vfcmp_clt_s", "vfcmp_cult_s", "vfcmp_cle_s", "vfcmp_cule_s",
0609 "vfcmp_cne_s", "vfcmp_cor_s", "vfcmp_cune_s",
0610 "vfcmp_saf_s", "vfcmp_sun_s", "vfcmp_seq_s", "vfcmp_sueq_s",
0611 "vfcmp_slt_s", "vfcmp_sult_s", "vfcmp_sle_s", "vfcmp_sule_s",
0612 "vfcmp_sne_s", "vfcmp_sor_s", "vfcmp_sune_s"] in
0613 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
0614 [llvm_v4f32_ty, llvm_v4f32_ty],
0615 [IntrNoMem]>;
0616 foreach inst = ["vfcmp_caf_d", "vfcmp_cun_d", "vfcmp_ceq_d", "vfcmp_cueq_d",
0617 "vfcmp_clt_d", "vfcmp_cult_d", "vfcmp_cle_d", "vfcmp_cule_d",
0618 "vfcmp_cne_d", "vfcmp_cor_d", "vfcmp_cune_d",
0619 "vfcmp_saf_d", "vfcmp_sun_d", "vfcmp_seq_d", "vfcmp_sueq_d",
0620 "vfcmp_slt_d", "vfcmp_sult_d", "vfcmp_sle_d", "vfcmp_sule_d",
0621 "vfcmp_sne_d", "vfcmp_sor_d", "vfcmp_sune_d"] in
0622 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
0623 [llvm_v2f64_ty, llvm_v2f64_ty],
0624 [IntrNoMem]>;
0625
0626 // LSX load/store
0627 def int_loongarch_lsx_vld
0628 : DefaultAttrsVecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
0629 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
0630 def int_loongarch_lsx_vldx
0631 : DefaultAttrsVecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i64_ty],
0632 [IntrReadMem, IntrArgMemOnly]>;
0633 def int_loongarch_lsx_vldrepl_b
0634 : DefaultAttrsVecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
0635 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
0636 def int_loongarch_lsx_vldrepl_h
0637 : DefaultAttrsVecInt<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
0638 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
0639 def int_loongarch_lsx_vldrepl_w
0640 : DefaultAttrsVecInt<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
0641 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
0642 def int_loongarch_lsx_vldrepl_d
0643 : DefaultAttrsVecInt<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
0644 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
0645
0646 def int_loongarch_lsx_vst
0647 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty],
0648 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>;
0649 def int_loongarch_lsx_vstx
0650 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i64_ty],
0651 [IntrWriteMem, IntrArgMemOnly]>;
0652 def int_loongarch_lsx_vstelm_b
0653 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
0654 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
0655 def int_loongarch_lsx_vstelm_h
0656 : VecInt<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
0657 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
0658 def int_loongarch_lsx_vstelm_w
0659 : VecInt<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
0660 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
0661 def int_loongarch_lsx_vstelm_d
0662 : VecInt<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
0663 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
0664
0665 } // TargetPrefix = "loongarch"
0666
0667 //===----------------------------------------------------------------------===//
0668 // LASX
0669
0670 let TargetPrefix = "loongarch" in {
0671 foreach inst = ["xvadd_b", "xvsub_b",
0672 "xvsadd_b", "xvsadd_bu", "xvssub_b", "xvssub_bu",
0673 "xvavg_b", "xvavg_bu", "xvavgr_b", "xvavgr_bu",
0674 "xvabsd_b", "xvabsd_bu", "xvadda_b",
0675 "xvmax_b", "xvmax_bu", "xvmin_b", "xvmin_bu",
0676 "xvmul_b", "xvmuh_b", "xvmuh_bu",
0677 "xvdiv_b", "xvdiv_bu", "xvmod_b", "xvmod_bu", "xvsigncov_b",
0678 "xvand_v", "xvor_v", "xvxor_v", "xvnor_v", "xvandn_v", "xvorn_v",
0679 "xvsll_b", "xvsrl_b", "xvsra_b", "xvrotr_b", "xvsrlr_b", "xvsrar_b",
0680 "xvbitclr_b", "xvbitset_b", "xvbitrev_b",
0681 "xvseq_b", "xvsle_b", "xvsle_bu", "xvslt_b", "xvslt_bu",
0682 "xvpackev_b", "xvpackod_b", "xvpickev_b", "xvpickod_b",
0683 "xvilvl_b", "xvilvh_b"] in
0684 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty],
0685 [llvm_v32i8_ty, llvm_v32i8_ty],
0686 [IntrNoMem]>;
0687
0688 foreach inst = ["xvadd_h", "xvsub_h",
0689 "xvsadd_h", "xvsadd_hu", "xvssub_h", "xvssub_hu",
0690 "xvavg_h", "xvavg_hu", "xvavgr_h", "xvavgr_hu",
0691 "xvabsd_h", "xvabsd_hu", "xvadda_h",
0692 "xvmax_h", "xvmax_hu", "xvmin_h", "xvmin_hu",
0693 "xvmul_h", "xvmuh_h", "xvmuh_hu",
0694 "xvdiv_h", "xvdiv_hu", "xvmod_h", "xvmod_hu", "xvsigncov_h",
0695 "xvsll_h", "xvsrl_h", "xvsra_h", "xvrotr_h", "xvsrlr_h", "xvsrar_h",
0696 "xvbitclr_h", "xvbitset_h", "xvbitrev_h",
0697 "xvseq_h", "xvsle_h", "xvsle_hu", "xvslt_h", "xvslt_hu",
0698 "xvpackev_h", "xvpackod_h", "xvpickev_h", "xvpickod_h",
0699 "xvilvl_h", "xvilvh_h"] in
0700 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
0701 [llvm_v16i16_ty, llvm_v16i16_ty],
0702 [IntrNoMem]>;
0703
0704 foreach inst = ["xvadd_w", "xvsub_w",
0705 "xvsadd_w", "xvsadd_wu", "xvssub_w", "xvssub_wu",
0706 "xvavg_w", "xvavg_wu", "xvavgr_w", "xvavgr_wu",
0707 "xvabsd_w", "xvabsd_wu", "xvadda_w",
0708 "xvmax_w", "xvmax_wu", "xvmin_w", "xvmin_wu",
0709 "xvmul_w", "xvmuh_w", "xvmuh_wu",
0710 "xvdiv_w", "xvdiv_wu", "xvmod_w", "xvmod_wu", "xvsigncov_w",
0711 "xvsll_w", "xvsrl_w", "xvsra_w", "xvrotr_w", "xvsrlr_w", "xvsrar_w",
0712 "xvbitclr_w", "xvbitset_w", "xvbitrev_w",
0713 "xvseq_w", "xvsle_w", "xvsle_wu", "xvslt_w", "xvslt_wu",
0714 "xvpackev_w", "xvpackod_w", "xvpickev_w", "xvpickod_w",
0715 "xvilvl_w", "xvilvh_w", "xvperm_w"] in
0716 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
0717 [llvm_v8i32_ty, llvm_v8i32_ty],
0718 [IntrNoMem]>;
0719
0720 foreach inst = ["xvadd_d", "xvadd_q", "xvsub_d", "xvsub_q",
0721 "xvsadd_d", "xvsadd_du", "xvssub_d", "xvssub_du",
0722 "xvhaddw_q_d", "xvhaddw_qu_du", "xvhsubw_q_d", "xvhsubw_qu_du",
0723 "xvaddwev_q_d", "xvaddwod_q_d", "xvsubwev_q_d", "xvsubwod_q_d",
0724 "xvaddwev_q_du", "xvaddwod_q_du", "xvsubwev_q_du", "xvsubwod_q_du",
0725 "xvaddwev_q_du_d", "xvaddwod_q_du_d",
0726 "xvavg_d", "xvavg_du", "xvavgr_d", "xvavgr_du",
0727 "xvabsd_d", "xvabsd_du", "xvadda_d",
0728 "xvmax_d", "xvmax_du", "xvmin_d", "xvmin_du",
0729 "xvmul_d", "xvmuh_d", "xvmuh_du",
0730 "xvmulwev_q_d", "xvmulwod_q_d", "xvmulwev_q_du", "xvmulwod_q_du",
0731 "xvmulwev_q_du_d", "xvmulwod_q_du_d",
0732 "xvdiv_d", "xvdiv_du", "xvmod_d", "xvmod_du", "xvsigncov_d",
0733 "xvsll_d", "xvsrl_d", "xvsra_d", "xvrotr_d", "xvsrlr_d", "xvsrar_d",
0734 "xvbitclr_d", "xvbitset_d", "xvbitrev_d",
0735 "xvseq_d", "xvsle_d", "xvsle_du", "xvslt_d", "xvslt_du",
0736 "xvpackev_d", "xvpackod_d", "xvpickev_d", "xvpickod_d",
0737 "xvilvl_d", "xvilvh_d"] in
0738 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty],
0739 [llvm_v4i64_ty, llvm_v4i64_ty],
0740 [IntrNoMem]>;
0741
0742 foreach inst = ["xvaddi_bu", "xvsubi_bu",
0743 "xvmaxi_b", "xvmaxi_bu", "xvmini_b", "xvmini_bu",
0744 "xvsat_b", "xvsat_bu",
0745 "xvandi_b", "xvori_b", "xvxori_b", "xvnori_b",
0746 "xvslli_b", "xvsrli_b", "xvsrai_b", "xvrotri_b",
0747 "xvsrlri_b", "xvsrari_b",
0748 "xvbitclri_b", "xvbitseti_b", "xvbitrevi_b",
0749 "xvseqi_b", "xvslei_b", "xvslei_bu", "xvslti_b", "xvslti_bu",
0750 "xvrepl128vei_b", "xvbsll_v", "xvbsrl_v", "xvshuf4i_b"] in
0751 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty],
0752 [llvm_v32i8_ty, llvm_i32_ty],
0753 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0754 foreach inst = ["xvaddi_hu", "xvsubi_hu",
0755 "xvmaxi_h", "xvmaxi_hu", "xvmini_h", "xvmini_hu",
0756 "xvsat_h", "xvsat_hu",
0757 "xvslli_h", "xvsrli_h", "xvsrai_h", "xvrotri_h",
0758 "xvsrlri_h", "xvsrari_h",
0759 "xvbitclri_h", "xvbitseti_h", "xvbitrevi_h",
0760 "xvseqi_h", "xvslei_h", "xvslei_hu", "xvslti_h", "xvslti_hu",
0761 "xvrepl128vei_h", "xvshuf4i_h"] in
0762 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
0763 [llvm_v16i16_ty, llvm_i32_ty],
0764 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0765 foreach inst = ["xvaddi_wu", "xvsubi_wu",
0766 "xvmaxi_w", "xvmaxi_wu", "xvmini_w", "xvmini_wu",
0767 "xvsat_w", "xvsat_wu",
0768 "xvslli_w", "xvsrli_w", "xvsrai_w", "xvrotri_w",
0769 "xvsrlri_w", "xvsrari_w",
0770 "xvbitclri_w", "xvbitseti_w", "xvbitrevi_w",
0771 "xvseqi_w", "xvslei_w", "xvslei_wu", "xvslti_w", "xvslti_wu",
0772 "xvrepl128vei_w", "xvshuf4i_w", "xvpickve_w"] in
0773 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
0774 [llvm_v8i32_ty, llvm_i32_ty],
0775 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0776 foreach inst = ["xvaddi_du", "xvsubi_du",
0777 "xvmaxi_d", "xvmaxi_du", "xvmini_d", "xvmini_du",
0778 "xvsat_d", "xvsat_du",
0779 "xvslli_d", "xvsrli_d", "xvsrai_d", "xvrotri_d",
0780 "xvsrlri_d", "xvsrari_d",
0781 "xvbitclri_d", "xvbitseti_d", "xvbitrevi_d",
0782 "xvseqi_d", "xvslei_d", "xvslei_du", "xvslti_d", "xvslti_du",
0783 "xvrepl128vei_d", "xvpermi_d", "xvpickve_d"] in
0784 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty],
0785 [llvm_v4i64_ty, llvm_i32_ty],
0786 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0787
0788 foreach inst = ["xvhaddw_h_b", "xvhaddw_hu_bu", "xvhsubw_h_b", "xvhsubw_hu_bu",
0789 "xvaddwev_h_b", "xvaddwod_h_b", "xvsubwev_h_b", "xvsubwod_h_b",
0790 "xvaddwev_h_bu", "xvaddwod_h_bu", "xvsubwev_h_bu", "xvsubwod_h_bu",
0791 "xvaddwev_h_bu_b", "xvaddwod_h_bu_b",
0792 "xvmulwev_h_b", "xvmulwod_h_b", "xvmulwev_h_bu", "xvmulwod_h_bu",
0793 "xvmulwev_h_bu_b", "xvmulwod_h_bu_b"] in
0794 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
0795 [llvm_v32i8_ty, llvm_v32i8_ty],
0796 [IntrNoMem]>;
0797
0798 foreach inst = ["xvhaddw_w_h", "xvhaddw_wu_hu", "xvhsubw_w_h", "xvhsubw_wu_hu",
0799 "xvaddwev_w_h", "xvaddwod_w_h", "xvsubwev_w_h", "xvsubwod_w_h",
0800 "xvaddwev_w_hu", "xvaddwod_w_hu", "xvsubwev_w_hu", "xvsubwod_w_hu",
0801 "xvaddwev_w_hu_h", "xvaddwod_w_hu_h",
0802 "xvmulwev_w_h", "xvmulwod_w_h", "xvmulwev_w_hu", "xvmulwod_w_hu",
0803 "xvmulwev_w_hu_h", "xvmulwod_w_hu_h"] in
0804 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
0805 [llvm_v16i16_ty, llvm_v16i16_ty],
0806 [IntrNoMem]>;
0807
0808 foreach inst = ["xvhaddw_d_w", "xvhaddw_du_wu", "xvhsubw_d_w", "xvhsubw_du_wu",
0809 "xvaddwev_d_w", "xvaddwod_d_w", "xvsubwev_d_w", "xvsubwod_d_w",
0810 "xvaddwev_d_wu", "xvaddwod_d_wu", "xvsubwev_d_wu", "xvsubwod_d_wu",
0811 "xvaddwev_d_wu_w", "xvaddwod_d_wu_w",
0812 "xvmulwev_d_w", "xvmulwod_d_w", "xvmulwev_d_wu", "xvmulwod_d_wu",
0813 "xvmulwev_d_wu_w", "xvmulwod_d_wu_w"] in
0814 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty],
0815 [llvm_v8i32_ty, llvm_v8i32_ty],
0816 [IntrNoMem]>;
0817
0818 foreach inst = ["xvsrln_b_h", "xvsran_b_h", "xvsrlrn_b_h", "xvsrarn_b_h",
0819 "xvssrln_b_h", "xvssran_b_h", "xvssrln_bu_h", "xvssran_bu_h",
0820 "xvssrlrn_b_h", "xvssrarn_b_h", "xvssrlrn_bu_h", "xvssrarn_bu_h"] in
0821 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty],
0822 [llvm_v16i16_ty, llvm_v16i16_ty],
0823 [IntrNoMem]>;
0824
0825 foreach inst = ["xvsrln_h_w", "xvsran_h_w", "xvsrlrn_h_w", "xvsrarn_h_w",
0826 "xvssrln_h_w", "xvssran_h_w", "xvssrln_hu_w", "xvssran_hu_w",
0827 "xvssrlrn_h_w", "xvssrarn_h_w", "xvssrlrn_hu_w", "xvssrarn_hu_w"] in
0828 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
0829 [llvm_v8i32_ty, llvm_v8i32_ty],
0830 [IntrNoMem]>;
0831
0832 foreach inst = ["xvsrln_w_d", "xvsran_w_d", "xvsrlrn_w_d", "xvsrarn_w_d",
0833 "xvssrln_w_d", "xvssran_w_d", "xvssrln_wu_d", "xvssran_wu_d",
0834 "xvssrlrn_w_d", "xvssrarn_w_d", "xvssrlrn_wu_d", "xvssrarn_wu_d"] in
0835 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
0836 [llvm_v4i64_ty, llvm_v4i64_ty],
0837 [IntrNoMem]>;
0838
0839 foreach inst = ["xvmadd_b", "xvmsub_b", "xvfrstp_b", "xvbitsel_v", "xvshuf_b"] in
0840 def int_loongarch_lasx_#inst
0841 : VecInt<[llvm_v32i8_ty],
0842 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty],
0843 [IntrNoMem]>;
0844 foreach inst = ["xvmadd_h", "xvmsub_h", "xvfrstp_h", "xvshuf_h"] in
0845 def int_loongarch_lasx_#inst
0846 : VecInt<[llvm_v16i16_ty],
0847 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty],
0848 [IntrNoMem]>;
0849 foreach inst = ["xvmadd_w", "xvmsub_w", "xvshuf_w"] in
0850 def int_loongarch_lasx_#inst
0851 : VecInt<[llvm_v8i32_ty],
0852 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty],
0853 [IntrNoMem]>;
0854 foreach inst = ["xvmadd_d", "xvmsub_d", "xvshuf_d"] in
0855 def int_loongarch_lasx_#inst
0856 : VecInt<[llvm_v4i64_ty],
0857 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
0858 [IntrNoMem]>;
0859
0860 foreach inst = ["xvsrlni_b_h", "xvsrani_b_h", "xvsrlrni_b_h", "xvsrarni_b_h",
0861 "xvssrlni_b_h", "xvssrani_b_h", "xvssrlni_bu_h", "xvssrani_bu_h",
0862 "xvssrlrni_b_h", "xvssrarni_b_h", "xvssrlrni_bu_h", "xvssrarni_bu_h",
0863 "xvfrstpi_b", "xvbitseli_b", "xvextrins_b", "xvpermi_q"] in
0864 def int_loongarch_lasx_#inst
0865 : VecInt<[llvm_v32i8_ty],
0866 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty],
0867 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0868 foreach inst = ["xvsrlni_h_w", "xvsrani_h_w", "xvsrlrni_h_w", "xvsrarni_h_w",
0869 "xvssrlni_h_w", "xvssrani_h_w", "xvssrlni_hu_w", "xvssrani_hu_w",
0870 "xvssrlrni_h_w", "xvssrarni_h_w", "xvssrlrni_hu_w", "xvssrarni_hu_w",
0871 "xvfrstpi_h", "xvextrins_h"] in
0872 def int_loongarch_lasx_#inst
0873 : VecInt<[llvm_v16i16_ty],
0874 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i32_ty],
0875 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0876 foreach inst = ["xvsrlni_w_d", "xvsrani_w_d", "xvsrlrni_w_d", "xvsrarni_w_d",
0877 "xvssrlni_w_d", "xvssrani_w_d", "xvssrlni_wu_d", "xvssrani_wu_d",
0878 "xvssrlrni_w_d", "xvssrarni_w_d", "xvssrlrni_wu_d", "xvssrarni_wu_d",
0879 "xvpermi_w", "xvextrins_w", "xvinsve0_w"] in
0880 def int_loongarch_lasx_#inst
0881 : VecInt<[llvm_v8i32_ty],
0882 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty],
0883 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0884 foreach inst = ["xvsrlni_d_q", "xvsrani_d_q", "xvsrlrni_d_q", "xvsrarni_d_q",
0885 "xvssrlni_d_q", "xvssrani_d_q", "xvssrlni_du_q", "xvssrani_du_q",
0886 "xvssrlrni_d_q", "xvssrarni_d_q", "xvssrlrni_du_q", "xvssrarni_du_q",
0887 "xvshuf4i_d", "xvextrins_d", "xvinsve0_d"] in
0888 def int_loongarch_lasx_#inst
0889 : VecInt<[llvm_v4i64_ty],
0890 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty],
0891 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0892
0893 foreach inst = ["xvmaddwev_h_b", "xvmaddwod_h_b", "xvmaddwev_h_bu",
0894 "xvmaddwod_h_bu", "xvmaddwev_h_bu_b", "xvmaddwod_h_bu_b"] in
0895 def int_loongarch_lasx_#inst
0896 : VecInt<[llvm_v16i16_ty],
0897 [llvm_v16i16_ty, llvm_v32i8_ty, llvm_v32i8_ty],
0898 [IntrNoMem]>;
0899 foreach inst = ["xvmaddwev_w_h", "xvmaddwod_w_h", "xvmaddwev_w_hu",
0900 "xvmaddwod_w_hu", "xvmaddwev_w_hu_h", "xvmaddwod_w_hu_h"] in
0901 def int_loongarch_lasx_#inst
0902 : VecInt<[llvm_v8i32_ty],
0903 [llvm_v8i32_ty, llvm_v16i16_ty, llvm_v16i16_ty],
0904 [IntrNoMem]>;
0905 foreach inst = ["xvmaddwev_d_w", "xvmaddwod_d_w", "xvmaddwev_d_wu",
0906 "xvmaddwod_d_wu", "xvmaddwev_d_wu_w", "xvmaddwod_d_wu_w"] in
0907 def int_loongarch_lasx_#inst
0908 : VecInt<[llvm_v4i64_ty],
0909 [llvm_v4i64_ty, llvm_v8i32_ty, llvm_v8i32_ty],
0910 [IntrNoMem]>;
0911 foreach inst = ["xvmaddwev_q_d", "xvmaddwod_q_d", "xvmaddwev_q_du",
0912 "xvmaddwod_q_du", "xvmaddwev_q_du_d", "xvmaddwod_q_du_d"] in
0913 def int_loongarch_lasx_#inst
0914 : VecInt<[llvm_v4i64_ty],
0915 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
0916 [IntrNoMem]>;
0917
0918 foreach inst = ["xvsllwil_h_b", "xvsllwil_hu_bu"] in
0919 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
0920 [llvm_v32i8_ty, llvm_i32_ty],
0921 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0922 foreach inst = ["xvsllwil_w_h", "xvsllwil_wu_hu"] in
0923 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
0924 [llvm_v16i16_ty, llvm_i32_ty],
0925 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0926 foreach inst = ["xvsllwil_d_w", "xvsllwil_du_wu"] in
0927 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty],
0928 [llvm_v8i32_ty, llvm_i32_ty],
0929 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
0930
0931 foreach inst = ["xvneg_b", "xvmskltz_b", "xvmskgez_b", "xvmsknz_b",
0932 "xvclo_b", "xvclz_b", "xvpcnt_b",
0933 "xvreplve0_b", "xvreplve0_q"] in
0934 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty],
0935 [IntrNoMem]>;
0936 foreach inst = ["xvneg_h", "xvmskltz_h", "xvclo_h", "xvclz_h", "xvpcnt_h",
0937 "xvreplve0_h"] in
0938 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty],
0939 [IntrNoMem]>;
0940 foreach inst = ["xvneg_w", "xvmskltz_w", "xvclo_w", "xvclz_w", "xvpcnt_w",
0941 "xvreplve0_w"] in
0942 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty],
0943 [IntrNoMem]>;
0944 foreach inst = ["xvneg_d", "xvexth_q_d", "xvexth_qu_du", "xvmskltz_d",
0945 "xvextl_q_d", "xvextl_qu_du", "xvclo_d", "xvclz_d", "xvpcnt_d",
0946 "xvreplve0_d"] in
0947 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty],
0948 [IntrNoMem]>;
0949
0950 foreach inst = ["xvexth_h_b", "xvexth_hu_bu", "vext2xv_h_b", "vext2xv_hu_bu"] in
0951 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v32i8_ty],
0952 [IntrNoMem]>;
0953 foreach inst = ["xvexth_w_h", "xvexth_wu_hu", "vext2xv_w_h", "vext2xv_wu_hu"] in
0954 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v16i16_ty],
0955 [IntrNoMem]>;
0956 foreach inst = ["xvexth_d_w", "xvexth_du_wu", "vext2xv_d_w", "vext2xv_du_wu"] in
0957 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8i32_ty],
0958 [IntrNoMem]>;
0959
0960 foreach inst = ["vext2xv_w_b", "vext2xv_wu_bu"] in
0961 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v32i8_ty],
0962 [IntrNoMem]>;
0963 foreach inst = ["vext2xv_d_h", "vext2xv_du_hu"] in
0964 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v16i16_ty],
0965 [IntrNoMem]>;
0966
0967 foreach inst = ["vext2xv_d_b", "vext2xv_du_bu"] in
0968 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v32i8_ty],
0969 [IntrNoMem]>;
0970
0971 def int_loongarch_lasx_xvldi : VecInt<[llvm_v4i64_ty], [llvm_i32_ty],
0972 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0973 def int_loongarch_lasx_xvrepli_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty],
0974 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0975 def int_loongarch_lasx_xvrepli_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty],
0976 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0977 def int_loongarch_lasx_xvrepli_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty],
0978 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0979 def int_loongarch_lasx_xvrepli_d : VecInt<[llvm_v4i64_ty], [llvm_i32_ty],
0980 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
0981
0982 def int_loongarch_lasx_xvreplgr2vr_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty],
0983 [IntrNoMem]>;
0984 def int_loongarch_lasx_xvreplgr2vr_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty],
0985 [IntrNoMem]>;
0986 def int_loongarch_lasx_xvreplgr2vr_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty],
0987 [IntrNoMem]>;
0988 def int_loongarch_lasx_xvreplgr2vr_d : VecInt<[llvm_v4i64_ty], [llvm_i64_ty],
0989 [IntrNoMem]>;
0990
0991 def int_loongarch_lasx_xvinsgr2vr_w
0992 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty],
0993 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0994 def int_loongarch_lasx_xvinsgr2vr_d
0995 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i64_ty, llvm_i32_ty],
0996 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
0997
0998 def int_loongarch_lasx_xvreplve_b
0999 : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
1000 def int_loongarch_lasx_xvreplve_h
1001 : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_i32_ty], [IntrNoMem]>;
1002 def int_loongarch_lasx_xvreplve_w
1003 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty], [IntrNoMem]>;
1004 def int_loongarch_lasx_xvreplve_d
1005 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i32_ty], [IntrNoMem]>;
1006
1007 foreach inst = ["xvpickve2gr_w", "xvpickve2gr_wu" ] in
1008 def int_loongarch_lasx_#inst : VecInt<[llvm_i32_ty],
1009 [llvm_v8i32_ty, llvm_i32_ty],
1010 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1011 foreach inst = ["xvpickve2gr_d", "xvpickve2gr_du" ] in
1012 def int_loongarch_lasx_#inst : VecInt<[llvm_i64_ty],
1013 [llvm_v4i64_ty, llvm_i32_ty],
1014 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1015
1016 def int_loongarch_lasx_xbz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty],
1017 [IntrNoMem]>;
1018 def int_loongarch_lasx_xbz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty],
1019 [IntrNoMem]>;
1020 def int_loongarch_lasx_xbz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty],
1021 [IntrNoMem]>;
1022 def int_loongarch_lasx_xbz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty],
1023 [IntrNoMem]>;
1024 def int_loongarch_lasx_xbz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty],
1025 [IntrNoMem]>;
1026
1027 def int_loongarch_lasx_xbnz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty],
1028 [IntrNoMem]>;
1029 def int_loongarch_lasx_xbnz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty],
1030 [IntrNoMem]>;
1031 def int_loongarch_lasx_xbnz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty],
1032 [IntrNoMem]>;
1033 def int_loongarch_lasx_xbnz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty],
1034 [IntrNoMem]>;
1035 def int_loongarch_lasx_xbnz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty],
1036 [IntrNoMem]>;
1037
1038 // LASX Float
1039
1040 foreach inst = ["xvfadd_s", "xvfsub_s", "xvfmul_s", "xvfdiv_s",
1041 "xvfmax_s", "xvfmin_s", "xvfmaxa_s", "xvfmina_s"] in
1042 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty],
1043 [llvm_v8f32_ty, llvm_v8f32_ty],
1044 [IntrNoMem]>;
1045 foreach inst = ["xvfadd_d", "xvfsub_d", "xvfmul_d", "xvfdiv_d",
1046 "xvfmax_d", "xvfmin_d", "xvfmaxa_d", "xvfmina_d"] in
1047 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty],
1048 [llvm_v4f64_ty, llvm_v4f64_ty],
1049 [IntrNoMem]>;
1050
1051 foreach inst = ["xvfmadd_s", "xvfmsub_s", "xvfnmadd_s", "xvfnmsub_s"] in
1052 def int_loongarch_lasx_#inst
1053 : VecInt<[llvm_v8f32_ty],
1054 [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
1055 [IntrNoMem]>;
1056 foreach inst = ["xvfmadd_d", "xvfmsub_d", "xvfnmadd_d", "xvfnmsub_d"] in
1057 def int_loongarch_lasx_#inst
1058 : VecInt<[llvm_v4f64_ty],
1059 [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
1060 [IntrNoMem]>;
1061
1062 foreach inst = ["xvflogb_s", "xvfsqrt_s", "xvfrecip_s", "xvfrsqrt_s", "xvfrint_s",
1063 "xvfrecipe_s", "xvfrsqrte_s",
1064 "xvfrintrne_s", "xvfrintrz_s", "xvfrintrp_s", "xvfrintrm_s"] in
1065 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty],
1066 [IntrNoMem]>;
1067 foreach inst = ["xvflogb_d", "xvfsqrt_d", "xvfrecip_d", "xvfrsqrt_d", "xvfrint_d",
1068 "xvfrecipe_d", "xvfrsqrte_d",
1069 "xvfrintrne_d", "xvfrintrz_d", "xvfrintrp_d", "xvfrintrm_d"] in
1070 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty],
1071 [IntrNoMem]>;
1072
1073 foreach inst = ["xvfcvtl_s_h", "xvfcvth_s_h"] in
1074 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v16i16_ty],
1075 [IntrNoMem]>;
1076 foreach inst = ["xvfcvtl_d_s", "xvfcvth_d_s"] in
1077 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8f32_ty],
1078 [IntrNoMem]>;
1079
1080 foreach inst = ["xvftintrne_w_s", "xvftintrz_w_s", "xvftintrp_w_s", "xvftintrm_w_s",
1081 "xvftint_w_s", "xvftintrz_wu_s", "xvftint_wu_s", "xvfclass_s"] in
1082 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8f32_ty],
1083 [IntrNoMem]>;
1084 foreach inst = ["xvftintrne_l_d", "xvftintrz_l_d", "xvftintrp_l_d", "xvftintrm_l_d",
1085 "xvftint_l_d", "xvftintrz_lu_d", "xvftint_lu_d", "xvfclass_d"] in
1086 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4f64_ty],
1087 [IntrNoMem]>;
1088
1089 foreach inst = ["xvftintrnel_l_s", "xvftintrneh_l_s", "xvftintrzl_l_s",
1090 "xvftintrzh_l_s", "xvftintrpl_l_s", "xvftintrph_l_s",
1091 "xvftintrml_l_s", "xvftintrmh_l_s", "xvftintl_l_s",
1092 "xvftinth_l_s"] in
1093 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8f32_ty],
1094 [IntrNoMem]>;
1095
1096 foreach inst = ["xvffint_s_w", "xvffint_s_wu"] in
1097 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8i32_ty],
1098 [IntrNoMem]>;
1099 foreach inst = ["xvffint_d_l", "xvffint_d_lu"] in
1100 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4i64_ty],
1101 [IntrNoMem]>;
1102
1103 foreach inst = ["xvffintl_d_w", "xvffinth_d_w"] in
1104 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8i32_ty],
1105 [IntrNoMem]>;
1106
1107 foreach inst = ["xvffint_s_l"] in
1108 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty],
1109 [llvm_v4i64_ty, llvm_v4i64_ty],
1110 [IntrNoMem]>;
1111 foreach inst = ["xvftintrne_w_d", "xvftintrz_w_d", "xvftintrp_w_d", "xvftintrm_w_d",
1112 "xvftint_w_d"] in
1113 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
1114 [llvm_v4f64_ty, llvm_v4f64_ty],
1115 [IntrNoMem]>;
1116
1117 foreach inst = ["xvfcvt_h_s"] in
1118 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty],
1119 [llvm_v8f32_ty, llvm_v8f32_ty],
1120 [IntrNoMem]>;
1121 foreach inst = ["xvfcvt_s_d"] in
1122 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty],
1123 [llvm_v4f64_ty, llvm_v4f64_ty],
1124 [IntrNoMem]>;
1125
1126 foreach inst = ["xvfcmp_caf_s", "xvfcmp_cun_s", "xvfcmp_ceq_s", "xvfcmp_cueq_s",
1127 "xvfcmp_clt_s", "xvfcmp_cult_s", "xvfcmp_cle_s", "xvfcmp_cule_s",
1128 "xvfcmp_cne_s", "xvfcmp_cor_s", "xvfcmp_cune_s",
1129 "xvfcmp_saf_s", "xvfcmp_sun_s", "xvfcmp_seq_s", "xvfcmp_sueq_s",
1130 "xvfcmp_slt_s", "xvfcmp_sult_s", "xvfcmp_sle_s", "xvfcmp_sule_s",
1131 "xvfcmp_sne_s", "xvfcmp_sor_s", "xvfcmp_sune_s"] in
1132 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty],
1133 [llvm_v8f32_ty, llvm_v8f32_ty],
1134 [IntrNoMem]>;
1135 foreach inst = ["xvfcmp_caf_d", "xvfcmp_cun_d", "xvfcmp_ceq_d", "xvfcmp_cueq_d",
1136 "xvfcmp_clt_d", "xvfcmp_cult_d", "xvfcmp_cle_d", "xvfcmp_cule_d",
1137 "xvfcmp_cne_d", "xvfcmp_cor_d", "xvfcmp_cune_d",
1138 "xvfcmp_saf_d", "xvfcmp_sun_d", "xvfcmp_seq_d", "xvfcmp_sueq_d",
1139 "xvfcmp_slt_d", "xvfcmp_sult_d", "xvfcmp_sle_d", "xvfcmp_sule_d",
1140 "xvfcmp_sne_d", "xvfcmp_sor_d", "xvfcmp_sune_d"] in
1141 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty],
1142 [llvm_v4f64_ty, llvm_v4f64_ty],
1143 [IntrNoMem]>;
1144
1145 def int_loongarch_lasx_xvpickve_w_f
1146 : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_i32_ty],
1147 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1148 def int_loongarch_lasx_xvpickve_d_f
1149 : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_i32_ty],
1150 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1151
1152 // LASX load/store
1153 def int_loongarch_lasx_xvld
1154 : DefaultAttrsVecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty],
1155 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
1156 def int_loongarch_lasx_xvldx
1157 : DefaultAttrsVecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i64_ty],
1158 [IntrReadMem, IntrArgMemOnly]>;
1159 def int_loongarch_lasx_xvldrepl_b
1160 : DefaultAttrsVecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty],
1161 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
1162 def int_loongarch_lasx_xvldrepl_h
1163 : DefaultAttrsVecInt<[llvm_v16i16_ty], [llvm_ptr_ty, llvm_i32_ty],
1164 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
1165 def int_loongarch_lasx_xvldrepl_w
1166 : DefaultAttrsVecInt<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_i32_ty],
1167 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
1168 def int_loongarch_lasx_xvldrepl_d
1169 : DefaultAttrsVecInt<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_i32_ty],
1170 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
1171
1172 def int_loongarch_lasx_xvst
1173 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty],
1174 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>;
1175 def int_loongarch_lasx_xvstx
1176 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i64_ty],
1177 [IntrWriteMem, IntrArgMemOnly]>;
1178 def int_loongarch_lasx_xvstelm_b
1179 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
1180 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
1181 def int_loongarch_lasx_xvstelm_h
1182 : VecInt<[], [llvm_v16i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
1183 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
1184 def int_loongarch_lasx_xvstelm_w
1185 : VecInt<[], [llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
1186 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
1187 def int_loongarch_lasx_xvstelm_d
1188 : VecInt<[], [llvm_v4i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
1189 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
1190 } // TargetPrefix = "loongarch"
