llvm/IR/IntrinsicsHexagonDep.td

0001 //===----------------------------------------------------------------------===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 // Automatically generated file, do not edit!
0009 //===----------------------------------------------------------------------===//
0010
0011 // tag : A2_abs
0012 class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,
0013       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0014   : Hexagon_Intrinsic<GCCIntSuffix,
0015        [llvm_i32_ty], [llvm_i32_ty],
0016        intr_properties>;
0017
0018 // tag : A2_absp
0019 class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix,
0020       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0021   : Hexagon_Intrinsic<GCCIntSuffix,
0022        [llvm_i64_ty], [llvm_i64_ty],
0023        intr_properties>;
0024
0025 // tag : A2_add
0026 class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,
0027       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0028   : Hexagon_Intrinsic<GCCIntSuffix,
0029        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
0030        intr_properties>;
0031
0032 // tag : A2_addp
0033 class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix,
0034       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0035   : Hexagon_Intrinsic<GCCIntSuffix,
0036        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
0037        intr_properties>;
0038
0039 // tag : A2_addsp
0040 class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix,
0041       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0042   : Hexagon_Intrinsic<GCCIntSuffix,
0043        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],
0044        intr_properties>;
0045
0046 // tag : A2_combineii
0047 class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix,
0048       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0049   : Hexagon_Intrinsic<GCCIntSuffix,
0050        [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],
0051        intr_properties>;
0052
0053 // tag : A2_roundsat
0054 class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix,
0055       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0056   : Hexagon_Intrinsic<GCCIntSuffix,
0057        [llvm_i32_ty], [llvm_i64_ty],
0058        intr_properties>;
0059
0060 // tag : A2_sxtw
0061 class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,
0062       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0063   : Hexagon_Intrinsic<GCCIntSuffix,
0064        [llvm_i64_ty], [llvm_i32_ty],
0065        intr_properties>;
0066
0067 // tag : A2_vcmpbeq
0068 class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,
0069       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0070   : Hexagon_Intrinsic<GCCIntSuffix,
0071        [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
0072        intr_properties>;
0073
0074 // tag : A2_vraddub_acc
0075 class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix,
0076       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0077   : Hexagon_Intrinsic<GCCIntSuffix,
0078        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
0079        intr_properties>;
0080
0081 // tag : A4_boundscheck
0082 class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix,
0083       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0084   : Hexagon_Intrinsic<GCCIntSuffix,
0085        [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],
0086        intr_properties>;
0087
0088 // tag : A4_tlbmatch
0089 class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix,
0090       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0091   : Hexagon_Intrinsic<GCCIntSuffix,
0092        [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],
0093        intr_properties>;
0094
0095 // tag : A4_vrmaxh
0096 class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,
0097       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0098   : Hexagon_Intrinsic<GCCIntSuffix,
0099        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
0100        intr_properties>;
0101
0102 // tag : A7_croundd_ri
0103 class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,
0104       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0105   : Hexagon_Intrinsic<GCCIntSuffix,
0106        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
0107        intr_properties>;
0108
0109 // tag : C2_mux
0110 class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,
0111       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0112   : Hexagon_Intrinsic<GCCIntSuffix,
0113        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
0114        intr_properties>;
0115
0116 // tag : C2_vmux
0117 class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix,
0118       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0119   : Hexagon_Intrinsic<GCCIntSuffix,
0120        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],
0121        intr_properties>;
0122
0123 // tag : F2_conv_d2df
0124 class Hexagon_double_i64_Intrinsic<string GCCIntSuffix,
0125       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0126   : Hexagon_Intrinsic<GCCIntSuffix,
0127        [llvm_double_ty], [llvm_i64_ty],
0128        intr_properties>;
0129
0130 // tag : F2_conv_d2sf
0131 class Hexagon_float_i64_Intrinsic<string GCCIntSuffix,
0132       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0133   : Hexagon_Intrinsic<GCCIntSuffix,
0134        [llvm_float_ty], [llvm_i64_ty],
0135        intr_properties>;
0136
0137 // tag : F2_conv_df2d
0138 class Hexagon_i64_double_Intrinsic<string GCCIntSuffix,
0139       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0140   : Hexagon_Intrinsic<GCCIntSuffix,
0141        [llvm_i64_ty], [llvm_double_ty],
0142        intr_properties>;
0143
0144 // tag : F2_conv_df2sf
0145 class Hexagon_float_double_Intrinsic<string GCCIntSuffix,
0146       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0147   : Hexagon_Intrinsic<GCCIntSuffix,
0148        [llvm_float_ty], [llvm_double_ty],
0149        intr_properties>;
0150
0151 // tag : F2_conv_df2uw
0152 class Hexagon_i32_double_Intrinsic<string GCCIntSuffix,
0153       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0154   : Hexagon_Intrinsic<GCCIntSuffix,
0155        [llvm_i32_ty], [llvm_double_ty],
0156        intr_properties>;
0157
0158 // tag : F2_conv_sf2d
0159 class Hexagon_i64_float_Intrinsic<string GCCIntSuffix,
0160       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0161   : Hexagon_Intrinsic<GCCIntSuffix,
0162        [llvm_i64_ty], [llvm_float_ty],
0163        intr_properties>;
0164
0165 // tag : F2_conv_sf2df
0166 class Hexagon_double_float_Intrinsic<string GCCIntSuffix,
0167       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0168   : Hexagon_Intrinsic<GCCIntSuffix,
0169        [llvm_double_ty], [llvm_float_ty],
0170        intr_properties>;
0171
0172 // tag : F2_conv_sf2uw
0173 class Hexagon_i32_float_Intrinsic<string GCCIntSuffix,
0174       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0175   : Hexagon_Intrinsic<GCCIntSuffix,
0176        [llvm_i32_ty], [llvm_float_ty],
0177        intr_properties>;
0178
0179 // tag : F2_conv_uw2df
0180 class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,
0181       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0182   : Hexagon_Intrinsic<GCCIntSuffix,
0183        [llvm_double_ty], [llvm_i32_ty],
0184        intr_properties>;
0185
0186 // tag : F2_conv_uw2sf
0187 class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,
0188       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0189   : Hexagon_Intrinsic<GCCIntSuffix,
0190        [llvm_float_ty], [llvm_i32_ty],
0191        intr_properties>;
0192
0193 // tag : F2_dfadd
0194 class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix,
0195       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0196   : Hexagon_Intrinsic<GCCIntSuffix,
0197        [llvm_double_ty], [llvm_double_ty,llvm_double_ty],
0198        intr_properties>;
0199
0200 // tag : F2_dfclass
0201 class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,
0202       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0203   : Hexagon_Intrinsic<GCCIntSuffix,
0204        [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],
0205        intr_properties>;
0206
0207 // tag : F2_dfcmpeq
0208 class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix,
0209       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0210   : Hexagon_Intrinsic<GCCIntSuffix,
0211        [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],
0212        intr_properties>;
0213
0214 // tag : F2_dfmpyhh
0215 class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix,
0216       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0217   : Hexagon_Intrinsic<GCCIntSuffix,
0218        [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty],
0219        intr_properties>;
0220
0221 // tag : F2_sfadd
0222 class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix,
0223       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0224   : Hexagon_Intrinsic<GCCIntSuffix,
0225        [llvm_float_ty], [llvm_float_ty,llvm_float_ty],
0226        intr_properties>;
0227
0228 // tag : F2_sfclass
0229 class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix,
0230       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0231   : Hexagon_Intrinsic<GCCIntSuffix,
0232        [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],
0233        intr_properties>;
0234
0235 // tag : F2_sfcmpeq
0236 class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix,
0237       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0238   : Hexagon_Intrinsic<GCCIntSuffix,
0239        [llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
0240        intr_properties>;
0241
0242 // tag : F2_sffixupr
0243 class Hexagon_float_float_Intrinsic<string GCCIntSuffix,
0244       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0245   : Hexagon_Intrinsic<GCCIntSuffix,
0246        [llvm_float_ty], [llvm_float_ty],
0247        intr_properties>;
0248
0249 // tag : F2_sffma
0250 class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix,
0251       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0252   : Hexagon_Intrinsic<GCCIntSuffix,
0253        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],
0254        intr_properties>;
0255
0256 // tag : F2_sffma_sc
0257 class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix,
0258       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0259   : Hexagon_Intrinsic<GCCIntSuffix,
0260        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],
0261        intr_properties>;
0262
0263 // tag : M2_cmaci_s0
0264 class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix,
0265       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0266   : Hexagon_Intrinsic<GCCIntSuffix,
0267        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
0268        intr_properties>;
0269
0270 // tag : S2_insert
0271 class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix,
0272       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0273   : Hexagon_Intrinsic<GCCIntSuffix,
0274        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
0275        intr_properties>;
0276
0277 // tag : S2_insert_rp
0278 class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix,
0279       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0280   : Hexagon_Intrinsic<GCCIntSuffix,
0281        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],
0282        intr_properties>;
0283
0284 // tag : S2_insertp
0285 class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,
0286       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0287   : Hexagon_Intrinsic<GCCIntSuffix,
0288        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
0289        intr_properties>;
0290
0291 // tag : V6_extractw
0292 class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix,
0293       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0294   : Hexagon_Intrinsic<GCCIntSuffix,
0295        [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
0296        intr_properties>;
0297
0298 // tag : V6_extractw
0299 class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix,
0300       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0301   : Hexagon_Intrinsic<GCCIntSuffix,
0302        [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
0303        intr_properties>;
0304
0305 // tag : V6_hi
0306 class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix,
0307       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0308   : Hexagon_Intrinsic<GCCIntSuffix,
0309        [llvm_v16i32_ty], [llvm_v32i32_ty],
0310        intr_properties>;
0311
0312 // tag : V6_hi
0313 class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix,
0314       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0315   : Hexagon_Intrinsic<GCCIntSuffix,
0316        [llvm_v32i32_ty], [llvm_v64i32_ty],
0317        intr_properties>;
0318
0319 // tag : V6_lvsplatb
0320 class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix,
0321       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0322   : Hexagon_Intrinsic<GCCIntSuffix,
0323        [llvm_v16i32_ty], [llvm_i32_ty],
0324        intr_properties>;
0325
0326 // tag : V6_lvsplatb
0327 class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix,
0328       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0329   : Hexagon_Intrinsic<GCCIntSuffix,
0330        [llvm_v32i32_ty], [llvm_i32_ty],
0331        intr_properties>;
0332
0333 // tag : V6_pred_and
0334 class Hexagon_v64i1_v64i1v64i1_Intrinsic<string GCCIntSuffix,
0335       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0336   : Hexagon_Intrinsic<GCCIntSuffix,
0337        [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty],
0338        intr_properties>;
0339
0340 // tag : V6_pred_and
0341 class Hexagon_v128i1_v128i1v128i1_Intrinsic<string GCCIntSuffix,
0342       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0343   : Hexagon_Intrinsic<GCCIntSuffix,
0344        [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty],
0345        intr_properties>;
0346
0347 // tag : V6_pred_not
0348 class Hexagon_v64i1_v64i1_Intrinsic<string GCCIntSuffix,
0349       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0350   : Hexagon_Intrinsic<GCCIntSuffix,
0351        [llvm_v64i1_ty], [llvm_v64i1_ty],
0352        intr_properties>;
0353
0354 // tag : V6_pred_not
0355 class Hexagon_v128i1_v128i1_Intrinsic<string GCCIntSuffix,
0356       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0357   : Hexagon_Intrinsic<GCCIntSuffix,
0358        [llvm_v128i1_ty], [llvm_v128i1_ty],
0359        intr_properties>;
0360
0361 // tag : V6_pred_scalar2
0362 class Hexagon_v64i1_i32_Intrinsic<string GCCIntSuffix,
0363       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0364   : Hexagon_Intrinsic<GCCIntSuffix,
0365        [llvm_v64i1_ty], [llvm_i32_ty],
0366        intr_properties>;
0367
0368 // tag : V6_pred_scalar2
0369 class Hexagon_v128i1_i32_Intrinsic<string GCCIntSuffix,
0370       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0371   : Hexagon_Intrinsic<GCCIntSuffix,
0372        [llvm_v128i1_ty], [llvm_i32_ty],
0373        intr_properties>;
0374
0375 // tag : V6_v6mpyhubs10
0376 class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
0377       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0378   : Hexagon_Intrinsic<GCCIntSuffix,
0379        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0380        intr_properties>;
0381
0382 // tag : V6_v6mpyhubs10
0383 class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix,
0384       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0385   : Hexagon_Intrinsic<GCCIntSuffix,
0386        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
0387        intr_properties>;
0388
0389 // tag : V6_v6mpyhubs10_vxx
0390 class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
0391       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0392   : Hexagon_Intrinsic<GCCIntSuffix,
0393        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0394        intr_properties>;
0395
0396 // tag : V6_v6mpyhubs10_vxx
0397 class Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<string GCCIntSuffix,
0398       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0399   : Hexagon_Intrinsic<GCCIntSuffix,
0400        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
0401        intr_properties>;
0402
0403 // tag : V6_vS32b_nqpred_ai
0404 class Hexagon__v64i1ptrv16i32_Intrinsic<string GCCIntSuffix,
0405       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0406   : Hexagon_Intrinsic<GCCIntSuffix,
0407        [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
0408        intr_properties>;
0409
0410 // tag : V6_vS32b_nqpred_ai
0411 class Hexagon__v128i1ptrv32i32_Intrinsic<string GCCIntSuffix,
0412       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0413   : Hexagon_Intrinsic<GCCIntSuffix,
0414        [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
0415        intr_properties>;
0416
0417 // tag : V6_vabs_hf
0418 class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix,
0419       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0420   : Hexagon_Intrinsic<GCCIntSuffix,
0421        [llvm_v16i32_ty], [llvm_v16i32_ty],
0422        intr_properties>;
0423
0424 // tag : V6_vabs_hf
0425 class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix,
0426       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0427   : Hexagon_Intrinsic<GCCIntSuffix,
0428        [llvm_v32i32_ty], [llvm_v32i32_ty],
0429        intr_properties>;
0430
0431 // tag : V6_vabsdiffh
0432 class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,
0433       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0434   : Hexagon_Intrinsic<GCCIntSuffix,
0435        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
0436        intr_properties>;
0437
0438 // tag : V6_vabsdiffh
0439 class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
0440       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0441   : Hexagon_Intrinsic<GCCIntSuffix,
0442        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
0443        intr_properties>;
0444
0445 // tag : V6_vadd_sf_bf
0446 class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,
0447       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0448   : Hexagon_Intrinsic<GCCIntSuffix,
0449        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
0450        intr_properties>;
0451
0452 // tag : V6_vadd_sf_bf
0453 class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
0454       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0455   : Hexagon_Intrinsic<GCCIntSuffix,
0456        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
0457        intr_properties>;
0458
0459 // tag : V6_vaddb_dv
0460 class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix,
0461       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0462   : Hexagon_Intrinsic<GCCIntSuffix,
0463        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
0464        intr_properties>;
0465
0466 // tag : V6_vaddbnq
0467 class Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix,
0468       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0469   : Hexagon_Intrinsic<GCCIntSuffix,
0470        [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0471        intr_properties>;
0472
0473 // tag : V6_vaddbnq
0474 class Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix,
0475       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0476   : Hexagon_Intrinsic<GCCIntSuffix,
0477        [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0478        intr_properties>;
0479
0480 // tag : V6_vaddcarry
0481 class Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic<
0482       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0483   : Hexagon_NonGCC_Intrinsic<
0484        [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty],
0485        intr_properties>;
0486
0487 // tag : V6_vaddcarry
0488 class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B<
0489       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0490   : Hexagon_NonGCC_Intrinsic<
0491        [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty],
0492        intr_properties>;
0493
0494 // tag : V6_vaddcarryo
0495 class Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic<
0496       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0497   : Hexagon_NonGCC_Intrinsic<
0498        [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
0499        intr_properties>;
0500
0501 // tag : V6_vaddcarryo
0502 class Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B<
0503       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0504   : Hexagon_NonGCC_Intrinsic<
0505        [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
0506        intr_properties>;
0507
0508 // tag : V6_vaddcarrysat
0509 class Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<string GCCIntSuffix,
0510       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0511   : Hexagon_Intrinsic<GCCIntSuffix,
0512        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty],
0513        intr_properties>;
0514
0515 // tag : V6_vaddcarrysat
0516 class Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<string GCCIntSuffix,
0517       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0518   : Hexagon_Intrinsic<GCCIntSuffix,
0519        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty],
0520        intr_properties>;
0521
0522 // tag : V6_vaddhw_acc
0523 class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,
0524       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0525   : Hexagon_Intrinsic<GCCIntSuffix,
0526        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0527        intr_properties>;
0528
0529 // tag : V6_vaddhw_acc
0530 class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix,
0531       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0532   : Hexagon_Intrinsic<GCCIntSuffix,
0533        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0534        intr_properties>;
0535
0536 // tag : V6_valignb
0537 class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
0538       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0539   : Hexagon_Intrinsic<GCCIntSuffix,
0540        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
0541        intr_properties>;
0542
0543 // tag : V6_vandnqrt
0544 class Hexagon_v16i32_v64i1i32_Intrinsic<string GCCIntSuffix,
0545       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0546   : Hexagon_Intrinsic<GCCIntSuffix,
0547        [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty],
0548        intr_properties>;
0549
0550 // tag : V6_vandnqrt
0551 class Hexagon_v32i32_v128i1i32_Intrinsic<string GCCIntSuffix,
0552       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0553   : Hexagon_Intrinsic<GCCIntSuffix,
0554        [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty],
0555        intr_properties>;
0556
0557 // tag : V6_vandnqrt_acc
0558 class Hexagon_v16i32_v16i32v64i1i32_Intrinsic<string GCCIntSuffix,
0559       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0560   : Hexagon_Intrinsic<GCCIntSuffix,
0561        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty],
0562        intr_properties>;
0563
0564 // tag : V6_vandnqrt_acc
0565 class Hexagon_v32i32_v32i32v128i1i32_Intrinsic<string GCCIntSuffix,
0566       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0567   : Hexagon_Intrinsic<GCCIntSuffix,
0568        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty],
0569        intr_properties>;
0570
0571 // tag : V6_vandvnqv
0572 class Hexagon_v16i32_v64i1v16i32_Intrinsic<string GCCIntSuffix,
0573       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0574   : Hexagon_Intrinsic<GCCIntSuffix,
0575        [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty],
0576        intr_properties>;
0577
0578 // tag : V6_vandvnqv
0579 class Hexagon_v32i32_v128i1v32i32_Intrinsic<string GCCIntSuffix,
0580       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0581   : Hexagon_Intrinsic<GCCIntSuffix,
0582        [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty],
0583        intr_properties>;
0584
0585 // tag : V6_vandvrt
0586 class Hexagon_v64i1_v16i32i32_Intrinsic<string GCCIntSuffix,
0587       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0588   : Hexagon_Intrinsic<GCCIntSuffix,
0589        [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
0590        intr_properties>;
0591
0592 // tag : V6_vandvrt
0593 class Hexagon_v128i1_v32i32i32_Intrinsic<string GCCIntSuffix,
0594       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0595   : Hexagon_Intrinsic<GCCIntSuffix,
0596        [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
0597        intr_properties>;
0598
0599 // tag : V6_vandvrt_acc
0600 class Hexagon_v64i1_v64i1v16i32i32_Intrinsic<string GCCIntSuffix,
0601       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0602   : Hexagon_Intrinsic<GCCIntSuffix,
0603        [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_i32_ty],
0604        intr_properties>;
0605
0606 // tag : V6_vandvrt_acc
0607 class Hexagon_v128i1_v128i1v32i32i32_Intrinsic<string GCCIntSuffix,
0608       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0609   : Hexagon_Intrinsic<GCCIntSuffix,
0610        [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty],
0611        intr_properties>;
0612
0613 // tag : V6_vaslh
0614 class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix,
0615       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0616   : Hexagon_Intrinsic<GCCIntSuffix,
0617        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
0618        intr_properties>;
0619
0620 // tag : V6_vaslh
0621 class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix,
0622       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0623   : Hexagon_Intrinsic<GCCIntSuffix,
0624        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
0625        intr_properties>;
0626
0627 // tag : V6_vasrvuhubrndsat
0628 class Hexagon_v16i32_v32i32v16i32_Intrinsic<string GCCIntSuffix,
0629       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0630   : Hexagon_Intrinsic<GCCIntSuffix,
0631        [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
0632        intr_properties>;
0633
0634 // tag : V6_vasrvuhubrndsat
0635 class Hexagon_v32i32_v64i32v32i32_Intrinsic<string GCCIntSuffix,
0636       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0637   : Hexagon_Intrinsic<GCCIntSuffix,
0638        [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
0639        intr_properties>;
0640
0641 // tag : V6_vassignp
0642 class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix,
0643       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0644   : Hexagon_Intrinsic<GCCIntSuffix,
0645        [llvm_v64i32_ty], [llvm_v64i32_ty],
0646        intr_properties>;
0647
0648 // tag : V6_vcvt_hf_b
0649 class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix,
0650       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0651   : Hexagon_Intrinsic<GCCIntSuffix,
0652        [llvm_v32i32_ty], [llvm_v16i32_ty],
0653        intr_properties>;
0654
0655 // tag : V6_vcvt_hf_b
0656 class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix,
0657       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0658   : Hexagon_Intrinsic<GCCIntSuffix,
0659        [llvm_v64i32_ty], [llvm_v32i32_ty],
0660        intr_properties>;
0661
0662 // tag : V6_vd0
0663 class Hexagon_v16i32__Intrinsic<string GCCIntSuffix,
0664       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0665   : Hexagon_Intrinsic<GCCIntSuffix,
0666        [llvm_v16i32_ty], [],
0667        intr_properties>;
0668
0669 // tag : V6_vd0
0670 class Hexagon_v32i32__Intrinsic<string GCCIntSuffix,
0671       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0672   : Hexagon_Intrinsic<GCCIntSuffix,
0673        [llvm_v32i32_ty], [],
0674        intr_properties>;
0675
0676 // tag : V6_vdd0
0677 class Hexagon_v64i32__Intrinsic<string GCCIntSuffix,
0678       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0679   : Hexagon_Intrinsic<GCCIntSuffix,
0680        [llvm_v64i32_ty], [],
0681        intr_properties>;
0682
0683 // tag : V6_vdealvdd
0684 class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
0685       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0686   : Hexagon_Intrinsic<GCCIntSuffix,
0687        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
0688        intr_properties>;
0689
0690 // tag : V6_vdealvdd
0691 class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
0692       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0693   : Hexagon_Intrinsic<GCCIntSuffix,
0694        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0695        intr_properties>;
0696
0697 // tag : V6_vdmpy_sf_hf_acc
0698 class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix,
0699       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0700   : Hexagon_Intrinsic<GCCIntSuffix,
0701        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0702        intr_properties>;
0703
0704 // tag : V6_vdmpy_sf_hf_acc
0705 class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,
0706       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0707   : Hexagon_Intrinsic<GCCIntSuffix,
0708        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0709        intr_properties>;
0710
0711 // tag : V6_vdmpybus_dv
0712 class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix,
0713       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0714   : Hexagon_Intrinsic<GCCIntSuffix,
0715        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
0716        intr_properties>;
0717
0718 // tag : V6_vdmpyhisat
0719 class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix,
0720       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0721   : Hexagon_Intrinsic<GCCIntSuffix,
0722        [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
0723        intr_properties>;
0724
0725 // tag : V6_vdmpyhisat
0726 class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix,
0727       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0728   : Hexagon_Intrinsic<GCCIntSuffix,
0729        [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
0730        intr_properties>;
0731
0732 // tag : V6_vdmpyhisat_acc
0733 class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix,
0734       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0735   : Hexagon_Intrinsic<GCCIntSuffix,
0736        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0737        intr_properties>;
0738
0739 // tag : V6_vdmpyhisat_acc
0740 class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix,
0741       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0742   : Hexagon_Intrinsic<GCCIntSuffix,
0743        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
0744        intr_properties>;
0745
0746 // tag : V6_veqb
0747 class Hexagon_v64i1_v16i32v16i32_Intrinsic<string GCCIntSuffix,
0748       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0749   : Hexagon_Intrinsic<GCCIntSuffix,
0750        [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
0751        intr_properties>;
0752
0753 // tag : V6_veqb
0754 class Hexagon_v128i1_v32i32v32i32_Intrinsic<string GCCIntSuffix,
0755       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0756   : Hexagon_Intrinsic<GCCIntSuffix,
0757        [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
0758        intr_properties>;
0759
0760 // tag : V6_veqb_and
0761 class Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix,
0762       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0763   : Hexagon_Intrinsic<GCCIntSuffix,
0764        [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0765        intr_properties>;
0766
0767 // tag : V6_veqb_and
0768 class Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix,
0769       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0770   : Hexagon_Intrinsic<GCCIntSuffix,
0771        [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0772        intr_properties>;
0773
0774 // tag : V6_vgathermh
0775 class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix,
0776       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0777   : Hexagon_Intrinsic<GCCIntSuffix,
0778        [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty],
0779        intr_properties>;
0780
0781 // tag : V6_vgathermh
0782 class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix,
0783       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0784   : Hexagon_Intrinsic<GCCIntSuffix,
0785        [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],
0786        intr_properties>;
0787
0788 // tag : V6_vgathermhq
0789 class Hexagon__ptrv64i1i32i32v16i32_Intrinsic<string GCCIntSuffix,
0790       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0791   : Hexagon_Intrinsic<GCCIntSuffix,
0792        [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty],
0793        intr_properties>;
0794
0795 // tag : V6_vgathermhq
0796 class Hexagon__ptrv128i1i32i32v32i32_Intrinsic<string GCCIntSuffix,
0797       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0798   : Hexagon_Intrinsic<GCCIntSuffix,
0799        [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],
0800        intr_properties>;
0801
0802 // tag : V6_vgathermhw
0803 class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix,
0804       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0805   : Hexagon_Intrinsic<GCCIntSuffix,
0806        [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty],
0807        intr_properties>;
0808
0809 // tag : V6_vgathermhwq
0810 class Hexagon__ptrv64i1i32i32v32i32_Intrinsic<string GCCIntSuffix,
0811       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0812   : Hexagon_Intrinsic<GCCIntSuffix,
0813        [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],
0814        intr_properties>;
0815
0816 // tag : V6_vgathermhwq
0817 class Hexagon__ptrv128i1i32i32v64i32_Intrinsic<string GCCIntSuffix,
0818       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0819   : Hexagon_Intrinsic<GCCIntSuffix,
0820        [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty],
0821        intr_properties>;
0822
0823 // tag : V6_vlut4
0824 class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix,
0825       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0826   : Hexagon_Intrinsic<GCCIntSuffix,
0827        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
0828        intr_properties>;
0829
0830 // tag : V6_vlut4
0831 class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix,
0832       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0833   : Hexagon_Intrinsic<GCCIntSuffix,
0834        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
0835        intr_properties>;
0836
0837 // tag : V6_vlutvvb_oracc
0838 class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
0839       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0840   : Hexagon_Intrinsic<GCCIntSuffix,
0841        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
0842        intr_properties>;
0843
0844 // tag : V6_vlutvwh_oracc
0845 class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
0846       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0847   : Hexagon_Intrinsic<GCCIntSuffix,
0848        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
0849        intr_properties>;
0850
0851 // tag : V6_vlutvwh_oracc
0852 class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
0853       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0854   : Hexagon_Intrinsic<GCCIntSuffix,
0855        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0856        intr_properties>;
0857
0858 // tag : V6_vmpahhsat
0859 class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix,
0860       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0861   : Hexagon_Intrinsic<GCCIntSuffix,
0862        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
0863        intr_properties>;
0864
0865 // tag : V6_vmpahhsat
0866 class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix,
0867       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0868   : Hexagon_Intrinsic<GCCIntSuffix,
0869        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
0870        intr_properties>;
0871
0872 // tag : V6_vmpybus
0873 class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix,
0874       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0875   : Hexagon_Intrinsic<GCCIntSuffix,
0876        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
0877        intr_properties>;
0878
0879 // tag : V6_vmpybus
0880 class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix,
0881       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0882   : Hexagon_Intrinsic<GCCIntSuffix,
0883        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
0884        intr_properties>;
0885
0886 // tag : V6_vmpybus_acc
0887 class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix,
0888       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0889   : Hexagon_Intrinsic<GCCIntSuffix,
0890        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
0891        intr_properties>;
0892
0893 // tag : V6_vmpybus_acc
0894 class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix,
0895       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0896   : Hexagon_Intrinsic<GCCIntSuffix,
0897        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
0898        intr_properties>;
0899
0900 // tag : V6_vprefixqb
0901 class Hexagon_v16i32_v64i1_Intrinsic<string GCCIntSuffix,
0902       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0903   : Hexagon_Intrinsic<GCCIntSuffix,
0904        [llvm_v16i32_ty], [llvm_v64i1_ty],
0905        intr_properties>;
0906
0907 // tag : V6_vprefixqb
0908 class Hexagon_v32i32_v128i1_Intrinsic<string GCCIntSuffix,
0909       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0910   : Hexagon_Intrinsic<GCCIntSuffix,
0911        [llvm_v32i32_ty], [llvm_v128i1_ty],
0912        intr_properties>;
0913
0914 // tag : V6_vrmpybusi
0915 class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,
0916       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0917   : Hexagon_Intrinsic<GCCIntSuffix,
0918        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
0919        intr_properties>;
0920
0921 // tag : V6_vrmpybusi
0922 class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,
0923       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0924   : Hexagon_Intrinsic<GCCIntSuffix,
0925        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
0926        intr_properties>;
0927
0928 // tag : V6_vrmpybusi_acc
0929 class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,
0930       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0931   : Hexagon_Intrinsic<GCCIntSuffix,
0932        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
0933        intr_properties>;
0934
0935 // tag : V6_vrmpybusi_acc
0936 class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,
0937       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0938   : Hexagon_Intrinsic<GCCIntSuffix,
0939        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
0940        intr_properties>;
0941
0942 // tag : V6_vscattermh
0943 class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,
0944       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0945   : Hexagon_Intrinsic<GCCIntSuffix,
0946        [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0947        intr_properties>;
0948
0949 // tag : V6_vscattermh
0950 class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,
0951       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0952   : Hexagon_Intrinsic<GCCIntSuffix,
0953        [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0954        intr_properties>;
0955
0956 // tag : V6_vscattermhq
0957 class Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,
0958       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0959   : Hexagon_Intrinsic<GCCIntSuffix,
0960        [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
0961        intr_properties>;
0962
0963 // tag : V6_vscattermhq
0964 class Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,
0965       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0966   : Hexagon_Intrinsic<GCCIntSuffix,
0967        [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
0968        intr_properties>;
0969
0970 // tag : V6_vscattermhw
0971 class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix,
0972       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0973   : Hexagon_Intrinsic<GCCIntSuffix,
0974        [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty],
0975        intr_properties>;
0976
0977 // tag : V6_vscattermhw
0978 class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix,
0979       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0980   : Hexagon_Intrinsic<GCCIntSuffix,
0981        [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty],
0982        intr_properties>;
0983
0984 // tag : V6_vscattermhwq
0985 class Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix,
0986       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0987   : Hexagon_Intrinsic<GCCIntSuffix,
0988        [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty],
0989        intr_properties>;
0990
0991 // tag : V6_vscattermhwq
0992 class Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix,
0993       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
0994   : Hexagon_Intrinsic<GCCIntSuffix,
0995        [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty],
0996        intr_properties>;
0997
0998 // tag : V6_vswap
0999 class Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix,
1000       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1001   : Hexagon_Intrinsic<GCCIntSuffix,
1002        [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
1003        intr_properties>;
1004
1005 // tag : V6_vswap
1006 class Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix,
1007       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1008   : Hexagon_Intrinsic<GCCIntSuffix,
1009        [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
1010        intr_properties>;
1011
1012 // tag : V6_vunpackob
1013 class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix,
1014       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1015   : Hexagon_Intrinsic<GCCIntSuffix,
1016        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
1017        intr_properties>;
1018
1019 // tag : V6_vunpackob
1020 class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix,
1021       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1022   : Hexagon_Intrinsic<GCCIntSuffix,
1023        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
1024        intr_properties>;
1025
1026 // tag : Y2_dccleana
1027 class Hexagon__ptr_Intrinsic<string GCCIntSuffix,
1028       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1029   : Hexagon_Intrinsic<GCCIntSuffix,
1030        [], [llvm_ptr_ty],
1031        intr_properties>;
1032
1033 // tag : Y4_l2fetch
1034 class Hexagon__ptri32_Intrinsic<string GCCIntSuffix,
1035       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1036   : Hexagon_Intrinsic<GCCIntSuffix,
1037        [], [llvm_ptr_ty,llvm_i32_ty],
1038        intr_properties>;
1039
1040 // tag : Y5_l2fetch
1041 class Hexagon__ptri64_Intrinsic<string GCCIntSuffix,
1042       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1043   : Hexagon_Intrinsic<GCCIntSuffix,
1044        [], [llvm_ptr_ty,llvm_i64_ty],
1045        intr_properties>;
1046
1047 // tag : Y6_dmlink
1048 class Hexagon__ptrptr_Intrinsic<string GCCIntSuffix,
1049       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1050   : Hexagon_Intrinsic<GCCIntSuffix,
1051        [], [llvm_ptr_ty,llvm_ptr_ty],
1052        intr_properties>;
1053
1054 // tag : Y6_dmpause
1055 class Hexagon_i32__Intrinsic<string GCCIntSuffix,
1056       list<IntrinsicProperty> intr_properties = [IntrNoMem]>
1057   : Hexagon_Intrinsic<GCCIntSuffix,
1058        [llvm_i32_ty], [],
1059        intr_properties>;
1060
1061 // V5 Scalar Instructions.
1062
1063 def int_hexagon_A2_abs :
1064 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">;
1065
1066 def int_hexagon_A2_absp :
1067 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;
1068
1069 def int_hexagon_A2_abssat :
1070 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;
1071
1072 def int_hexagon_A2_add :
1073 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;
1074
1075 def int_hexagon_A2_addh_h16_hh :
1076 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
1077
1078 def int_hexagon_A2_addh_h16_hl :
1079 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
1080
1081 def int_hexagon_A2_addh_h16_lh :
1082 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
1083
1084 def int_hexagon_A2_addh_h16_ll :
1085 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
1086
1087 def int_hexagon_A2_addh_h16_sat_hh :
1088 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
1089
1090 def int_hexagon_A2_addh_h16_sat_hl :
1091 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
1092
1093 def int_hexagon_A2_addh_h16_sat_lh :
1094 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
1095
1096 def int_hexagon_A2_addh_h16_sat_ll :
1097 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
1098
1099 def int_hexagon_A2_addh_l16_hl :
1100 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
1101
1102 def int_hexagon_A2_addh_l16_ll :
1103 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
1104
1105 def int_hexagon_A2_addh_l16_sat_hl :
1106 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
1107
1108 def int_hexagon_A2_addh_l16_sat_ll :
1109 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
1110
1111 def int_hexagon_A2_addi :
1112 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1113
1114 def int_hexagon_A2_addp :
1115 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;
1116
1117 def int_hexagon_A2_addpsat :
1118 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;
1119
1120 def int_hexagon_A2_addsat :
1121 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;
1122
1123 def int_hexagon_A2_addsp :
1124 Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;
1125
1126 def int_hexagon_A2_and :
1127 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">;
1128
1129 def int_hexagon_A2_andir :
1130 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1131
1132 def int_hexagon_A2_andp :
1133 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;
1134
1135 def int_hexagon_A2_aslh :
1136 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;
1137
1138 def int_hexagon_A2_asrh :
1139 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;
1140
1141 def int_hexagon_A2_combine_hh :
1142 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;
1143
1144 def int_hexagon_A2_combine_hl :
1145 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;
1146
1147 def int_hexagon_A2_combine_lh :
1148 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">;
1149
1150 def int_hexagon_A2_combine_ll :
1151 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">;
1152
1153 def int_hexagon_A2_combineii :
1154 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
1155
1156 def int_hexagon_A2_combinew :
1157 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;
1158
1159 def int_hexagon_A2_max :
1160 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;
1161
1162 def int_hexagon_A2_maxp :
1163 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;
1164
1165 def int_hexagon_A2_maxu :
1166 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;
1167
1168 def int_hexagon_A2_maxup :
1169 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;
1170
1171 def int_hexagon_A2_min :
1172 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;
1173
1174 def int_hexagon_A2_minp :
1175 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;
1176
1177 def int_hexagon_A2_minu :
1178 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;
1179
1180 def int_hexagon_A2_minup :
1181 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">;
1182
1183 def int_hexagon_A2_neg :
1184 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;
1185
1186 def int_hexagon_A2_negp :
1187 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;
1188
1189 def int_hexagon_A2_negsat :
1190 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;
1191
1192 def int_hexagon_A2_not :
1193 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;
1194
1195 def int_hexagon_A2_notp :
1196 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;
1197
1198 def int_hexagon_A2_or :
1199 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">;
1200
1201 def int_hexagon_A2_orir :
1202 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1203
1204 def int_hexagon_A2_orp :
1205 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;
1206
1207 def int_hexagon_A2_roundsat :
1208 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;
1209
1210 def int_hexagon_A2_sat :
1211 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;
1212
1213 def int_hexagon_A2_satb :
1214 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;
1215
1216 def int_hexagon_A2_sath :
1217 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;
1218
1219 def int_hexagon_A2_satub :
1220 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;
1221
1222 def int_hexagon_A2_satuh :
1223 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">;
1224
1225 def int_hexagon_A2_sub :
1226 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;
1227
1228 def int_hexagon_A2_subh_h16_hh :
1229 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
1230
1231 def int_hexagon_A2_subh_h16_hl :
1232 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
1233
1234 def int_hexagon_A2_subh_h16_lh :
1235 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
1236
1237 def int_hexagon_A2_subh_h16_ll :
1238 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
1239
1240 def int_hexagon_A2_subh_h16_sat_hh :
1241 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
1242
1243 def int_hexagon_A2_subh_h16_sat_hl :
1244 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
1245
1246 def int_hexagon_A2_subh_h16_sat_lh :
1247 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
1248
1249 def int_hexagon_A2_subh_h16_sat_ll :
1250 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
1251
1252 def int_hexagon_A2_subh_l16_hl :
1253 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
1254
1255 def int_hexagon_A2_subh_l16_ll :
1256 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
1257
1258 def int_hexagon_A2_subh_l16_sat_hl :
1259 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
1260
1261 def int_hexagon_A2_subh_l16_sat_ll :
1262 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
1263
1264 def int_hexagon_A2_subp :
1265 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">;
1266
1267 def int_hexagon_A2_subri :
1268 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1269
1270 def int_hexagon_A2_subsat :
1271 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;
1272
1273 def int_hexagon_A2_svaddh :
1274 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;
1275
1276 def int_hexagon_A2_svaddhs :
1277 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;
1278
1279 def int_hexagon_A2_svadduhs :
1280 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">;
1281
1282 def int_hexagon_A2_svavgh :
1283 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;
1284
1285 def int_hexagon_A2_svavghs :
1286 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;
1287
1288 def int_hexagon_A2_svnavgh :
1289 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;
1290
1291 def int_hexagon_A2_svsubh :
1292 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;
1293
1294 def int_hexagon_A2_svsubhs :
1295 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;
1296
1297 def int_hexagon_A2_svsubuhs :
1298 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">;
1299
1300 def int_hexagon_A2_swiz :
1301 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;
1302
1303 def int_hexagon_A2_sxtb :
1304 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;
1305
1306 def int_hexagon_A2_sxth :
1307 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;
1308
1309 def int_hexagon_A2_sxtw :
1310 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;
1311
1312 def int_hexagon_A2_tfr :
1313 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;
1314
1315 def int_hexagon_A2_tfrih :
1316 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1317
1318 def int_hexagon_A2_tfril :
1319 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1320
1321 def int_hexagon_A2_tfrp :
1322 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">;
1323
1324 def int_hexagon_A2_tfrpi :
1325 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1326
1327 def int_hexagon_A2_tfrsi :
1328 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1329
1330 def int_hexagon_A2_vabsh :
1331 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;
1332
1333 def int_hexagon_A2_vabshsat :
1334 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;
1335
1336 def int_hexagon_A2_vabsw :
1337 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;
1338
1339 def int_hexagon_A2_vabswsat :
1340 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;
1341
1342 def int_hexagon_A2_vaddb_map :
1343 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;
1344
1345 def int_hexagon_A2_vaddh :
1346 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;
1347
1348 def int_hexagon_A2_vaddhs :
1349 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">;
1350
1351 def int_hexagon_A2_vaddub :
1352 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">;
1353
1354 def int_hexagon_A2_vaddubs :
1355 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;
1356
1357 def int_hexagon_A2_vadduhs :
1358 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;
1359
1360 def int_hexagon_A2_vaddw :
1361 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;
1362
1363 def int_hexagon_A2_vaddws :
1364 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;
1365
1366 def int_hexagon_A2_vavgh :
1367 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;
1368
1369 def int_hexagon_A2_vavghcr :
1370 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;
1371
1372 def int_hexagon_A2_vavghr :
1373 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;
1374
1375 def int_hexagon_A2_vavgub :
1376 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;
1377
1378 def int_hexagon_A2_vavgubr :
1379 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;
1380
1381 def int_hexagon_A2_vavguh :
1382 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;
1383
1384 def int_hexagon_A2_vavguhr :
1385 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">;
1386
1387 def int_hexagon_A2_vavguw :
1388 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;
1389
1390 def int_hexagon_A2_vavguwr :
1391 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;
1392
1393 def int_hexagon_A2_vavgw :
1394 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;
1395
1396 def int_hexagon_A2_vavgwcr :
1397 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;
1398
1399 def int_hexagon_A2_vavgwr :
1400 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;
1401
1402 def int_hexagon_A2_vcmpbeq :
1403 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;
1404
1405 def int_hexagon_A2_vcmpbgtu :
1406 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
1407
1408 def int_hexagon_A2_vcmpheq :
1409 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;
1410
1411 def int_hexagon_A2_vcmphgt :
1412 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;
1413
1414 def int_hexagon_A2_vcmphgtu :
1415 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;
1416
1417 def int_hexagon_A2_vcmpweq :
1418 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;
1419
1420 def int_hexagon_A2_vcmpwgt :
1421 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">;
1422
1423 def int_hexagon_A2_vcmpwgtu :
1424 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
1425
1426 def int_hexagon_A2_vconj :
1427 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;
1428
1429 def int_hexagon_A2_vmaxb :
1430 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;
1431
1432 def int_hexagon_A2_vmaxh :
1433 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;
1434
1435 def int_hexagon_A2_vmaxub :
1436 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;
1437
1438 def int_hexagon_A2_vmaxuh :
1439 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;
1440
1441 def int_hexagon_A2_vmaxuw :
1442 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;
1443
1444 def int_hexagon_A2_vmaxw :
1445 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;
1446
1447 def int_hexagon_A2_vminb :
1448 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">;
1449
1450 def int_hexagon_A2_vminh :
1451 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">;
1452
1453 def int_hexagon_A2_vminub :
1454 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;
1455
1456 def int_hexagon_A2_vminuh :
1457 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;
1458
1459 def int_hexagon_A2_vminuw :
1460 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">;
1461
1462 def int_hexagon_A2_vminw :
1463 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">;
1464
1465 def int_hexagon_A2_vnavgh :
1466 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;
1467
1468 def int_hexagon_A2_vnavghcr :
1469 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;
1470
1471 def int_hexagon_A2_vnavghr :
1472 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;
1473
1474 def int_hexagon_A2_vnavgw :
1475 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;
1476
1477 def int_hexagon_A2_vnavgwcr :
1478 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;
1479
1480 def int_hexagon_A2_vnavgwr :
1481 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;
1482
1483 def int_hexagon_A2_vraddub :
1484 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">;
1485
1486 def int_hexagon_A2_vraddub_acc :
1487 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;
1488
1489 def int_hexagon_A2_vrsadub :
1490 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;
1491
1492 def int_hexagon_A2_vrsadub_acc :
1493 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
1494
1495 def int_hexagon_A2_vsubb_map :
1496 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;
1497
1498 def int_hexagon_A2_vsubh :
1499 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">;
1500
1501 def int_hexagon_A2_vsubhs :
1502 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">;
1503
1504 def int_hexagon_A2_vsubub :
1505 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;
1506
1507 def int_hexagon_A2_vsububs :
1508 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;
1509
1510 def int_hexagon_A2_vsubuhs :
1511 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;
1512
1513 def int_hexagon_A2_vsubw :
1514 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">;
1515
1516 def int_hexagon_A2_vsubws :
1517 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;
1518
1519 def int_hexagon_A2_xor :
1520 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;
1521
1522 def int_hexagon_A2_xorp :
1523 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;
1524
1525 def int_hexagon_A2_zxtb :
1526 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;
1527
1528 def int_hexagon_A2_zxth :
1529 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;
1530
1531 def int_hexagon_A4_andn :
1532 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;
1533
1534 def int_hexagon_A4_andnp :
1535 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;
1536
1537 def int_hexagon_A4_bitsplit :
1538 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;
1539
1540 def int_hexagon_A4_bitspliti :
1541 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1542
1543 def int_hexagon_A4_boundscheck :
1544 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;
1545
1546 def int_hexagon_A4_cmpbeq :
1547 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;
1548
1549 def int_hexagon_A4_cmpbeqi :
1550 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1551
1552 def int_hexagon_A4_cmpbgt :
1553 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;
1554
1555 def int_hexagon_A4_cmpbgti :
1556 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1557
1558 def int_hexagon_A4_cmpbgtu :
1559 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;
1560
1561 def int_hexagon_A4_cmpbgtui :
1562 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1563
1564 def int_hexagon_A4_cmpheq :
1565 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;
1566
1567 def int_hexagon_A4_cmpheqi :
1568 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1569
1570 def int_hexagon_A4_cmphgt :
1571 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;
1572
1573 def int_hexagon_A4_cmphgti :
1574 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1575
1576 def int_hexagon_A4_cmphgtu :
1577 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;
1578
1579 def int_hexagon_A4_cmphgtui :
1580 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1581
1582 def int_hexagon_A4_combineir :
1583 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1584
1585 def int_hexagon_A4_combineri :
1586 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1587
1588 def int_hexagon_A4_cround_ri :
1589 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1590
1591 def int_hexagon_A4_cround_rr :
1592 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;
1593
1594 def int_hexagon_A4_modwrapu :
1595 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;
1596
1597 def int_hexagon_A4_orn :
1598 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;
1599
1600 def int_hexagon_A4_ornp :
1601 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;
1602
1603 def int_hexagon_A4_rcmpeq :
1604 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;
1605
1606 def int_hexagon_A4_rcmpeqi :
1607 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1608
1609 def int_hexagon_A4_rcmpneq :
1610 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;
1611
1612 def int_hexagon_A4_rcmpneqi :
1613 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1614
1615 def int_hexagon_A4_round_ri :
1616 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1617
1618 def int_hexagon_A4_round_ri_sat :
1619 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1620
1621 def int_hexagon_A4_round_rr :
1622 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;
1623
1624 def int_hexagon_A4_round_rr_sat :
1625 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;
1626
1627 def int_hexagon_A4_tlbmatch :
1628 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">;
1629
1630 def int_hexagon_A4_vcmpbeq_any :
1631 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
1632
1633 def int_hexagon_A4_vcmpbeqi :
1634 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1635
1636 def int_hexagon_A4_vcmpbgt :
1637 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;
1638
1639 def int_hexagon_A4_vcmpbgti :
1640 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1641
1642 def int_hexagon_A4_vcmpbgtui :
1643 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1644
1645 def int_hexagon_A4_vcmpheqi :
1646 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1647
1648 def int_hexagon_A4_vcmphgti :
1649 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1650
1651 def int_hexagon_A4_vcmphgtui :
1652 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1653
1654 def int_hexagon_A4_vcmpweqi :
1655 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1656
1657 def int_hexagon_A4_vcmpwgti :
1658 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1659
1660 def int_hexagon_A4_vcmpwgtui :
1661 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1662
1663 def int_hexagon_A4_vrmaxh :
1664 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;
1665
1666 def int_hexagon_A4_vrmaxuh :
1667 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;
1668
1669 def int_hexagon_A4_vrmaxuw :
1670 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;
1671
1672 def int_hexagon_A4_vrmaxw :
1673 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;
1674
1675 def int_hexagon_A4_vrminh :
1676 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;
1677
1678 def int_hexagon_A4_vrminuh :
1679 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;
1680
1681 def int_hexagon_A4_vrminuw :
1682 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;
1683
1684 def int_hexagon_A4_vrminw :
1685 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;
1686
1687 def int_hexagon_A5_vaddhubs :
1688 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;
1689
1690 def int_hexagon_C2_all8 :
1691 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;
1692
1693 def int_hexagon_C2_and :
1694 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;
1695
1696 def int_hexagon_C2_andn :
1697 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;
1698
1699 def int_hexagon_C2_any8 :
1700 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;
1701
1702 def int_hexagon_C2_bitsclr :
1703 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;
1704
1705 def int_hexagon_C2_bitsclri :
1706 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1707
1708 def int_hexagon_C2_bitsset :
1709 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;
1710
1711 def int_hexagon_C2_cmpeq :
1712 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">;
1713
1714 def int_hexagon_C2_cmpeqi :
1715 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1716
1717 def int_hexagon_C2_cmpeqp :
1718 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;
1719
1720 def int_hexagon_C2_cmpgei :
1721 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1722
1723 def int_hexagon_C2_cmpgeui :
1724 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1725
1726 def int_hexagon_C2_cmpgt :
1727 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;
1728
1729 def int_hexagon_C2_cmpgti :
1730 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1731
1732 def int_hexagon_C2_cmpgtp :
1733 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;
1734
1735 def int_hexagon_C2_cmpgtu :
1736 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;
1737
1738 def int_hexagon_C2_cmpgtui :
1739 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1740
1741 def int_hexagon_C2_cmpgtup :
1742 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;
1743
1744 def int_hexagon_C2_cmplt :
1745 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;
1746
1747 def int_hexagon_C2_cmpltu :
1748 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;
1749
1750 def int_hexagon_C2_mask :
1751 Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;
1752
1753 def int_hexagon_C2_mux :
1754 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;
1755
1756 def int_hexagon_C2_muxii :
1757 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
1758
1759 def int_hexagon_C2_muxir :
1760 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
1761
1762 def int_hexagon_C2_muxri :
1763 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1764
1765 def int_hexagon_C2_not :
1766 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;
1767
1768 def int_hexagon_C2_or :
1769 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;
1770
1771 def int_hexagon_C2_orn :
1772 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;
1773
1774 def int_hexagon_C2_pxfer_map :
1775 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;
1776
1777 def int_hexagon_C2_tfrpr :
1778 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;
1779
1780 def int_hexagon_C2_tfrrp :
1781 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">;
1782
1783 def int_hexagon_C2_vitpack :
1784 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">;
1785
1786 def int_hexagon_C2_vmux :
1787 Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;
1788
1789 def int_hexagon_C2_xor :
1790 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;
1791
1792 def int_hexagon_C4_and_and :
1793 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">;
1794
1795 def int_hexagon_C4_and_andn :
1796 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">;
1797
1798 def int_hexagon_C4_and_or :
1799 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;
1800
1801 def int_hexagon_C4_and_orn :
1802 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;
1803
1804 def int_hexagon_C4_cmplte :
1805 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;
1806
1807 def int_hexagon_C4_cmpltei :
1808 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1809
1810 def int_hexagon_C4_cmplteu :
1811 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;
1812
1813 def int_hexagon_C4_cmplteui :
1814 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1815
1816 def int_hexagon_C4_cmpneq :
1817 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">;
1818
1819 def int_hexagon_C4_cmpneqi :
1820 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1821
1822 def int_hexagon_C4_fastcorner9 :
1823 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;
1824
1825 def int_hexagon_C4_fastcorner9_not :
1826 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
1827
1828 def int_hexagon_C4_nbitsclr :
1829 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">;
1830
1831 def int_hexagon_C4_nbitsclri :
1832 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1833
1834 def int_hexagon_C4_nbitsset :
1835 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;
1836
1837 def int_hexagon_C4_or_and :
1838 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;
1839
1840 def int_hexagon_C4_or_andn :
1841 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;
1842
1843 def int_hexagon_C4_or_or :
1844 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;
1845
1846 def int_hexagon_C4_or_orn :
1847 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;
1848
1849 def int_hexagon_F2_conv_d2df :
1850 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;
1851
1852 def int_hexagon_F2_conv_d2sf :
1853 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;
1854
1855 def int_hexagon_F2_conv_df2d :
1856 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;
1857
1858 def int_hexagon_F2_conv_df2d_chop :
1859 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
1860
1861 def int_hexagon_F2_conv_df2sf :
1862 Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;
1863
1864 def int_hexagon_F2_conv_df2ud :
1865 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;
1866
1867 def int_hexagon_F2_conv_df2ud_chop :
1868 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
1869
1870 def int_hexagon_F2_conv_df2uw :
1871 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;
1872
1873 def int_hexagon_F2_conv_df2uw_chop :
1874 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
1875
1876 def int_hexagon_F2_conv_df2w :
1877 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;
1878
1879 def int_hexagon_F2_conv_df2w_chop :
1880 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
1881
1882 def int_hexagon_F2_conv_sf2d :
1883 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;
1884
1885 def int_hexagon_F2_conv_sf2d_chop :
1886 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
1887
1888 def int_hexagon_F2_conv_sf2df :
1889 Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">;
1890
1891 def int_hexagon_F2_conv_sf2ud :
1892 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
1893
1894 def int_hexagon_F2_conv_sf2ud_chop :
1895 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
1896
1897 def int_hexagon_F2_conv_sf2uw :
1898 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
1899
1900 def int_hexagon_F2_conv_sf2uw_chop :
1901 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
1902
1903 def int_hexagon_F2_conv_sf2w :
1904 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;
1905
1906 def int_hexagon_F2_conv_sf2w_chop :
1907 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
1908
1909 def int_hexagon_F2_conv_ud2df :
1910 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;
1911
1912 def int_hexagon_F2_conv_ud2sf :
1913 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
1914
1915 def int_hexagon_F2_conv_uw2df :
1916 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;
1917
1918 def int_hexagon_F2_conv_uw2sf :
1919 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
1920
1921 def int_hexagon_F2_conv_w2df :
1922 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;
1923
1924 def int_hexagon_F2_conv_w2sf :
1925 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;
1926
1927 def int_hexagon_F2_dfclass :
1928 Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>;
1929
1930 def int_hexagon_F2_dfcmpeq :
1931 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>;
1932
1933 def int_hexagon_F2_dfcmpge :
1934 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>;
1935
1936 def int_hexagon_F2_dfcmpgt :
1937 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>;
1938
1939 def int_hexagon_F2_dfcmpuo :
1940 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>;
1941
1942 def int_hexagon_F2_dfimm_n :
1943 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>;
1944
1945 def int_hexagon_F2_dfimm_p :
1946 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>;
1947
1948 def int_hexagon_F2_sfadd :
1949 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>;
1950
1951 def int_hexagon_F2_sfclass :
1952 Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>;
1953
1954 def int_hexagon_F2_sfcmpeq :
1955 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>;
1956
1957 def int_hexagon_F2_sfcmpge :
1958 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>;
1959
1960 def int_hexagon_F2_sfcmpgt :
1961 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>;
1962
1963 def int_hexagon_F2_sfcmpuo :
1964 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>;
1965
1966 def int_hexagon_F2_sffixupd :
1967 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>;
1968
1969 def int_hexagon_F2_sffixupn :
1970 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>;
1971
1972 def int_hexagon_F2_sffixupr :
1973 Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>;
1974
1975 def int_hexagon_F2_sffma :
1976 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>;
1977
1978 def int_hexagon_F2_sffma_lib :
1979 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>;
1980
1981 def int_hexagon_F2_sffma_sc :
1982 Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>;
1983
1984 def int_hexagon_F2_sffms :
1985 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>;
1986
1987 def int_hexagon_F2_sffms_lib :
1988 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>;
1989
1990 def int_hexagon_F2_sfimm_n :
1991 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>;
1992
1993 def int_hexagon_F2_sfimm_p :
1994 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>;
1995
1996 def int_hexagon_F2_sfmax :
1997 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>;
1998
1999 def int_hexagon_F2_sfmin :
2000 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>;
2001
2002 def int_hexagon_F2_sfmpy :
2003 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>;
2004
2005 def int_hexagon_F2_sfsub :
2006 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>;
2007
2008 def int_hexagon_M2_acci :
2009 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;
2010
2011 def int_hexagon_M2_accii :
2012 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2013
2014 def int_hexagon_M2_cmaci_s0 :
2015 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;
2016
2017 def int_hexagon_M2_cmacr_s0 :
2018 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;
2019
2020 def int_hexagon_M2_cmacs_s0 :
2021 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;
2022
2023 def int_hexagon_M2_cmacs_s1 :
2024 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;
2025
2026 def int_hexagon_M2_cmacsc_s0 :
2027 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
2028
2029 def int_hexagon_M2_cmacsc_s1 :
2030 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
2031
2032 def int_hexagon_M2_cmpyi_s0 :
2033 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
2034
2035 def int_hexagon_M2_cmpyr_s0 :
2036 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
2037
2038 def int_hexagon_M2_cmpyrs_s0 :
2039 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
2040
2041 def int_hexagon_M2_cmpyrs_s1 :
2042 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
2043
2044 def int_hexagon_M2_cmpyrsc_s0 :
2045 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
2046
2047 def int_hexagon_M2_cmpyrsc_s1 :
2048 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
2049
2050 def int_hexagon_M2_cmpys_s0 :
2051 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">;
2052
2053 def int_hexagon_M2_cmpys_s1 :
2054 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">;
2055
2056 def int_hexagon_M2_cmpysc_s0 :
2057 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
2058
2059 def int_hexagon_M2_cmpysc_s1 :
2060 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
2061
2062 def int_hexagon_M2_cnacs_s0 :
2063 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;
2064
2065 def int_hexagon_M2_cnacs_s1 :
2066 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;
2067
2068 def int_hexagon_M2_cnacsc_s0 :
2069 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
2070
2071 def int_hexagon_M2_cnacsc_s1 :
2072 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
2073
2074 def int_hexagon_M2_dpmpyss_acc_s0 :
2075 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
2076
2077 def int_hexagon_M2_dpmpyss_nac_s0 :
2078 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
2079
2080 def int_hexagon_M2_dpmpyss_rnd_s0 :
2081 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
2082
2083 def int_hexagon_M2_dpmpyss_s0 :
2084 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
2085
2086 def int_hexagon_M2_dpmpyuu_acc_s0 :
2087 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
2088
2089 def int_hexagon_M2_dpmpyuu_nac_s0 :
2090 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
2091
2092 def int_hexagon_M2_dpmpyuu_s0 :
2093 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
2094
2095 def int_hexagon_M2_hmmpyh_rs1 :
2096 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
2097
2098 def int_hexagon_M2_hmmpyh_s1 :
2099 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
2100
2101 def int_hexagon_M2_hmmpyl_rs1 :
2102 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
2103
2104 def int_hexagon_M2_hmmpyl_s1 :
2105 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
2106
2107 def int_hexagon_M2_maci :
2108 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;
2109
2110 def int_hexagon_M2_macsin :
2111 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2112
2113 def int_hexagon_M2_macsip :
2114 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2115
2116 def int_hexagon_M2_mmachs_rs0 :
2117 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
2118
2119 def int_hexagon_M2_mmachs_rs1 :
2120 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
2121
2122 def int_hexagon_M2_mmachs_s0 :
2123 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;
2124
2125 def int_hexagon_M2_mmachs_s1 :
2126 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;
2127
2128 def int_hexagon_M2_mmacls_rs0 :
2129 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
2130
2131 def int_hexagon_M2_mmacls_rs1 :
2132 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
2133
2134 def int_hexagon_M2_mmacls_s0 :
2135 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;
2136
2137 def int_hexagon_M2_mmacls_s1 :
2138 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;
2139
2140 def int_hexagon_M2_mmacuhs_rs0 :
2141 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
2142
2143 def int_hexagon_M2_mmacuhs_rs1 :
2144 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
2145
2146 def int_hexagon_M2_mmacuhs_s0 :
2147 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
2148
2149 def int_hexagon_M2_mmacuhs_s1 :
2150 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
2151
2152 def int_hexagon_M2_mmaculs_rs0 :
2153 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
2154
2155 def int_hexagon_M2_mmaculs_rs1 :
2156 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
2157
2158 def int_hexagon_M2_mmaculs_s0 :
2159 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
2160
2161 def int_hexagon_M2_mmaculs_s1 :
2162 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
2163
2164 def int_hexagon_M2_mmpyh_rs0 :
2165 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
2166
2167 def int_hexagon_M2_mmpyh_rs1 :
2168 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
2169
2170 def int_hexagon_M2_mmpyh_s0 :
2171 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
2172
2173 def int_hexagon_M2_mmpyh_s1 :
2174 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
2175
2176 def int_hexagon_M2_mmpyl_rs0 :
2177 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
2178
2179 def int_hexagon_M2_mmpyl_rs1 :
2180 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
2181
2182 def int_hexagon_M2_mmpyl_s0 :
2183 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
2184
2185 def int_hexagon_M2_mmpyl_s1 :
2186 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
2187
2188 def int_hexagon_M2_mmpyuh_rs0 :
2189 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
2190
2191 def int_hexagon_M2_mmpyuh_rs1 :
2192 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
2193
2194 def int_hexagon_M2_mmpyuh_s0 :
2195 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
2196
2197 def int_hexagon_M2_mmpyuh_s1 :
2198 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
2199
2200 def int_hexagon_M2_mmpyul_rs0 :
2201 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
2202
2203 def int_hexagon_M2_mmpyul_rs1 :
2204 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
2205
2206 def int_hexagon_M2_mmpyul_s0 :
2207 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
2208
2209 def int_hexagon_M2_mmpyul_s1 :
2210 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
2211
2212 def int_hexagon_M2_mpy_acc_hh_s0 :
2213 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
2214
2215 def int_hexagon_M2_mpy_acc_hh_s1 :
2216 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
2217
2218 def int_hexagon_M2_mpy_acc_hl_s0 :
2219 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
2220
2221 def int_hexagon_M2_mpy_acc_hl_s1 :
2222 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
2223
2224 def int_hexagon_M2_mpy_acc_lh_s0 :
2225 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
2226
2227 def int_hexagon_M2_mpy_acc_lh_s1 :
2228 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
2229
2230 def int_hexagon_M2_mpy_acc_ll_s0 :
2231 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
2232
2233 def int_hexagon_M2_mpy_acc_ll_s1 :
2234 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
2235
2236 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
2237 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
2238
2239 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
2240 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
2241
2242 def int_hexagon_M2_mpy_acc_sat_hl_s0 :
2243 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
2244
2245 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
2246 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
2247
2248 def int_hexagon_M2_mpy_acc_sat_lh_s0 :
2249 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
2250
2251 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
2252 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
2253
2254 def int_hexagon_M2_mpy_acc_sat_ll_s0 :
2255 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
2256
2257 def int_hexagon_M2_mpy_acc_sat_ll_s1 :
2258 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
2259
2260 def int_hexagon_M2_mpy_hh_s0 :
2261 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
2262
2263 def int_hexagon_M2_mpy_hh_s1 :
2264 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
2265
2266 def int_hexagon_M2_mpy_hl_s0 :
2267 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
2268
2269 def int_hexagon_M2_mpy_hl_s1 :
2270 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
2271
2272 def int_hexagon_M2_mpy_lh_s0 :
2273 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
2274
2275 def int_hexagon_M2_mpy_lh_s1 :
2276 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
2277
2278 def int_hexagon_M2_mpy_ll_s0 :
2279 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
2280
2281 def int_hexagon_M2_mpy_ll_s1 :
2282 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
2283
2284 def int_hexagon_M2_mpy_nac_hh_s0 :
2285 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
2286
2287 def int_hexagon_M2_mpy_nac_hh_s1 :
2288 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
2289
2290 def int_hexagon_M2_mpy_nac_hl_s0 :
2291 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
2292
2293 def int_hexagon_M2_mpy_nac_hl_s1 :
2294 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
2295
2296 def int_hexagon_M2_mpy_nac_lh_s0 :
2297 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
2298
2299 def int_hexagon_M2_mpy_nac_lh_s1 :
2300 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
2301
2302 def int_hexagon_M2_mpy_nac_ll_s0 :
2303 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
2304
2305 def int_hexagon_M2_mpy_nac_ll_s1 :
2306 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
2307
2308 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
2309 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
2310
2311 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
2312 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
2313
2314 def int_hexagon_M2_mpy_nac_sat_hl_s0 :
2315 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
2316
2317 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
2318 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
2319
2320 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
2321 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
2322
2323 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
2324 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
2325
2326 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
2327 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
2328
2329 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
2330 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
2331
2332 def int_hexagon_M2_mpy_rnd_hh_s0 :
2333 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
2334
2335 def int_hexagon_M2_mpy_rnd_hh_s1 :
2336 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
2337
2338 def int_hexagon_M2_mpy_rnd_hl_s0 :
2339 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
2340
2341 def int_hexagon_M2_mpy_rnd_hl_s1 :
2342 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
2343
2344 def int_hexagon_M2_mpy_rnd_lh_s0 :
2345 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
2346
2347 def int_hexagon_M2_mpy_rnd_lh_s1 :
2348 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
2349
2350 def int_hexagon_M2_mpy_rnd_ll_s0 :
2351 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
2352
2353 def int_hexagon_M2_mpy_rnd_ll_s1 :
2354 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
2355
2356 def int_hexagon_M2_mpy_sat_hh_s0 :
2357 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
2358
2359 def int_hexagon_M2_mpy_sat_hh_s1 :
2360 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
2361
2362 def int_hexagon_M2_mpy_sat_hl_s0 :
2363 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
2364
2365 def int_hexagon_M2_mpy_sat_hl_s1 :
2366 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
2367
2368 def int_hexagon_M2_mpy_sat_lh_s0 :
2369 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
2370
2371 def int_hexagon_M2_mpy_sat_lh_s1 :
2372 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
2373
2374 def int_hexagon_M2_mpy_sat_ll_s0 :
2375 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
2376
2377 def int_hexagon_M2_mpy_sat_ll_s1 :
2378 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
2379
2380 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
2381 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
2382
2383 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
2384 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
2385
2386 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
2387 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
2388
2389 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
2390 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
2391
2392 def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
2393 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
2394
2395 def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
2396 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
2397
2398 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
2399 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
2400
2401 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
2402 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
2403
2404 def int_hexagon_M2_mpy_up :
2405 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;
2406
2407 def int_hexagon_M2_mpy_up_s1 :
2408 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
2409
2410 def int_hexagon_M2_mpy_up_s1_sat :
2411 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
2412
2413 def int_hexagon_M2_mpyd_acc_hh_s0 :
2414 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
2415
2416 def int_hexagon_M2_mpyd_acc_hh_s1 :
2417 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
2418
2419 def int_hexagon_M2_mpyd_acc_hl_s0 :
2420 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
2421
2422 def int_hexagon_M2_mpyd_acc_hl_s1 :
2423 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
2424
2425 def int_hexagon_M2_mpyd_acc_lh_s0 :
2426 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
2427
2428 def int_hexagon_M2_mpyd_acc_lh_s1 :
2429 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
2430
2431 def int_hexagon_M2_mpyd_acc_ll_s0 :
2432 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
2433
2434 def int_hexagon_M2_mpyd_acc_ll_s1 :
2435 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
2436
2437 def int_hexagon_M2_mpyd_hh_s0 :
2438 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
2439
2440 def int_hexagon_M2_mpyd_hh_s1 :
2441 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
2442
2443 def int_hexagon_M2_mpyd_hl_s0 :
2444 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
2445
2446 def int_hexagon_M2_mpyd_hl_s1 :
2447 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
2448
2449 def int_hexagon_M2_mpyd_lh_s0 :
2450 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
2451
2452 def int_hexagon_M2_mpyd_lh_s1 :
2453 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
2454
2455 def int_hexagon_M2_mpyd_ll_s0 :
2456 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
2457
2458 def int_hexagon_M2_mpyd_ll_s1 :
2459 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
2460
2461 def int_hexagon_M2_mpyd_nac_hh_s0 :
2462 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
2463
2464 def int_hexagon_M2_mpyd_nac_hh_s1 :
2465 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
2466
2467 def int_hexagon_M2_mpyd_nac_hl_s0 :
2468 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
2469
2470 def int_hexagon_M2_mpyd_nac_hl_s1 :
2471 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
2472
2473 def int_hexagon_M2_mpyd_nac_lh_s0 :
2474 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
2475
2476 def int_hexagon_M2_mpyd_nac_lh_s1 :
2477 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
2478
2479 def int_hexagon_M2_mpyd_nac_ll_s0 :
2480 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
2481
2482 def int_hexagon_M2_mpyd_nac_ll_s1 :
2483 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
2484
2485 def int_hexagon_M2_mpyd_rnd_hh_s0 :
2486 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
2487
2488 def int_hexagon_M2_mpyd_rnd_hh_s1 :
2489 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
2490
2491 def int_hexagon_M2_mpyd_rnd_hl_s0 :
2492 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
2493
2494 def int_hexagon_M2_mpyd_rnd_hl_s1 :
2495 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
2496
2497 def int_hexagon_M2_mpyd_rnd_lh_s0 :
2498 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
2499
2500 def int_hexagon_M2_mpyd_rnd_lh_s1 :
2501 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
2502
2503 def int_hexagon_M2_mpyd_rnd_ll_s0 :
2504 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
2505
2506 def int_hexagon_M2_mpyd_rnd_ll_s1 :
2507 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
2508
2509 def int_hexagon_M2_mpyi :
2510 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;
2511
2512 def int_hexagon_M2_mpysmi :
2513 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2514
2515 def int_hexagon_M2_mpysu_up :
2516 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;
2517
2518 def int_hexagon_M2_mpyu_acc_hh_s0 :
2519 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
2520
2521 def int_hexagon_M2_mpyu_acc_hh_s1 :
2522 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
2523
2524 def int_hexagon_M2_mpyu_acc_hl_s0 :
2525 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
2526
2527 def int_hexagon_M2_mpyu_acc_hl_s1 :
2528 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
2529
2530 def int_hexagon_M2_mpyu_acc_lh_s0 :
2531 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
2532
2533 def int_hexagon_M2_mpyu_acc_lh_s1 :
2534 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
2535
2536 def int_hexagon_M2_mpyu_acc_ll_s0 :
2537 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
2538
2539 def int_hexagon_M2_mpyu_acc_ll_s1 :
2540 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
2541
2542 def int_hexagon_M2_mpyu_hh_s0 :
2543 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
2544
2545 def int_hexagon_M2_mpyu_hh_s1 :
2546 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
2547
2548 def int_hexagon_M2_mpyu_hl_s0 :
2549 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
2550
2551 def int_hexagon_M2_mpyu_hl_s1 :
2552 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
2553
2554 def int_hexagon_M2_mpyu_lh_s0 :
2555 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
2556
2557 def int_hexagon_M2_mpyu_lh_s1 :
2558 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
2559
2560 def int_hexagon_M2_mpyu_ll_s0 :
2561 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
2562
2563 def int_hexagon_M2_mpyu_ll_s1 :
2564 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
2565
2566 def int_hexagon_M2_mpyu_nac_hh_s0 :
2567 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
2568
2569 def int_hexagon_M2_mpyu_nac_hh_s1 :
2570 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
2571
2572 def int_hexagon_M2_mpyu_nac_hl_s0 :
2573 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
2574
2575 def int_hexagon_M2_mpyu_nac_hl_s1 :
2576 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
2577
2578 def int_hexagon_M2_mpyu_nac_lh_s0 :
2579 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
2580
2581 def int_hexagon_M2_mpyu_nac_lh_s1 :
2582 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
2583
2584 def int_hexagon_M2_mpyu_nac_ll_s0 :
2585 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
2586
2587 def int_hexagon_M2_mpyu_nac_ll_s1 :
2588 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
2589
2590 def int_hexagon_M2_mpyu_up :
2591 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;
2592
2593 def int_hexagon_M2_mpyud_acc_hh_s0 :
2594 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
2595
2596 def int_hexagon_M2_mpyud_acc_hh_s1 :
2597 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
2598
2599 def int_hexagon_M2_mpyud_acc_hl_s0 :
2600 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
2601
2602 def int_hexagon_M2_mpyud_acc_hl_s1 :
2603 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
2604
2605 def int_hexagon_M2_mpyud_acc_lh_s0 :
2606 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
2607
2608 def int_hexagon_M2_mpyud_acc_lh_s1 :
2609 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
2610
2611 def int_hexagon_M2_mpyud_acc_ll_s0 :
2612 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
2613
2614 def int_hexagon_M2_mpyud_acc_ll_s1 :
2615 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
2616
2617 def int_hexagon_M2_mpyud_hh_s0 :
2618 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
2619
2620 def int_hexagon_M2_mpyud_hh_s1 :
2621 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
2622
2623 def int_hexagon_M2_mpyud_hl_s0 :
2624 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
2625
2626 def int_hexagon_M2_mpyud_hl_s1 :
2627 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
2628
2629 def int_hexagon_M2_mpyud_lh_s0 :
2630 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
2631
2632 def int_hexagon_M2_mpyud_lh_s1 :
2633 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
2634
2635 def int_hexagon_M2_mpyud_ll_s0 :
2636 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
2637
2638 def int_hexagon_M2_mpyud_ll_s1 :
2639 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
2640
2641 def int_hexagon_M2_mpyud_nac_hh_s0 :
2642 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
2643
2644 def int_hexagon_M2_mpyud_nac_hh_s1 :
2645 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
2646
2647 def int_hexagon_M2_mpyud_nac_hl_s0 :
2648 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
2649
2650 def int_hexagon_M2_mpyud_nac_hl_s1 :
2651 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
2652
2653 def int_hexagon_M2_mpyud_nac_lh_s0 :
2654 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
2655
2656 def int_hexagon_M2_mpyud_nac_lh_s1 :
2657 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
2658
2659 def int_hexagon_M2_mpyud_nac_ll_s0 :
2660 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
2661
2662 def int_hexagon_M2_mpyud_nac_ll_s1 :
2663 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
2664
2665 def int_hexagon_M2_mpyui :
2666 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;
2667
2668 def int_hexagon_M2_nacci :
2669 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;
2670
2671 def int_hexagon_M2_naccii :
2672 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2673
2674 def int_hexagon_M2_subacc :
2675 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;
2676
2677 def int_hexagon_M2_vabsdiffh :
2678 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">;
2679
2680 def int_hexagon_M2_vabsdiffw :
2681 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">;
2682
2683 def int_hexagon_M2_vcmac_s0_sat_i :
2684 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
2685
2686 def int_hexagon_M2_vcmac_s0_sat_r :
2687 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
2688
2689 def int_hexagon_M2_vcmpy_s0_sat_i :
2690 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
2691
2692 def int_hexagon_M2_vcmpy_s0_sat_r :
2693 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
2694
2695 def int_hexagon_M2_vcmpy_s1_sat_i :
2696 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
2697
2698 def int_hexagon_M2_vcmpy_s1_sat_r :
2699 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
2700
2701 def int_hexagon_M2_vdmacs_s0 :
2702 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
2703
2704 def int_hexagon_M2_vdmacs_s1 :
2705 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
2706
2707 def int_hexagon_M2_vdmpyrs_s0 :
2708 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
2709
2710 def int_hexagon_M2_vdmpyrs_s1 :
2711 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
2712
2713 def int_hexagon_M2_vdmpys_s0 :
2714 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
2715
2716 def int_hexagon_M2_vdmpys_s1 :
2717 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
2718
2719 def int_hexagon_M2_vmac2 :
2720 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;
2721
2722 def int_hexagon_M2_vmac2es :
2723 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">;
2724
2725 def int_hexagon_M2_vmac2es_s0 :
2726 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
2727
2728 def int_hexagon_M2_vmac2es_s1 :
2729 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
2730
2731 def int_hexagon_M2_vmac2s_s0 :
2732 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
2733
2734 def int_hexagon_M2_vmac2s_s1 :
2735 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
2736
2737 def int_hexagon_M2_vmac2su_s0 :
2738 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
2739
2740 def int_hexagon_M2_vmac2su_s1 :
2741 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
2742
2743 def int_hexagon_M2_vmpy2es_s0 :
2744 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
2745
2746 def int_hexagon_M2_vmpy2es_s1 :
2747 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
2748
2749 def int_hexagon_M2_vmpy2s_s0 :
2750 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
2751
2752 def int_hexagon_M2_vmpy2s_s0pack :
2753 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
2754
2755 def int_hexagon_M2_vmpy2s_s1 :
2756 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
2757
2758 def int_hexagon_M2_vmpy2s_s1pack :
2759 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
2760
2761 def int_hexagon_M2_vmpy2su_s0 :
2762 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
2763
2764 def int_hexagon_M2_vmpy2su_s1 :
2765 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
2766
2767 def int_hexagon_M2_vraddh :
2768 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">;
2769
2770 def int_hexagon_M2_vradduh :
2771 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;
2772
2773 def int_hexagon_M2_vrcmaci_s0 :
2774 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
2775
2776 def int_hexagon_M2_vrcmaci_s0c :
2777 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
2778
2779 def int_hexagon_M2_vrcmacr_s0 :
2780 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
2781
2782 def int_hexagon_M2_vrcmacr_s0c :
2783 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
2784
2785 def int_hexagon_M2_vrcmpyi_s0 :
2786 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
2787
2788 def int_hexagon_M2_vrcmpyi_s0c :
2789 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
2790
2791 def int_hexagon_M2_vrcmpyr_s0 :
2792 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
2793
2794 def int_hexagon_M2_vrcmpyr_s0c :
2795 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
2796
2797 def int_hexagon_M2_vrcmpys_acc_s1 :
2798 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
2799
2800 def int_hexagon_M2_vrcmpys_s1 :
2801 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
2802
2803 def int_hexagon_M2_vrcmpys_s1rp :
2804 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
2805
2806 def int_hexagon_M2_vrmac_s0 :
2807 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">;
2808
2809 def int_hexagon_M2_vrmpy_s0 :
2810 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
2811
2812 def int_hexagon_M2_xor_xacc :
2813 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;
2814
2815 def int_hexagon_M4_and_and :
2816 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;
2817
2818 def int_hexagon_M4_and_andn :
2819 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;
2820
2821 def int_hexagon_M4_and_or :
2822 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;
2823
2824 def int_hexagon_M4_and_xor :
2825 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;
2826
2827 def int_hexagon_M4_cmpyi_wh :
2828 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
2829
2830 def int_hexagon_M4_cmpyi_whc :
2831 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
2832
2833 def int_hexagon_M4_cmpyr_wh :
2834 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
2835
2836 def int_hexagon_M4_cmpyr_whc :
2837 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
2838
2839 def int_hexagon_M4_mac_up_s1_sat :
2840 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
2841
2842 def int_hexagon_M4_mpyri_addi :
2843 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
2844
2845 def int_hexagon_M4_mpyri_addr :
2846 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2847
2848 def int_hexagon_M4_mpyri_addr_u2 :
2849 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2850
2851 def int_hexagon_M4_mpyrr_addi :
2852 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
2853
2854 def int_hexagon_M4_mpyrr_addr :
2855 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
2856
2857 def int_hexagon_M4_nac_up_s1_sat :
2858 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
2859
2860 def int_hexagon_M4_or_and :
2861 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;
2862
2863 def int_hexagon_M4_or_andn :
2864 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;
2865
2866 def int_hexagon_M4_or_or :
2867 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;
2868
2869 def int_hexagon_M4_or_xor :
2870 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;
2871
2872 def int_hexagon_M4_pmpyw :
2873 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;
2874
2875 def int_hexagon_M4_pmpyw_acc :
2876 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
2877
2878 def int_hexagon_M4_vpmpyh :
2879 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;
2880
2881 def int_hexagon_M4_vpmpyh_acc :
2882 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
2883
2884 def int_hexagon_M4_vrmpyeh_acc_s0 :
2885 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
2886
2887 def int_hexagon_M4_vrmpyeh_acc_s1 :
2888 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
2889
2890 def int_hexagon_M4_vrmpyeh_s0 :
2891 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
2892
2893 def int_hexagon_M4_vrmpyeh_s1 :
2894 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
2895
2896 def int_hexagon_M4_vrmpyoh_acc_s0 :
2897 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
2898
2899 def int_hexagon_M4_vrmpyoh_acc_s1 :
2900 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
2901
2902 def int_hexagon_M4_vrmpyoh_s0 :
2903 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
2904
2905 def int_hexagon_M4_vrmpyoh_s1 :
2906 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
2907
2908 def int_hexagon_M4_xor_and :
2909 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;
2910
2911 def int_hexagon_M4_xor_andn :
2912 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;
2913
2914 def int_hexagon_M4_xor_or :
2915 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">;
2916
2917 def int_hexagon_M4_xor_xacc :
2918 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;
2919
2920 def int_hexagon_M5_vdmacbsu :
2921 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">;
2922
2923 def int_hexagon_M5_vdmpybsu :
2924 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;
2925
2926 def int_hexagon_M5_vmacbsu :
2927 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;
2928
2929 def int_hexagon_M5_vmacbuu :
2930 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;
2931
2932 def int_hexagon_M5_vmpybsu :
2933 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">;
2934
2935 def int_hexagon_M5_vmpybuu :
2936 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;
2937
2938 def int_hexagon_M5_vrmacbsu :
2939 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;
2940
2941 def int_hexagon_M5_vrmacbuu :
2942 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;
2943
2944 def int_hexagon_M5_vrmpybsu :
2945 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;
2946
2947 def int_hexagon_M5_vrmpybuu :
2948 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;
2949
2950 def int_hexagon_S2_addasl_rrri :
2951 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2952
2953 def int_hexagon_S2_asl_i_p :
2954 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2955
2956 def int_hexagon_S2_asl_i_p_acc :
2957 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2958
2959 def int_hexagon_S2_asl_i_p_and :
2960 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2961
2962 def int_hexagon_S2_asl_i_p_nac :
2963 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2964
2965 def int_hexagon_S2_asl_i_p_or :
2966 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2967
2968 def int_hexagon_S2_asl_i_p_xacc :
2969 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2970
2971 def int_hexagon_S2_asl_i_r :
2972 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2973
2974 def int_hexagon_S2_asl_i_r_acc :
2975 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2976
2977 def int_hexagon_S2_asl_i_r_and :
2978 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2979
2980 def int_hexagon_S2_asl_i_r_nac :
2981 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2982
2983 def int_hexagon_S2_asl_i_r_or :
2984 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2985
2986 def int_hexagon_S2_asl_i_r_sat :
2987 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2988
2989 def int_hexagon_S2_asl_i_r_xacc :
2990 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
2991
2992 def int_hexagon_S2_asl_i_vh :
2993 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2994
2995 def int_hexagon_S2_asl_i_vw :
2996 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
2997
2998 def int_hexagon_S2_asl_r_p :
2999 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;
3000
3001 def int_hexagon_S2_asl_r_p_acc :
3002 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
3003
3004 def int_hexagon_S2_asl_r_p_and :
3005 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
3006
3007 def int_hexagon_S2_asl_r_p_nac :
3008 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
3009
3010 def int_hexagon_S2_asl_r_p_or :
3011 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
3012
3013 def int_hexagon_S2_asl_r_p_xor :
3014 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
3015
3016 def int_hexagon_S2_asl_r_r :
3017 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;
3018
3019 def int_hexagon_S2_asl_r_r_acc :
3020 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
3021
3022 def int_hexagon_S2_asl_r_r_and :
3023 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
3024
3025 def int_hexagon_S2_asl_r_r_nac :
3026 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
3027
3028 def int_hexagon_S2_asl_r_r_or :
3029 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
3030
3031 def int_hexagon_S2_asl_r_r_sat :
3032 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
3033
3034 def int_hexagon_S2_asl_r_vh :
3035 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">;
3036
3037 def int_hexagon_S2_asl_r_vw :
3038 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">;
3039
3040 def int_hexagon_S2_asr_i_p :
3041 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3042
3043 def int_hexagon_S2_asr_i_p_acc :
3044 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3045
3046 def int_hexagon_S2_asr_i_p_and :
3047 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3048
3049 def int_hexagon_S2_asr_i_p_nac :
3050 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3051
3052 def int_hexagon_S2_asr_i_p_or :
3053 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3054
3055 def int_hexagon_S2_asr_i_p_rnd :
3056 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3057
3058 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
3059 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3060
3061 def int_hexagon_S2_asr_i_r :
3062 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3063
3064 def int_hexagon_S2_asr_i_r_acc :
3065 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3066
3067 def int_hexagon_S2_asr_i_r_and :
3068 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3069
3070 def int_hexagon_S2_asr_i_r_nac :
3071 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3072
3073 def int_hexagon_S2_asr_i_r_or :
3074 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3075
3076 def int_hexagon_S2_asr_i_r_rnd :
3077 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3078
3079 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
3080 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3081
3082 def int_hexagon_S2_asr_i_svw_trun :
3083 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3084
3085 def int_hexagon_S2_asr_i_vh :
3086 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3087
3088 def int_hexagon_S2_asr_i_vw :
3089 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3090
3091 def int_hexagon_S2_asr_r_p :
3092 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;
3093
3094 def int_hexagon_S2_asr_r_p_acc :
3095 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
3096
3097 def int_hexagon_S2_asr_r_p_and :
3098 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
3099
3100 def int_hexagon_S2_asr_r_p_nac :
3101 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
3102
3103 def int_hexagon_S2_asr_r_p_or :
3104 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
3105
3106 def int_hexagon_S2_asr_r_p_xor :
3107 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
3108
3109 def int_hexagon_S2_asr_r_r :
3110 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;
3111
3112 def int_hexagon_S2_asr_r_r_acc :
3113 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
3114
3115 def int_hexagon_S2_asr_r_r_and :
3116 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
3117
3118 def int_hexagon_S2_asr_r_r_nac :
3119 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
3120
3121 def int_hexagon_S2_asr_r_r_or :
3122 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
3123
3124 def int_hexagon_S2_asr_r_r_sat :
3125 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
3126
3127 def int_hexagon_S2_asr_r_svw_trun :
3128 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
3129
3130 def int_hexagon_S2_asr_r_vh :
3131 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;
3132
3133 def int_hexagon_S2_asr_r_vw :
3134 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;
3135
3136 def int_hexagon_S2_brev :
3137 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;
3138
3139 def int_hexagon_S2_brevp :
3140 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;
3141
3142 def int_hexagon_S2_cl0 :
3143 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;
3144
3145 def int_hexagon_S2_cl0p :
3146 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;
3147
3148 def int_hexagon_S2_cl1 :
3149 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;
3150
3151 def int_hexagon_S2_cl1p :
3152 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;
3153
3154 def int_hexagon_S2_clb :
3155 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">;
3156
3157 def int_hexagon_S2_clbnorm :
3158 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;
3159
3160 def int_hexagon_S2_clbp :
3161 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;
3162
3163 def int_hexagon_S2_clrbit_i :
3164 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3165
3166 def int_hexagon_S2_clrbit_r :
3167 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;
3168
3169 def int_hexagon_S2_ct0 :
3170 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;
3171
3172 def int_hexagon_S2_ct0p :
3173 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;
3174
3175 def int_hexagon_S2_ct1 :
3176 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;
3177
3178 def int_hexagon_S2_ct1p :
3179 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;
3180
3181 def int_hexagon_S2_deinterleave :
3182 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;
3183
3184 def int_hexagon_S2_extractu :
3185 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
3186
3187 def int_hexagon_S2_extractu_rp :
3188 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;
3189
3190 def int_hexagon_S2_extractup :
3191 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
3192
3193 def int_hexagon_S2_extractup_rp :
3194 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;
3195
3196 def int_hexagon_S2_insert :
3197 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3198
3199 def int_hexagon_S2_insert_rp :
3200 Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">;
3201
3202 def int_hexagon_S2_insertp :
3203 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3204
3205 def int_hexagon_S2_insertp_rp :
3206 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;
3207
3208 def int_hexagon_S2_interleave :
3209 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;
3210
3211 def int_hexagon_S2_lfsp :
3212 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;
3213
3214 def int_hexagon_S2_lsl_r_p :
3215 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;
3216
3217 def int_hexagon_S2_lsl_r_p_acc :
3218 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
3219
3220 def int_hexagon_S2_lsl_r_p_and :
3221 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
3222
3223 def int_hexagon_S2_lsl_r_p_nac :
3224 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
3225
3226 def int_hexagon_S2_lsl_r_p_or :
3227 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
3228
3229 def int_hexagon_S2_lsl_r_p_xor :
3230 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
3231
3232 def int_hexagon_S2_lsl_r_r :
3233 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;
3234
3235 def int_hexagon_S2_lsl_r_r_acc :
3236 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
3237
3238 def int_hexagon_S2_lsl_r_r_and :
3239 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
3240
3241 def int_hexagon_S2_lsl_r_r_nac :
3242 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
3243
3244 def int_hexagon_S2_lsl_r_r_or :
3245 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
3246
3247 def int_hexagon_S2_lsl_r_vh :
3248 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
3249
3250 def int_hexagon_S2_lsl_r_vw :
3251 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
3252
3253 def int_hexagon_S2_lsr_i_p :
3254 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3255
3256 def int_hexagon_S2_lsr_i_p_acc :
3257 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3258
3259 def int_hexagon_S2_lsr_i_p_and :
3260 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3261
3262 def int_hexagon_S2_lsr_i_p_nac :
3263 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3264
3265 def int_hexagon_S2_lsr_i_p_or :
3266 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3267
3268 def int_hexagon_S2_lsr_i_p_xacc :
3269 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3270
3271 def int_hexagon_S2_lsr_i_r :
3272 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3273
3274 def int_hexagon_S2_lsr_i_r_acc :
3275 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3276
3277 def int_hexagon_S2_lsr_i_r_and :
3278 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3279
3280 def int_hexagon_S2_lsr_i_r_nac :
3281 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3282
3283 def int_hexagon_S2_lsr_i_r_or :
3284 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3285
3286 def int_hexagon_S2_lsr_i_r_xacc :
3287 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3288
3289 def int_hexagon_S2_lsr_i_vh :
3290 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3291
3292 def int_hexagon_S2_lsr_i_vw :
3293 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3294
3295 def int_hexagon_S2_lsr_r_p :
3296 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">;
3297
3298 def int_hexagon_S2_lsr_r_p_acc :
3299 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
3300
3301 def int_hexagon_S2_lsr_r_p_and :
3302 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
3303
3304 def int_hexagon_S2_lsr_r_p_nac :
3305 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
3306
3307 def int_hexagon_S2_lsr_r_p_or :
3308 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
3309
3310 def int_hexagon_S2_lsr_r_p_xor :
3311 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
3312
3313 def int_hexagon_S2_lsr_r_r :
3314 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">;
3315
3316 def int_hexagon_S2_lsr_r_r_acc :
3317 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
3318
3319 def int_hexagon_S2_lsr_r_r_and :
3320 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
3321
3322 def int_hexagon_S2_lsr_r_r_nac :
3323 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
3324
3325 def int_hexagon_S2_lsr_r_r_or :
3326 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
3327
3328 def int_hexagon_S2_lsr_r_vh :
3329 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
3330
3331 def int_hexagon_S2_lsr_r_vw :
3332 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
3333
3334 def int_hexagon_S2_packhl :
3335 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;
3336
3337 def int_hexagon_S2_parityp :
3338 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;
3339
3340 def int_hexagon_S2_setbit_i :
3341 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3342
3343 def int_hexagon_S2_setbit_r :
3344 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">;
3345
3346 def int_hexagon_S2_shuffeb :
3347 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">;
3348
3349 def int_hexagon_S2_shuffeh :
3350 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;
3351
3352 def int_hexagon_S2_shuffob :
3353 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">;
3354
3355 def int_hexagon_S2_shuffoh :
3356 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;
3357
3358 def int_hexagon_S2_svsathb :
3359 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;
3360
3361 def int_hexagon_S2_svsathub :
3362 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">;
3363
3364 def int_hexagon_S2_tableidxb_goodsyntax :
3365 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3366
3367 def int_hexagon_S2_tableidxd_goodsyntax :
3368 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3369
3370 def int_hexagon_S2_tableidxh_goodsyntax :
3371 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3372
3373 def int_hexagon_S2_tableidxw_goodsyntax :
3374 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3375
3376 def int_hexagon_S2_togglebit_i :
3377 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3378
3379 def int_hexagon_S2_togglebit_r :
3380 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;
3381
3382 def int_hexagon_S2_tstbit_i :
3383 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3384
3385 def int_hexagon_S2_tstbit_r :
3386 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;
3387
3388 def int_hexagon_S2_valignib :
3389 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3390
3391 def int_hexagon_S2_valignrb :
3392 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">;
3393
3394 def int_hexagon_S2_vcnegh :
3395 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;
3396
3397 def int_hexagon_S2_vcrotate :
3398 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;
3399
3400 def int_hexagon_S2_vrcnegh :
3401 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;
3402
3403 def int_hexagon_S2_vrndpackwh :
3404 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;
3405
3406 def int_hexagon_S2_vrndpackwhs :
3407 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
3408
3409 def int_hexagon_S2_vsathb :
3410 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;
3411
3412 def int_hexagon_S2_vsathb_nopack :
3413 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
3414
3415 def int_hexagon_S2_vsathub :
3416 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;
3417
3418 def int_hexagon_S2_vsathub_nopack :
3419 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
3420
3421 def int_hexagon_S2_vsatwh :
3422 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;
3423
3424 def int_hexagon_S2_vsatwh_nopack :
3425 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
3426
3427 def int_hexagon_S2_vsatwuh :
3428 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;
3429
3430 def int_hexagon_S2_vsatwuh_nopack :
3431 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
3432
3433 def int_hexagon_S2_vsplatrb :
3434 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;
3435
3436 def int_hexagon_S2_vsplatrh :
3437 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;
3438
3439 def int_hexagon_S2_vspliceib :
3440 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3441
3442 def int_hexagon_S2_vsplicerb :
3443 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">;
3444
3445 def int_hexagon_S2_vsxtbh :
3446 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;
3447
3448 def int_hexagon_S2_vsxthw :
3449 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;
3450
3451 def int_hexagon_S2_vtrunehb :
3452 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;
3453
3454 def int_hexagon_S2_vtrunewh :
3455 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;
3456
3457 def int_hexagon_S2_vtrunohb :
3458 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">;
3459
3460 def int_hexagon_S2_vtrunowh :
3461 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">;
3462
3463 def int_hexagon_S2_vzxtbh :
3464 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;
3465
3466 def int_hexagon_S2_vzxthw :
3467 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;
3468
3469 def int_hexagon_S4_addaddi :
3470 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3471
3472 def int_hexagon_S4_addi_asl_ri :
3473 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3474
3475 def int_hexagon_S4_addi_lsr_ri :
3476 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3477
3478 def int_hexagon_S4_andi_asl_ri :
3479 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3480
3481 def int_hexagon_S4_andi_lsr_ri :
3482 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3483
3484 def int_hexagon_S4_clbaddi :
3485 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3486
3487 def int_hexagon_S4_clbpaddi :
3488 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3489
3490 def int_hexagon_S4_clbpnorm :
3491 Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;
3492
3493 def int_hexagon_S4_extract :
3494 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
3495
3496 def int_hexagon_S4_extract_rp :
3497 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;
3498
3499 def int_hexagon_S4_extractp :
3500 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
3501
3502 def int_hexagon_S4_extractp_rp :
3503 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;
3504
3505 def int_hexagon_S4_lsli :
3506 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
3507
3508 def int_hexagon_S4_ntstbit_i :
3509 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3510
3511 def int_hexagon_S4_ntstbit_r :
3512 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;
3513
3514 def int_hexagon_S4_or_andi :
3515 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3516
3517 def int_hexagon_S4_or_andix :
3518 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3519
3520 def int_hexagon_S4_or_ori :
3521 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3522
3523 def int_hexagon_S4_ori_asl_ri :
3524 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3525
3526 def int_hexagon_S4_ori_lsr_ri :
3527 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3528
3529 def int_hexagon_S4_parity :
3530 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">;
3531
3532 def int_hexagon_S4_subaddi :
3533 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3534
3535 def int_hexagon_S4_subi_asl_ri :
3536 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3537
3538 def int_hexagon_S4_subi_lsr_ri :
3539 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
3540
3541 def int_hexagon_S4_vrcrotate :
3542 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3543
3544 def int_hexagon_S4_vrcrotate_acc :
3545 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
3546
3547 def int_hexagon_S4_vxaddsubh :
3548 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;
3549
3550 def int_hexagon_S4_vxaddsubhr :
3551 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
3552
3553 def int_hexagon_S4_vxaddsubw :
3554 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;
3555
3556 def int_hexagon_S4_vxsubaddh :
3557 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;
3558
3559 def int_hexagon_S4_vxsubaddhr :
3560 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
3561
3562 def int_hexagon_S4_vxsubaddw :
3563 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;
3564
3565 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
3566 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3567
3568 def int_hexagon_S5_asrhub_sat :
3569 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3570
3571 def int_hexagon_S5_popcountp :
3572 Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;
3573
3574 def int_hexagon_S5_vasrhrnd_goodsyntax :
3575 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3576
3577 def int_hexagon_Y2_dccleana :
3578 Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>;
3579
3580 def int_hexagon_Y2_dccleaninva :
3581 Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>;
3582
3583 def int_hexagon_Y2_dcfetch :
3584 Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>;
3585
3586 def int_hexagon_Y2_dcinva :
3587 Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>;
3588
3589 def int_hexagon_Y2_dczeroa :
3590 Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>;
3591
3592 def int_hexagon_Y4_l2fetch :
3593 Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>;
3594
3595 def int_hexagon_Y5_l2fetch :
3596 Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>;
3597
3598 // V60 Scalar Instructions.
3599
3600 def int_hexagon_S6_rol_i_p :
3601 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3602
3603 def int_hexagon_S6_rol_i_p_acc :
3604 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3605
3606 def int_hexagon_S6_rol_i_p_and :
3607 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3608
3609 def int_hexagon_S6_rol_i_p_nac :
3610 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3611
3612 def int_hexagon_S6_rol_i_p_or :
3613 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3614
3615 def int_hexagon_S6_rol_i_p_xacc :
3616 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3617
3618 def int_hexagon_S6_rol_i_r :
3619 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3620
3621 def int_hexagon_S6_rol_i_r_acc :
3622 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3623
3624 def int_hexagon_S6_rol_i_r_and :
3625 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3626
3627 def int_hexagon_S6_rol_i_r_nac :
3628 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3629
3630 def int_hexagon_S6_rol_i_r_or :
3631 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3632
3633 def int_hexagon_S6_rol_i_r_xacc :
3634 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
3635
3636 // V62 Scalar Instructions.
3637
3638 def int_hexagon_M6_vabsdiffb :
3639 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">;
3640
3641 def int_hexagon_M6_vabsdiffub :
3642 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">;
3643
3644 def int_hexagon_S6_vsplatrbp :
3645 Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">;
3646
3647 def int_hexagon_S6_vtrunehb_ppp :
3648 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
3649
3650 def int_hexagon_S6_vtrunohb_ppp :
3651 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;
3652
3653 // V65 Scalar Instructions.
3654
3655 def int_hexagon_A6_vcmpbeq_notany :
3656 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
3657
3658 // V66 Scalar Instructions.
3659
3660 def int_hexagon_F2_dfadd :
3661 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>;
3662
3663 def int_hexagon_F2_dfsub :
3664 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>;
3665
3666 def int_hexagon_M2_mnaci :
3667 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;
3668
3669 def int_hexagon_S2_mask :
3670 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
3671
3672 // V67 Scalar Instructions.
3673
3674 def int_hexagon_A7_clip :
3675 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3676
3677 def int_hexagon_A7_croundd_ri :
3678 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3679
3680 def int_hexagon_A7_croundd_rr :
3681 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">;
3682
3683 def int_hexagon_A7_vclip :
3684 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
3685
3686 def int_hexagon_F2_dfmax :
3687 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>;
3688
3689 def int_hexagon_F2_dfmin :
3690 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>;
3691
3692 def int_hexagon_F2_dfmpyfix :
3693 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>;
3694
3695 def int_hexagon_F2_dfmpyhh :
3696 Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>;
3697
3698 def int_hexagon_F2_dfmpylh :
3699 Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>;
3700
3701 def int_hexagon_F2_dfmpyll :
3702 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>;
3703
3704 def int_hexagon_M7_dcmpyiw :
3705 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">;
3706
3707 def int_hexagon_M7_dcmpyiw_acc :
3708 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">;
3709
3710 def int_hexagon_M7_dcmpyiwc :
3711 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">;
3712
3713 def int_hexagon_M7_dcmpyiwc_acc :
3714 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">;
3715
3716 def int_hexagon_M7_dcmpyrw :
3717 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">;
3718
3719 def int_hexagon_M7_dcmpyrw_acc :
3720 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">;
3721
3722 def int_hexagon_M7_dcmpyrwc :
3723 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">;
3724
3725 def int_hexagon_M7_dcmpyrwc_acc :
3726 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">;
3727
3728 def int_hexagon_M7_vdmpy :
3729 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">;
3730
3731 def int_hexagon_M7_vdmpy_acc :
3732 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">;
3733
3734 def int_hexagon_M7_wcmpyiw :
3735 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">;
3736
3737 def int_hexagon_M7_wcmpyiw_rnd :
3738 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">;
3739
3740 def int_hexagon_M7_wcmpyiwc :
3741 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">;
3742
3743 def int_hexagon_M7_wcmpyiwc_rnd :
3744 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">;
3745
3746 def int_hexagon_M7_wcmpyrw :
3747 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">;
3748
3749 def int_hexagon_M7_wcmpyrw_rnd :
3750 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">;
3751
3752 def int_hexagon_M7_wcmpyrwc :
3753 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">;
3754
3755 def int_hexagon_M7_wcmpyrwc_rnd :
3756 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">;
3757
3758 // V68 Scalar Instructions.
3759
3760 def int_hexagon_Y6_dmlink :
3761 Hexagon__ptrptr_Intrinsic<"HEXAGON_Y6_dmlink", [IntrArgMemOnly, IntrHasSideEffects]>;
3762
3763 def int_hexagon_Y6_dmpause :
3764 Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpause", [IntrArgMemOnly, IntrHasSideEffects]>;
3765
3766 def int_hexagon_Y6_dmpoll :
3767 Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpoll", [IntrArgMemOnly, IntrHasSideEffects]>;
3768
3769 def int_hexagon_Y6_dmresume :
3770 Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmresume", [IntrArgMemOnly, IntrHasSideEffects]>;
3771
3772 def int_hexagon_Y6_dmstart :
3773 Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmstart", [IntrArgMemOnly, IntrHasSideEffects]>;
3774
3775 def int_hexagon_Y6_dmwait :
3776 Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmwait", [IntrArgMemOnly, IntrHasSideEffects]>;
3777
3778 // V60 HVX Instructions.
3779
3780 def int_hexagon_V6_extractw :
3781 Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">;
3782
3783 def int_hexagon_V6_extractw_128B :
3784 Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">;
3785
3786 def int_hexagon_V6_hi :
3787 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">;
3788
3789 def int_hexagon_V6_hi_128B :
3790 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">;
3791
3792 def int_hexagon_V6_lo :
3793 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">;
3794
3795 def int_hexagon_V6_lo_128B :
3796 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">;
3797
3798 def int_hexagon_V6_lvsplatw :
3799 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">;
3800
3801 def int_hexagon_V6_lvsplatw_128B :
3802 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;
3803
3804 def int_hexagon_V6_pred_and :
3805 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and">;
3806
3807 def int_hexagon_V6_pred_and_128B :
3808 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_128B">;
3809
3810 def int_hexagon_V6_pred_and_n :
3811 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and_n">;
3812
3813 def int_hexagon_V6_pred_and_n_128B :
3814 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;
3815
3816 def int_hexagon_V6_pred_not :
3817 Hexagon_v64i1_v64i1_Intrinsic<"HEXAGON_V6_pred_not">;
3818
3819 def int_hexagon_V6_pred_not_128B :
3820 Hexagon_v128i1_v128i1_Intrinsic<"HEXAGON_V6_pred_not_128B">;
3821
3822 def int_hexagon_V6_pred_or :
3823 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or">;
3824
3825 def int_hexagon_V6_pred_or_128B :
3826 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_128B">;
3827
3828 def int_hexagon_V6_pred_or_n :
3829 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or_n">;
3830
3831 def int_hexagon_V6_pred_or_n_128B :
3832 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;
3833
3834 def int_hexagon_V6_pred_scalar2 :
3835 Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">;
3836
3837 def int_hexagon_V6_pred_scalar2_128B :
3838 Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;
3839
3840 def int_hexagon_V6_pred_xor :
3841 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_xor">;
3842
3843 def int_hexagon_V6_pred_xor_128B :
3844 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">;
3845
3846 def int_hexagon_V6_vS32b_nqpred_ai :
3847 Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai", [IntrWriteMem]>;
3848
3849 def int_hexagon_V6_vS32b_nqpred_ai_128B :
3850 Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B", [IntrWriteMem]>;
3851
3852 def int_hexagon_V6_vS32b_nt_nqpred_ai :
3853 Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai", [IntrWriteMem]>;
3854
3855 def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
3856 Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B", [IntrWriteMem]>;
3857
3858 def int_hexagon_V6_vS32b_nt_qpred_ai :
3859 Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai", [IntrWriteMem]>;
3860
3861 def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
3862 Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B", [IntrWriteMem]>;
3863
3864 def int_hexagon_V6_vS32b_qpred_ai :
3865 Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai", [IntrWriteMem]>;
3866
3867 def int_hexagon_V6_vS32b_qpred_ai_128B :
3868 Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B", [IntrWriteMem]>;
3869
3870 def int_hexagon_V6_vabsdiffh :
3871 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">;
3872
3873 def int_hexagon_V6_vabsdiffh_128B :
3874 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">;
3875
3876 def int_hexagon_V6_vabsdiffub :
3877 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">;
3878
3879 def int_hexagon_V6_vabsdiffub_128B :
3880 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">;
3881
3882 def int_hexagon_V6_vabsdiffuh :
3883 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">;
3884
3885 def int_hexagon_V6_vabsdiffuh_128B :
3886 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">;
3887
3888 def int_hexagon_V6_vabsdiffw :
3889 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">;
3890
3891 def int_hexagon_V6_vabsdiffw_128B :
3892 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">;
3893
3894 def int_hexagon_V6_vabsh :
3895 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">;
3896
3897 def int_hexagon_V6_vabsh_128B :
3898 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">;
3899
3900 def int_hexagon_V6_vabsh_sat :
3901 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">;
3902
3903 def int_hexagon_V6_vabsh_sat_128B :
3904 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;
3905
3906 def int_hexagon_V6_vabsw :
3907 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;
3908
3909 def int_hexagon_V6_vabsw_128B :
3910 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;
3911
3912 def int_hexagon_V6_vabsw_sat :
3913 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">;
3914
3915 def int_hexagon_V6_vabsw_sat_128B :
3916 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;
3917
3918 def int_hexagon_V6_vaddb :
3919 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">;
3920
3921 def int_hexagon_V6_vaddb_128B :
3922 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">;
3923
3924 def int_hexagon_V6_vaddb_dv :
3925 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">;
3926
3927 def int_hexagon_V6_vaddb_dv_128B :
3928 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;
3929
3930 def int_hexagon_V6_vaddbnq :
3931 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;
3932
3933 def int_hexagon_V6_vaddbnq_128B :
3934 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
3935
3936 def int_hexagon_V6_vaddbq :
3937 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">;
3938
3939 def int_hexagon_V6_vaddbq_128B :
3940 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">;
3941
3942 def int_hexagon_V6_vaddh :
3943 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">;
3944
3945 def int_hexagon_V6_vaddh_128B :
3946 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">;
3947
3948 def int_hexagon_V6_vaddh_dv :
3949 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;
3950
3951 def int_hexagon_V6_vaddh_dv_128B :
3952 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
3953
3954 def int_hexagon_V6_vaddhnq :
3955 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">;
3956
3957 def int_hexagon_V6_vaddhnq_128B :
3958 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;
3959
3960 def int_hexagon_V6_vaddhq :
3961 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">;
3962
3963 def int_hexagon_V6_vaddhq_128B :
3964 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">;
3965
3966 def int_hexagon_V6_vaddhsat :
3967 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">;
3968
3969 def int_hexagon_V6_vaddhsat_128B :
3970 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;
3971
3972 def int_hexagon_V6_vaddhsat_dv :
3973 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;
3974
3975 def int_hexagon_V6_vaddhsat_dv_128B :
3976 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;
3977
3978 def int_hexagon_V6_vaddhw :
3979 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">;
3980
3981 def int_hexagon_V6_vaddhw_128B :
3982 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">;
3983
3984 def int_hexagon_V6_vaddubh :
3985 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">;
3986
3987 def int_hexagon_V6_vaddubh_128B :
3988 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">;
3989
3990 def int_hexagon_V6_vaddubsat :
3991 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">;
3992
3993 def int_hexagon_V6_vaddubsat_128B :
3994 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;
3995
3996 def int_hexagon_V6_vaddubsat_dv :
3997 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;
3998
3999 def int_hexagon_V6_vaddubsat_dv_128B :
4000 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;
4001
4002 def int_hexagon_V6_vadduhsat :
4003 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">;
4004
4005 def int_hexagon_V6_vadduhsat_128B :
4006 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;
4007
4008 def int_hexagon_V6_vadduhsat_dv :
4009 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;
4010
4011 def int_hexagon_V6_vadduhsat_dv_128B :
4012 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;
4013
4014 def int_hexagon_V6_vadduhw :
4015 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">;
4016
4017 def int_hexagon_V6_vadduhw_128B :
4018 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">;
4019
4020 def int_hexagon_V6_vaddw :
4021 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">;
4022
4023 def int_hexagon_V6_vaddw_128B :
4024 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">;
4025
4026 def int_hexagon_V6_vaddw_dv :
4027 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">;
4028
4029 def int_hexagon_V6_vaddw_dv_128B :
4030 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;
4031
4032 def int_hexagon_V6_vaddwnq :
4033 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">;
4034
4035 def int_hexagon_V6_vaddwnq_128B :
4036 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;
4037
4038 def int_hexagon_V6_vaddwq :
4039 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">;
4040
4041 def int_hexagon_V6_vaddwq_128B :
4042 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">;
4043
4044 def int_hexagon_V6_vaddwsat :
4045 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;
4046
4047 def int_hexagon_V6_vaddwsat_128B :
4048 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
4049
4050 def int_hexagon_V6_vaddwsat_dv :
4051 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;
4052
4053 def int_hexagon_V6_vaddwsat_dv_128B :
4054 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;
4055
4056 def int_hexagon_V6_valignb :
4057 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">;
4058
4059 def int_hexagon_V6_valignb_128B :
4060 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">;
4061
4062 def int_hexagon_V6_valignbi :
4063 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
4064
4065 def int_hexagon_V6_valignbi_128B :
4066 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
4067
4068 def int_hexagon_V6_vand :
4069 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">;
4070
4071 def int_hexagon_V6_vand_128B :
4072 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">;
4073
4074 def int_hexagon_V6_vandqrt :
4075 Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt">;
4076
4077 def int_hexagon_V6_vandqrt_128B :
4078 Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">;
4079
4080 def int_hexagon_V6_vandqrt_acc :
4081 Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">;
4082
4083 def int_hexagon_V6_vandqrt_acc_128B :
4084 Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;
4085
4086 def int_hexagon_V6_vandvrt :
4087 Hexagon_v64i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">;
4088
4089 def int_hexagon_V6_vandvrt_128B :
4090 Hexagon_v128i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">;
4091
4092 def int_hexagon_V6_vandvrt_acc :
4093 Hexagon_v64i1_v64i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">;
4094
4095 def int_hexagon_V6_vandvrt_acc_128B :
4096 Hexagon_v128i1_v128i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;
4097
4098 def int_hexagon_V6_vaslh :
4099 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">;
4100
4101 def int_hexagon_V6_vaslh_128B :
4102 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">;
4103
4104 def int_hexagon_V6_vaslhv :
4105 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">;
4106
4107 def int_hexagon_V6_vaslhv_128B :
4108 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">;
4109
4110 def int_hexagon_V6_vaslw :
4111 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">;
4112
4113 def int_hexagon_V6_vaslw_128B :
4114 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">;
4115
4116 def int_hexagon_V6_vaslw_acc :
4117 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">;
4118
4119 def int_hexagon_V6_vaslw_acc_128B :
4120 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;
4121
4122 def int_hexagon_V6_vaslwv :
4123 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">;
4124
4125 def int_hexagon_V6_vaslwv_128B :
4126 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">;
4127
4128 def int_hexagon_V6_vasrh :
4129 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">;
4130
4131 def int_hexagon_V6_vasrh_128B :
4132 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">;
4133
4134 def int_hexagon_V6_vasrhbrndsat :
4135 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;
4136
4137 def int_hexagon_V6_vasrhbrndsat_128B :
4138 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;
4139
4140 def int_hexagon_V6_vasrhubrndsat :
4141 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;
4142
4143 def int_hexagon_V6_vasrhubrndsat_128B :
4144 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;
4145
4146 def int_hexagon_V6_vasrhubsat :
4147 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">;
4148
4149 def int_hexagon_V6_vasrhubsat_128B :
4150 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;
4151
4152 def int_hexagon_V6_vasrhv :
4153 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">;
4154
4155 def int_hexagon_V6_vasrhv_128B :
4156 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">;
4157
4158 def int_hexagon_V6_vasrw :
4159 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;
4160
4161 def int_hexagon_V6_vasrw_128B :
4162 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;
4163
4164 def int_hexagon_V6_vasrw_acc :
4165 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">;
4166
4167 def int_hexagon_V6_vasrw_acc_128B :
4168 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;
4169
4170 def int_hexagon_V6_vasrwh :
4171 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">;
4172
4173 def int_hexagon_V6_vasrwh_128B :
4174 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">;
4175
4176 def int_hexagon_V6_vasrwhrndsat :
4177 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;
4178
4179 def int_hexagon_V6_vasrwhrndsat_128B :
4180 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;
4181
4182 def int_hexagon_V6_vasrwhsat :
4183 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">;
4184
4185 def int_hexagon_V6_vasrwhsat_128B :
4186 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;
4187
4188 def int_hexagon_V6_vasrwuhsat :
4189 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">;
4190
4191 def int_hexagon_V6_vasrwuhsat_128B :
4192 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;
4193
4194 def int_hexagon_V6_vasrwv :
4195 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;
4196
4197 def int_hexagon_V6_vasrwv_128B :
4198 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
4199
4200 def int_hexagon_V6_vassign :
4201 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">;
4202
4203 def int_hexagon_V6_vassign_128B :
4204 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">;
4205
4206 def int_hexagon_V6_vassignp :
4207 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">;
4208
4209 def int_hexagon_V6_vassignp_128B :
4210 Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">;
4211
4212 def int_hexagon_V6_vavgh :
4213 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">;
4214
4215 def int_hexagon_V6_vavgh_128B :
4216 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">;
4217
4218 def int_hexagon_V6_vavghrnd :
4219 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">;
4220
4221 def int_hexagon_V6_vavghrnd_128B :
4222 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;
4223
4224 def int_hexagon_V6_vavgub :
4225 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">;
4226
4227 def int_hexagon_V6_vavgub_128B :
4228 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">;
4229
4230 def int_hexagon_V6_vavgubrnd :
4231 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">;
4232
4233 def int_hexagon_V6_vavgubrnd_128B :
4234 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;
4235
4236 def int_hexagon_V6_vavguh :
4237 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">;
4238
4239 def int_hexagon_V6_vavguh_128B :
4240 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">;
4241
4242 def int_hexagon_V6_vavguhrnd :
4243 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">;
4244
4245 def int_hexagon_V6_vavguhrnd_128B :
4246 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;
4247
4248 def int_hexagon_V6_vavgw :
4249 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">;
4250
4251 def int_hexagon_V6_vavgw_128B :
4252 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">;
4253
4254 def int_hexagon_V6_vavgwrnd :
4255 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">;
4256
4257 def int_hexagon_V6_vavgwrnd_128B :
4258 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;
4259
4260 def int_hexagon_V6_vcl0h :
4261 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">;
4262
4263 def int_hexagon_V6_vcl0h_128B :
4264 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">;
4265
4266 def int_hexagon_V6_vcl0w :
4267 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">;
4268
4269 def int_hexagon_V6_vcl0w_128B :
4270 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">;
4271
4272 def int_hexagon_V6_vcombine :
4273 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">;
4274
4275 def int_hexagon_V6_vcombine_128B :
4276 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">;
4277
4278 def int_hexagon_V6_vd0 :
4279 Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">;
4280
4281 def int_hexagon_V6_vd0_128B :
4282 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">;
4283
4284 def int_hexagon_V6_vdealb :
4285 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">;
4286
4287 def int_hexagon_V6_vdealb_128B :
4288 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">;
4289
4290 def int_hexagon_V6_vdealb4w :
4291 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">;
4292
4293 def int_hexagon_V6_vdealb4w_128B :
4294 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;
4295
4296 def int_hexagon_V6_vdealh :
4297 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">;
4298
4299 def int_hexagon_V6_vdealh_128B :
4300 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">;
4301
4302 def int_hexagon_V6_vdealvdd :
4303 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">;
4304
4305 def int_hexagon_V6_vdealvdd_128B :
4306 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;
4307
4308 def int_hexagon_V6_vdelta :
4309 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">;
4310
4311 def int_hexagon_V6_vdelta_128B :
4312 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">;
4313
4314 def int_hexagon_V6_vdmpybus :
4315 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">;
4316
4317 def int_hexagon_V6_vdmpybus_128B :
4318 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;
4319
4320 def int_hexagon_V6_vdmpybus_acc :
4321 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;
4322
4323 def int_hexagon_V6_vdmpybus_acc_128B :
4324 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;
4325
4326 def int_hexagon_V6_vdmpybus_dv :
4327 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;
4328
4329 def int_hexagon_V6_vdmpybus_dv_128B :
4330 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;
4331
4332 def int_hexagon_V6_vdmpybus_dv_acc :
4333 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;
4334
4335 def int_hexagon_V6_vdmpybus_dv_acc_128B :
4336 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;
4337
4338 def int_hexagon_V6_vdmpyhb :
4339 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">;
4340
4341 def int_hexagon_V6_vdmpyhb_128B :
4342 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;
4343
4344 def int_hexagon_V6_vdmpyhb_acc :
4345 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;
4346
4347 def int_hexagon_V6_vdmpyhb_acc_128B :
4348 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;
4349
4350 def int_hexagon_V6_vdmpyhb_dv :
4351 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;
4352
4353 def int_hexagon_V6_vdmpyhb_dv_128B :
4354 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;
4355
4356 def int_hexagon_V6_vdmpyhb_dv_acc :
4357 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
4358
4359 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
4360 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
4361
4362 def int_hexagon_V6_vdmpyhisat :
4363 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">;
4364
4365 def int_hexagon_V6_vdmpyhisat_128B :
4366 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;
4367
4368 def int_hexagon_V6_vdmpyhisat_acc :
4369 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;
4370
4371 def int_hexagon_V6_vdmpyhisat_acc_128B :
4372 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;
4373
4374 def int_hexagon_V6_vdmpyhsat :
4375 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">;
4376
4377 def int_hexagon_V6_vdmpyhsat_128B :
4378 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;
4379
4380 def int_hexagon_V6_vdmpyhsat_acc :
4381 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;
4382
4383 def int_hexagon_V6_vdmpyhsat_acc_128B :
4384 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;
4385
4386 def int_hexagon_V6_vdmpyhsuisat :
4387 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
4388
4389 def int_hexagon_V6_vdmpyhsuisat_128B :
4390 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
4391
4392 def int_hexagon_V6_vdmpyhsuisat_acc :
4393 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;
4394
4395 def int_hexagon_V6_vdmpyhsuisat_acc_128B :
4396 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;
4397
4398 def int_hexagon_V6_vdmpyhsusat :
4399 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;
4400
4401 def int_hexagon_V6_vdmpyhsusat_128B :
4402 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;
4403
4404 def int_hexagon_V6_vdmpyhsusat_acc :
4405 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;
4406
4407 def int_hexagon_V6_vdmpyhsusat_acc_128B :
4408 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;
4409
4410 def int_hexagon_V6_vdmpyhvsat :
4411 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;
4412
4413 def int_hexagon_V6_vdmpyhvsat_128B :
4414 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;
4415
4416 def int_hexagon_V6_vdmpyhvsat_acc :
4417 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;
4418
4419 def int_hexagon_V6_vdmpyhvsat_acc_128B :
4420 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;
4421
4422 def int_hexagon_V6_vdsaduh :
4423 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">;
4424
4425 def int_hexagon_V6_vdsaduh_128B :
4426 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;
4427
4428 def int_hexagon_V6_vdsaduh_acc :
4429 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;
4430
4431 def int_hexagon_V6_vdsaduh_acc_128B :
4432 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;
4433
4434 def int_hexagon_V6_veqb :
4435 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">;
4436
4437 def int_hexagon_V6_veqb_128B :
4438 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">;
4439
4440 def int_hexagon_V6_veqb_and :
4441 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">;
4442
4443 def int_hexagon_V6_veqb_and_128B :
4444 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">;
4445
4446 def int_hexagon_V6_veqb_or :
4447 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;
4448
4449 def int_hexagon_V6_veqb_or_128B :
4450 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;
4451
4452 def int_hexagon_V6_veqb_xor :
4453 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">;
4454
4455 def int_hexagon_V6_veqb_xor_128B :
4456 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;
4457
4458 def int_hexagon_V6_veqh :
4459 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">;
4460
4461 def int_hexagon_V6_veqh_128B :
4462 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">;
4463
4464 def int_hexagon_V6_veqh_and :
4465 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;
4466
4467 def int_hexagon_V6_veqh_and_128B :
4468 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
4469
4470 def int_hexagon_V6_veqh_or :
4471 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">;
4472
4473 def int_hexagon_V6_veqh_or_128B :
4474 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">;
4475
4476 def int_hexagon_V6_veqh_xor :
4477 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">;
4478
4479 def int_hexagon_V6_veqh_xor_128B :
4480 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;
4481
4482 def int_hexagon_V6_veqw :
4483 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">;
4484
4485 def int_hexagon_V6_veqw_128B :
4486 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">;
4487
4488 def int_hexagon_V6_veqw_and :
4489 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">;
4490
4491 def int_hexagon_V6_veqw_and_128B :
4492 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">;
4493
4494 def int_hexagon_V6_veqw_or :
4495 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">;
4496
4497 def int_hexagon_V6_veqw_or_128B :
4498 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">;
4499
4500 def int_hexagon_V6_veqw_xor :
4501 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">;
4502
4503 def int_hexagon_V6_veqw_xor_128B :
4504 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;
4505
4506 def int_hexagon_V6_vgtb :
4507 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">;
4508
4509 def int_hexagon_V6_vgtb_128B :
4510 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">;
4511
4512 def int_hexagon_V6_vgtb_and :
4513 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">;
4514
4515 def int_hexagon_V6_vgtb_and_128B :
4516 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;
4517
4518 def int_hexagon_V6_vgtb_or :
4519 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">;
4520
4521 def int_hexagon_V6_vgtb_or_128B :
4522 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;
4523
4524 def int_hexagon_V6_vgtb_xor :
4525 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">;
4526
4527 def int_hexagon_V6_vgtb_xor_128B :
4528 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;
4529
4530 def int_hexagon_V6_vgth :
4531 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">;
4532
4533 def int_hexagon_V6_vgth_128B :
4534 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">;
4535
4536 def int_hexagon_V6_vgth_and :
4537 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">;
4538
4539 def int_hexagon_V6_vgth_and_128B :
4540 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">;
4541
4542 def int_hexagon_V6_vgth_or :
4543 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">;
4544
4545 def int_hexagon_V6_vgth_or_128B :
4546 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">;
4547
4548 def int_hexagon_V6_vgth_xor :
4549 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">;
4550
4551 def int_hexagon_V6_vgth_xor_128B :
4552 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;
4553
4554 def int_hexagon_V6_vgtub :
4555 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">;
4556
4557 def int_hexagon_V6_vgtub_128B :
4558 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">;
4559
4560 def int_hexagon_V6_vgtub_and :
4561 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">;
4562
4563 def int_hexagon_V6_vgtub_and_128B :
4564 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;
4565
4566 def int_hexagon_V6_vgtub_or :
4567 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">;
4568
4569 def int_hexagon_V6_vgtub_or_128B :
4570 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;
4571
4572 def int_hexagon_V6_vgtub_xor :
4573 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">;
4574
4575 def int_hexagon_V6_vgtub_xor_128B :
4576 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;
4577
4578 def int_hexagon_V6_vgtuh :
4579 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">;
4580
4581 def int_hexagon_V6_vgtuh_128B :
4582 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">;
4583
4584 def int_hexagon_V6_vgtuh_and :
4585 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">;
4586
4587 def int_hexagon_V6_vgtuh_and_128B :
4588 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;
4589
4590 def int_hexagon_V6_vgtuh_or :
4591 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">;
4592
4593 def int_hexagon_V6_vgtuh_or_128B :
4594 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;
4595
4596 def int_hexagon_V6_vgtuh_xor :
4597 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">;
4598
4599 def int_hexagon_V6_vgtuh_xor_128B :
4600 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;
4601
4602 def int_hexagon_V6_vgtuw :
4603 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">;
4604
4605 def int_hexagon_V6_vgtuw_128B :
4606 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">;
4607
4608 def int_hexagon_V6_vgtuw_and :
4609 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">;
4610
4611 def int_hexagon_V6_vgtuw_and_128B :
4612 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;
4613
4614 def int_hexagon_V6_vgtuw_or :
4615 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">;
4616
4617 def int_hexagon_V6_vgtuw_or_128B :
4618 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;
4619
4620 def int_hexagon_V6_vgtuw_xor :
4621 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">;
4622
4623 def int_hexagon_V6_vgtuw_xor_128B :
4624 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;
4625
4626 def int_hexagon_V6_vgtw :
4627 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">;
4628
4629 def int_hexagon_V6_vgtw_128B :
4630 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">;
4631
4632 def int_hexagon_V6_vgtw_and :
4633 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">;
4634
4635 def int_hexagon_V6_vgtw_and_128B :
4636 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;
4637
4638 def int_hexagon_V6_vgtw_or :
4639 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">;
4640
4641 def int_hexagon_V6_vgtw_or_128B :
4642 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;
4643
4644 def int_hexagon_V6_vgtw_xor :
4645 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">;
4646
4647 def int_hexagon_V6_vgtw_xor_128B :
4648 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;
4649
4650 def int_hexagon_V6_vinsertwr :
4651 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">;
4652
4653 def int_hexagon_V6_vinsertwr_128B :
4654 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;
4655
4656 def int_hexagon_V6_vlalignb :
4657 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">;
4658
4659 def int_hexagon_V6_vlalignb_128B :
4660 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">;
4661
4662 def int_hexagon_V6_vlalignbi :
4663 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
4664
4665 def int_hexagon_V6_vlalignbi_128B :
4666 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
4667
4668 def int_hexagon_V6_vlsrh :
4669 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">;
4670
4671 def int_hexagon_V6_vlsrh_128B :
4672 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">;
4673
4674 def int_hexagon_V6_vlsrhv :
4675 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">;
4676
4677 def int_hexagon_V6_vlsrhv_128B :
4678 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;
4679
4680 def int_hexagon_V6_vlsrw :
4681 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">;
4682
4683 def int_hexagon_V6_vlsrw_128B :
4684 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">;
4685
4686 def int_hexagon_V6_vlsrwv :
4687 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">;
4688
4689 def int_hexagon_V6_vlsrwv_128B :
4690 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;
4691
4692 def int_hexagon_V6_vlutvvb :
4693 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">;
4694
4695 def int_hexagon_V6_vlutvvb_128B :
4696 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;
4697
4698 def int_hexagon_V6_vlutvvb_oracc :
4699 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;
4700
4701 def int_hexagon_V6_vlutvvb_oracc_128B :
4702 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;
4703
4704 def int_hexagon_V6_vlutvwh :
4705 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">;
4706
4707 def int_hexagon_V6_vlutvwh_128B :
4708 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;
4709
4710 def int_hexagon_V6_vlutvwh_oracc :
4711 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
4712
4713 def int_hexagon_V6_vlutvwh_oracc_128B :
4714 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
4715
4716 def int_hexagon_V6_vmaxh :
4717 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">;
4718
4719 def int_hexagon_V6_vmaxh_128B :
4720 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">;
4721
4722 def int_hexagon_V6_vmaxub :
4723 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">;
4724
4725 def int_hexagon_V6_vmaxub_128B :
4726 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">;
4727
4728 def int_hexagon_V6_vmaxuh :
4729 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">;
4730
4731 def int_hexagon_V6_vmaxuh_128B :
4732 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;
4733
4734 def int_hexagon_V6_vmaxw :
4735 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">;
4736
4737 def int_hexagon_V6_vmaxw_128B :
4738 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">;
4739
4740 def int_hexagon_V6_vminh :
4741 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">;
4742
4743 def int_hexagon_V6_vminh_128B :
4744 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">;
4745
4746 def int_hexagon_V6_vminub :
4747 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">;
4748
4749 def int_hexagon_V6_vminub_128B :
4750 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">;
4751
4752 def int_hexagon_V6_vminuh :
4753 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">;
4754
4755 def int_hexagon_V6_vminuh_128B :
4756 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">;
4757
4758 def int_hexagon_V6_vminw :
4759 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;
4760
4761 def int_hexagon_V6_vminw_128B :
4762 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;
4763
4764 def int_hexagon_V6_vmpabus :
4765 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">;
4766
4767 def int_hexagon_V6_vmpabus_128B :
4768 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">;
4769
4770 def int_hexagon_V6_vmpabus_acc :
4771 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">;
4772
4773 def int_hexagon_V6_vmpabus_acc_128B :
4774 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;
4775
4776 def int_hexagon_V6_vmpabusv :
4777 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">;
4778
4779 def int_hexagon_V6_vmpabusv_128B :
4780 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;
4781
4782 def int_hexagon_V6_vmpabuuv :
4783 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">;
4784
4785 def int_hexagon_V6_vmpabuuv_128B :
4786 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;
4787
4788 def int_hexagon_V6_vmpahb :
4789 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">;
4790
4791 def int_hexagon_V6_vmpahb_128B :
4792 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">;
4793
4794 def int_hexagon_V6_vmpahb_acc :
4795 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">;
4796
4797 def int_hexagon_V6_vmpahb_acc_128B :
4798 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;
4799
4800 def int_hexagon_V6_vmpybus :
4801 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">;
4802
4803 def int_hexagon_V6_vmpybus_128B :
4804 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">;
4805
4806 def int_hexagon_V6_vmpybus_acc :
4807 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">;
4808
4809 def int_hexagon_V6_vmpybus_acc_128B :
4810 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;
4811
4812 def int_hexagon_V6_vmpybusv :
4813 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">;
4814
4815 def int_hexagon_V6_vmpybusv_128B :
4816 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;
4817
4818 def int_hexagon_V6_vmpybusv_acc :
4819 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;
4820
4821 def int_hexagon_V6_vmpybusv_acc_128B :
4822 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;
4823
4824 def int_hexagon_V6_vmpybv :
4825 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">;
4826
4827 def int_hexagon_V6_vmpybv_128B :
4828 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">;
4829
4830 def int_hexagon_V6_vmpybv_acc :
4831 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
4832
4833 def int_hexagon_V6_vmpybv_acc_128B :
4834 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
4835
4836 def int_hexagon_V6_vmpyewuh :
4837 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">;
4838
4839 def int_hexagon_V6_vmpyewuh_128B :
4840 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;
4841
4842 def int_hexagon_V6_vmpyh :
4843 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">;
4844
4845 def int_hexagon_V6_vmpyh_128B :
4846 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">;
4847
4848 def int_hexagon_V6_vmpyhsat_acc :
4849 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;
4850
4851 def int_hexagon_V6_vmpyhsat_acc_128B :
4852 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;
4853
4854 def int_hexagon_V6_vmpyhsrs :
4855 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">;
4856
4857 def int_hexagon_V6_vmpyhsrs_128B :
4858 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;
4859
4860 def int_hexagon_V6_vmpyhss :
4861 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">;
4862
4863 def int_hexagon_V6_vmpyhss_128B :
4864 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;
4865
4866 def int_hexagon_V6_vmpyhus :
4867 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">;
4868
4869 def int_hexagon_V6_vmpyhus_128B :
4870 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;
4871
4872 def int_hexagon_V6_vmpyhus_acc :
4873 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;
4874
4875 def int_hexagon_V6_vmpyhus_acc_128B :
4876 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;
4877
4878 def int_hexagon_V6_vmpyhv :
4879 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">;
4880
4881 def int_hexagon_V6_vmpyhv_128B :
4882 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;
4883
4884 def int_hexagon_V6_vmpyhv_acc :
4885 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;
4886
4887 def int_hexagon_V6_vmpyhv_acc_128B :
4888 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;
4889
4890 def int_hexagon_V6_vmpyhvsrs :
4891 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;
4892
4893 def int_hexagon_V6_vmpyhvsrs_128B :
4894 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;
4895
4896 def int_hexagon_V6_vmpyieoh :
4897 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">;
4898
4899 def int_hexagon_V6_vmpyieoh_128B :
4900 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;
4901
4902 def int_hexagon_V6_vmpyiewh_acc :
4903 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;
4904
4905 def int_hexagon_V6_vmpyiewh_acc_128B :
4906 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;
4907
4908 def int_hexagon_V6_vmpyiewuh :
4909 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">;
4910
4911 def int_hexagon_V6_vmpyiewuh_128B :
4912 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;
4913
4914 def int_hexagon_V6_vmpyiewuh_acc :
4915 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;
4916
4917 def int_hexagon_V6_vmpyiewuh_acc_128B :
4918 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;
4919
4920 def int_hexagon_V6_vmpyih :
4921 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">;
4922
4923 def int_hexagon_V6_vmpyih_128B :
4924 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">;
4925
4926 def int_hexagon_V6_vmpyih_acc :
4927 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">;
4928
4929 def int_hexagon_V6_vmpyih_acc_128B :
4930 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;
4931
4932 def int_hexagon_V6_vmpyihb :
4933 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">;
4934
4935 def int_hexagon_V6_vmpyihb_128B :
4936 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;
4937
4938 def int_hexagon_V6_vmpyihb_acc :
4939 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;
4940
4941 def int_hexagon_V6_vmpyihb_acc_128B :
4942 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;
4943
4944 def int_hexagon_V6_vmpyiowh :
4945 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">;
4946
4947 def int_hexagon_V6_vmpyiowh_128B :
4948 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;
4949
4950 def int_hexagon_V6_vmpyiwb :
4951 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">;
4952
4953 def int_hexagon_V6_vmpyiwb_128B :
4954 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;
4955
4956 def int_hexagon_V6_vmpyiwb_acc :
4957 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;
4958
4959 def int_hexagon_V6_vmpyiwb_acc_128B :
4960 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;
4961
4962 def int_hexagon_V6_vmpyiwh :
4963 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">;
4964
4965 def int_hexagon_V6_vmpyiwh_128B :
4966 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;
4967
4968 def int_hexagon_V6_vmpyiwh_acc :
4969 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;
4970
4971 def int_hexagon_V6_vmpyiwh_acc_128B :
4972 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;
4973
4974 def int_hexagon_V6_vmpyowh :
4975 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">;
4976
4977 def int_hexagon_V6_vmpyowh_128B :
4978 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;
4979
4980 def int_hexagon_V6_vmpyowh_rnd :
4981 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;
4982
4983 def int_hexagon_V6_vmpyowh_rnd_128B :
4984 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;
4985
4986 def int_hexagon_V6_vmpyowh_rnd_sacc :
4987 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;
4988
4989 def int_hexagon_V6_vmpyowh_rnd_sacc_128B :
4990 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;
4991
4992 def int_hexagon_V6_vmpyowh_sacc :
4993 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;
4994
4995 def int_hexagon_V6_vmpyowh_sacc_128B :
4996 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;
4997
4998 def int_hexagon_V6_vmpyub :
4999 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">;
5000
5001 def int_hexagon_V6_vmpyub_128B :
5002 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">;
5003
5004 def int_hexagon_V6_vmpyub_acc :
5005 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">;
5006
5007 def int_hexagon_V6_vmpyub_acc_128B :
5008 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;
5009
5010 def int_hexagon_V6_vmpyubv :
5011 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">;
5012
5013 def int_hexagon_V6_vmpyubv_128B :
5014 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;
5015
5016 def int_hexagon_V6_vmpyubv_acc :
5017 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;
5018
5019 def int_hexagon_V6_vmpyubv_acc_128B :
5020 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;
5021
5022 def int_hexagon_V6_vmpyuh :
5023 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">;
5024
5025 def int_hexagon_V6_vmpyuh_128B :
5026 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;
5027
5028 def int_hexagon_V6_vmpyuh_acc :
5029 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;
5030
5031 def int_hexagon_V6_vmpyuh_acc_128B :
5032 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;
5033
5034 def int_hexagon_V6_vmpyuhv :
5035 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">;
5036
5037 def int_hexagon_V6_vmpyuhv_128B :
5038 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;
5039
5040 def int_hexagon_V6_vmpyuhv_acc :
5041 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;
5042
5043 def int_hexagon_V6_vmpyuhv_acc_128B :
5044 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;
5045
5046 def int_hexagon_V6_vmux :
5047 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">;
5048
5049 def int_hexagon_V6_vmux_128B :
5050 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">;
5051
5052 def int_hexagon_V6_vnavgh :
5053 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">;
5054
5055 def int_hexagon_V6_vnavgh_128B :
5056 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">;
5057
5058 def int_hexagon_V6_vnavgub :
5059 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">;
5060
5061 def int_hexagon_V6_vnavgub_128B :
5062 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">;
5063
5064 def int_hexagon_V6_vnavgw :
5065 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;
5066
5067 def int_hexagon_V6_vnavgw_128B :
5068 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
5069
5070 def int_hexagon_V6_vnormamth :
5071 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">;
5072
5073 def int_hexagon_V6_vnormamth_128B :
5074 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">;
5075
5076 def int_hexagon_V6_vnormamtw :
5077 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">;
5078
5079 def int_hexagon_V6_vnormamtw_128B :
5080 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;
5081
5082 def int_hexagon_V6_vnot :
5083 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">;
5084
5085 def int_hexagon_V6_vnot_128B :
5086 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">;
5087
5088 def int_hexagon_V6_vor :
5089 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">;
5090
5091 def int_hexagon_V6_vor_128B :
5092 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">;
5093
5094 def int_hexagon_V6_vpackeb :
5095 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">;
5096
5097 def int_hexagon_V6_vpackeb_128B :
5098 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">;
5099
5100 def int_hexagon_V6_vpackeh :
5101 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">;
5102
5103 def int_hexagon_V6_vpackeh_128B :
5104 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">;
5105
5106 def int_hexagon_V6_vpackhb_sat :
5107 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">;
5108
5109 def int_hexagon_V6_vpackhb_sat_128B :
5110 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;
5111
5112 def int_hexagon_V6_vpackhub_sat :
5113 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">;
5114
5115 def int_hexagon_V6_vpackhub_sat_128B :
5116 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;
5117
5118 def int_hexagon_V6_vpackob :
5119 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">;
5120
5121 def int_hexagon_V6_vpackob_128B :
5122 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">;
5123
5124 def int_hexagon_V6_vpackoh :
5125 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">;
5126
5127 def int_hexagon_V6_vpackoh_128B :
5128 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">;
5129
5130 def int_hexagon_V6_vpackwh_sat :
5131 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">;
5132
5133 def int_hexagon_V6_vpackwh_sat_128B :
5134 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;
5135
5136 def int_hexagon_V6_vpackwuh_sat :
5137 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;
5138
5139 def int_hexagon_V6_vpackwuh_sat_128B :
5140 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;
5141
5142 def int_hexagon_V6_vpopcounth :
5143 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">;
5144
5145 def int_hexagon_V6_vpopcounth_128B :
5146 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;
5147
5148 def int_hexagon_V6_vrdelta :
5149 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">;
5150
5151 def int_hexagon_V6_vrdelta_128B :
5152 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">;
5153
5154 def int_hexagon_V6_vrmpybus :
5155 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">;
5156
5157 def int_hexagon_V6_vrmpybus_128B :
5158 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;
5159
5160 def int_hexagon_V6_vrmpybus_acc :
5161 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;
5162
5163 def int_hexagon_V6_vrmpybus_acc_128B :
5164 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;
5165
5166 def int_hexagon_V6_vrmpybusi :
5167 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5168
5169 def int_hexagon_V6_vrmpybusi_128B :
5170 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5171
5172 def int_hexagon_V6_vrmpybusi_acc :
5173 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5174
5175 def int_hexagon_V6_vrmpybusi_acc_128B :
5176 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5177
5178 def int_hexagon_V6_vrmpybusv :
5179 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">;
5180
5181 def int_hexagon_V6_vrmpybusv_128B :
5182 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;
5183
5184 def int_hexagon_V6_vrmpybusv_acc :
5185 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;
5186
5187 def int_hexagon_V6_vrmpybusv_acc_128B :
5188 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;
5189
5190 def int_hexagon_V6_vrmpybv :
5191 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">;
5192
5193 def int_hexagon_V6_vrmpybv_128B :
5194 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;
5195
5196 def int_hexagon_V6_vrmpybv_acc :
5197 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;
5198
5199 def int_hexagon_V6_vrmpybv_acc_128B :
5200 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;
5201
5202 def int_hexagon_V6_vrmpyub :
5203 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">;
5204
5205 def int_hexagon_V6_vrmpyub_128B :
5206 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;
5207
5208 def int_hexagon_V6_vrmpyub_acc :
5209 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;
5210
5211 def int_hexagon_V6_vrmpyub_acc_128B :
5212 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;
5213
5214 def int_hexagon_V6_vrmpyubi :
5215 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5216
5217 def int_hexagon_V6_vrmpyubi_128B :
5218 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5219
5220 def int_hexagon_V6_vrmpyubi_acc :
5221 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5222
5223 def int_hexagon_V6_vrmpyubi_acc_128B :
5224 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5225
5226 def int_hexagon_V6_vrmpyubv :
5227 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">;
5228
5229 def int_hexagon_V6_vrmpyubv_128B :
5230 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;
5231
5232 def int_hexagon_V6_vrmpyubv_acc :
5233 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;
5234
5235 def int_hexagon_V6_vrmpyubv_acc_128B :
5236 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;
5237
5238 def int_hexagon_V6_vror :
5239 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">;
5240
5241 def int_hexagon_V6_vror_128B :
5242 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">;
5243
5244 def int_hexagon_V6_vroundhb :
5245 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">;
5246
5247 def int_hexagon_V6_vroundhb_128B :
5248 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">;
5249
5250 def int_hexagon_V6_vroundhub :
5251 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">;
5252
5253 def int_hexagon_V6_vroundhub_128B :
5254 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">;
5255
5256 def int_hexagon_V6_vroundwh :
5257 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">;
5258
5259 def int_hexagon_V6_vroundwh_128B :
5260 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">;
5261
5262 def int_hexagon_V6_vroundwuh :
5263 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">;
5264
5265 def int_hexagon_V6_vroundwuh_128B :
5266 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;
5267
5268 def int_hexagon_V6_vrsadubi :
5269 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5270
5271 def int_hexagon_V6_vrsadubi_128B :
5272 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5273
5274 def int_hexagon_V6_vrsadubi_acc :
5275 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5276
5277 def int_hexagon_V6_vrsadubi_acc_128B :
5278 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5279
5280 def int_hexagon_V6_vsathub :
5281 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">;
5282
5283 def int_hexagon_V6_vsathub_128B :
5284 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">;
5285
5286 def int_hexagon_V6_vsatwh :
5287 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;
5288
5289 def int_hexagon_V6_vsatwh_128B :
5290 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
5291
5292 def int_hexagon_V6_vsb :
5293 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">;
5294
5295 def int_hexagon_V6_vsb_128B :
5296 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">;
5297
5298 def int_hexagon_V6_vsh :
5299 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">;
5300
5301 def int_hexagon_V6_vsh_128B :
5302 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">;
5303
5304 def int_hexagon_V6_vshufeh :
5305 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">;
5306
5307 def int_hexagon_V6_vshufeh_128B :
5308 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">;
5309
5310 def int_hexagon_V6_vshuffb :
5311 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">;
5312
5313 def int_hexagon_V6_vshuffb_128B :
5314 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">;
5315
5316 def int_hexagon_V6_vshuffeb :
5317 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">;
5318
5319 def int_hexagon_V6_vshuffeb_128B :
5320 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;
5321
5322 def int_hexagon_V6_vshuffh :
5323 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">;
5324
5325 def int_hexagon_V6_vshuffh_128B :
5326 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">;
5327
5328 def int_hexagon_V6_vshuffob :
5329 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">;
5330
5331 def int_hexagon_V6_vshuffob_128B :
5332 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">;
5333
5334 def int_hexagon_V6_vshuffvdd :
5335 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">;
5336
5337 def int_hexagon_V6_vshuffvdd_128B :
5338 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;
5339
5340 def int_hexagon_V6_vshufoeb :
5341 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">;
5342
5343 def int_hexagon_V6_vshufoeb_128B :
5344 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;
5345
5346 def int_hexagon_V6_vshufoeh :
5347 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">;
5348
5349 def int_hexagon_V6_vshufoeh_128B :
5350 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;
5351
5352 def int_hexagon_V6_vshufoh :
5353 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;
5354
5355 def int_hexagon_V6_vshufoh_128B :
5356 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
5357
5358 def int_hexagon_V6_vsubb :
5359 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">;
5360
5361 def int_hexagon_V6_vsubb_128B :
5362 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">;
5363
5364 def int_hexagon_V6_vsubb_dv :
5365 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">;
5366
5367 def int_hexagon_V6_vsubb_dv_128B :
5368 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;
5369
5370 def int_hexagon_V6_vsubbnq :
5371 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">;
5372
5373 def int_hexagon_V6_vsubbnq_128B :
5374 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;
5375
5376 def int_hexagon_V6_vsubbq :
5377 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">;
5378
5379 def int_hexagon_V6_vsubbq_128B :
5380 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">;
5381
5382 def int_hexagon_V6_vsubh :
5383 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;
5384
5385 def int_hexagon_V6_vsubh_128B :
5386 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;
5387
5388 def int_hexagon_V6_vsubh_dv :
5389 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">;
5390
5391 def int_hexagon_V6_vsubh_dv_128B :
5392 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;
5393
5394 def int_hexagon_V6_vsubhnq :
5395 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">;
5396
5397 def int_hexagon_V6_vsubhnq_128B :
5398 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;
5399
5400 def int_hexagon_V6_vsubhq :
5401 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">;
5402
5403 def int_hexagon_V6_vsubhq_128B :
5404 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">;
5405
5406 def int_hexagon_V6_vsubhsat :
5407 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;
5408
5409 def int_hexagon_V6_vsubhsat_128B :
5410 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
5411
5412 def int_hexagon_V6_vsubhsat_dv :
5413 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;
5414
5415 def int_hexagon_V6_vsubhsat_dv_128B :
5416 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;
5417
5418 def int_hexagon_V6_vsubhw :
5419 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">;
5420
5421 def int_hexagon_V6_vsubhw_128B :
5422 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">;
5423
5424 def int_hexagon_V6_vsububh :
5425 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">;
5426
5427 def int_hexagon_V6_vsububh_128B :
5428 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">;
5429
5430 def int_hexagon_V6_vsububsat :
5431 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">;
5432
5433 def int_hexagon_V6_vsububsat_128B :
5434 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">;
5435
5436 def int_hexagon_V6_vsububsat_dv :
5437 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">;
5438
5439 def int_hexagon_V6_vsububsat_dv_128B :
5440 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;
5441
5442 def int_hexagon_V6_vsubuhsat :
5443 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">;
5444
5445 def int_hexagon_V6_vsubuhsat_128B :
5446 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;
5447
5448 def int_hexagon_V6_vsubuhsat_dv :
5449 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;
5450
5451 def int_hexagon_V6_vsubuhsat_dv_128B :
5452 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;
5453
5454 def int_hexagon_V6_vsubuhw :
5455 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;
5456
5457 def int_hexagon_V6_vsubuhw_128B :
5458 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
5459
5460 def int_hexagon_V6_vsubw :
5461 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">;
5462
5463 def int_hexagon_V6_vsubw_128B :
5464 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">;
5465
5466 def int_hexagon_V6_vsubw_dv :
5467 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">;
5468
5469 def int_hexagon_V6_vsubw_dv_128B :
5470 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;
5471
5472 def int_hexagon_V6_vsubwnq :
5473 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">;
5474
5475 def int_hexagon_V6_vsubwnq_128B :
5476 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;
5477
5478 def int_hexagon_V6_vsubwq :
5479 Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">;
5480
5481 def int_hexagon_V6_vsubwq_128B :
5482 Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">;
5483
5484 def int_hexagon_V6_vsubwsat :
5485 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">;
5486
5487 def int_hexagon_V6_vsubwsat_128B :
5488 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;
5489
5490 def int_hexagon_V6_vsubwsat_dv :
5491 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;
5492
5493 def int_hexagon_V6_vsubwsat_dv_128B :
5494 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;
5495
5496 def int_hexagon_V6_vswap :
5497 Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">;
5498
5499 def int_hexagon_V6_vswap_128B :
5500 Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">;
5501
5502 def int_hexagon_V6_vtmpyb :
5503 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">;
5504
5505 def int_hexagon_V6_vtmpyb_128B :
5506 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;
5507
5508 def int_hexagon_V6_vtmpyb_acc :
5509 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;
5510
5511 def int_hexagon_V6_vtmpyb_acc_128B :
5512 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;
5513
5514 def int_hexagon_V6_vtmpybus :
5515 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">;
5516
5517 def int_hexagon_V6_vtmpybus_128B :
5518 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;
5519
5520 def int_hexagon_V6_vtmpybus_acc :
5521 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;
5522
5523 def int_hexagon_V6_vtmpybus_acc_128B :
5524 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;
5525
5526 def int_hexagon_V6_vtmpyhb :
5527 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">;
5528
5529 def int_hexagon_V6_vtmpyhb_128B :
5530 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;
5531
5532 def int_hexagon_V6_vtmpyhb_acc :
5533 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;
5534
5535 def int_hexagon_V6_vtmpyhb_acc_128B :
5536 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;
5537
5538 def int_hexagon_V6_vunpackb :
5539 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">;
5540
5541 def int_hexagon_V6_vunpackb_128B :
5542 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">;
5543
5544 def int_hexagon_V6_vunpackh :
5545 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">;
5546
5547 def int_hexagon_V6_vunpackh_128B :
5548 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">;
5549
5550 def int_hexagon_V6_vunpackob :
5551 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">;
5552
5553 def int_hexagon_V6_vunpackob_128B :
5554 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">;
5555
5556 def int_hexagon_V6_vunpackoh :
5557 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">;
5558
5559 def int_hexagon_V6_vunpackoh_128B :
5560 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;
5561
5562 def int_hexagon_V6_vunpackub :
5563 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">;
5564
5565 def int_hexagon_V6_vunpackub_128B :
5566 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">;
5567
5568 def int_hexagon_V6_vunpackuh :
5569 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">;
5570
5571 def int_hexagon_V6_vunpackuh_128B :
5572 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;
5573
5574 def int_hexagon_V6_vxor :
5575 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">;
5576
5577 def int_hexagon_V6_vxor_128B :
5578 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">;
5579
5580 def int_hexagon_V6_vzb :
5581 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">;
5582
5583 def int_hexagon_V6_vzb_128B :
5584 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">;
5585
5586 def int_hexagon_V6_vzh :
5587 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">;
5588
5589 def int_hexagon_V6_vzh_128B :
5590 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">;
5591
5592 // V62 HVX Instructions.
5593
5594 def int_hexagon_V6_lvsplatb :
5595 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">;
5596
5597 def int_hexagon_V6_lvsplatb_128B :
5598 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;
5599
5600 def int_hexagon_V6_lvsplath :
5601 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">;
5602
5603 def int_hexagon_V6_lvsplath_128B :
5604 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">;
5605
5606 def int_hexagon_V6_pred_scalar2v2 :
5607 Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;
5608
5609 def int_hexagon_V6_pred_scalar2v2_128B :
5610 Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;
5611
5612 def int_hexagon_V6_shuffeqh :
5613 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqh">;
5614
5615 def int_hexagon_V6_shuffeqh_128B :
5616 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;
5617
5618 def int_hexagon_V6_shuffeqw :
5619 Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqw">;
5620
5621 def int_hexagon_V6_shuffeqw_128B :
5622 Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;
5623
5624 def int_hexagon_V6_vaddbsat :
5625 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">;
5626
5627 def int_hexagon_V6_vaddbsat_128B :
5628 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;
5629
5630 def int_hexagon_V6_vaddbsat_dv :
5631 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;
5632
5633 def int_hexagon_V6_vaddbsat_dv_128B :
5634 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;
5635
5636 def int_hexagon_V6_vaddcarry :
5637 Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic;
5638
5639 def int_hexagon_V6_vaddcarry_128B :
5640 Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B;
5641
5642 def int_hexagon_V6_vaddclbh :
5643 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">;
5644
5645 def int_hexagon_V6_vaddclbh_128B :
5646 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;
5647
5648 def int_hexagon_V6_vaddclbw :
5649 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">;
5650
5651 def int_hexagon_V6_vaddclbw_128B :
5652 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;
5653
5654 def int_hexagon_V6_vaddhw_acc :
5655 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">;
5656
5657 def int_hexagon_V6_vaddhw_acc_128B :
5658 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;
5659
5660 def int_hexagon_V6_vaddubh_acc :
5661 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">;
5662
5663 def int_hexagon_V6_vaddubh_acc_128B :
5664 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;
5665
5666 def int_hexagon_V6_vaddububb_sat :
5667 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
5668
5669 def int_hexagon_V6_vaddububb_sat_128B :
5670 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
5671
5672 def int_hexagon_V6_vadduhw_acc :
5673 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">;
5674
5675 def int_hexagon_V6_vadduhw_acc_128B :
5676 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;
5677
5678 def int_hexagon_V6_vadduwsat :
5679 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">;
5680
5681 def int_hexagon_V6_vadduwsat_128B :
5682 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;
5683
5684 def int_hexagon_V6_vadduwsat_dv :
5685 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;
5686
5687 def int_hexagon_V6_vadduwsat_dv_128B :
5688 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;
5689
5690 def int_hexagon_V6_vandnqrt :
5691 Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">;
5692
5693 def int_hexagon_V6_vandnqrt_128B :
5694 Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;
5695
5696 def int_hexagon_V6_vandnqrt_acc :
5697 Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;
5698
5699 def int_hexagon_V6_vandnqrt_acc_128B :
5700 Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;
5701
5702 def int_hexagon_V6_vandvnqv :
5703 Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">;
5704
5705 def int_hexagon_V6_vandvnqv_128B :
5706 Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;
5707
5708 def int_hexagon_V6_vandvqv :
5709 Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">;
5710
5711 def int_hexagon_V6_vandvqv_128B :
5712 Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">;
5713
5714 def int_hexagon_V6_vasrhbsat :
5715 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">;
5716
5717 def int_hexagon_V6_vasrhbsat_128B :
5718 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;
5719
5720 def int_hexagon_V6_vasruwuhrndsat :
5721 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;
5722
5723 def int_hexagon_V6_vasruwuhrndsat_128B :
5724 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;
5725
5726 def int_hexagon_V6_vasrwuhrndsat :
5727 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
5728
5729 def int_hexagon_V6_vasrwuhrndsat_128B :
5730 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
5731
5732 def int_hexagon_V6_vlsrb :
5733 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;
5734
5735 def int_hexagon_V6_vlsrb_128B :
5736 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
5737
5738 def int_hexagon_V6_vlutvvb_nm :
5739 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;
5740
5741 def int_hexagon_V6_vlutvvb_nm_128B :
5742 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;
5743
5744 def int_hexagon_V6_vlutvvb_oracci :
5745 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5746
5747 def int_hexagon_V6_vlutvvb_oracci_128B :
5748 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5749
5750 def int_hexagon_V6_vlutvvbi :
5751 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5752
5753 def int_hexagon_V6_vlutvvbi_128B :
5754 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5755
5756 def int_hexagon_V6_vlutvwh_nm :
5757 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;
5758
5759 def int_hexagon_V6_vlutvwh_nm_128B :
5760 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
5761
5762 def int_hexagon_V6_vlutvwh_oracci :
5763 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5764
5765 def int_hexagon_V6_vlutvwh_oracci_128B :
5766 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
5767
5768 def int_hexagon_V6_vlutvwhi :
5769 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5770
5771 def int_hexagon_V6_vlutvwhi_128B :
5772 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
5773
5774 def int_hexagon_V6_vmaxb :
5775 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">;
5776
5777 def int_hexagon_V6_vmaxb_128B :
5778 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">;
5779
5780 def int_hexagon_V6_vminb :
5781 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">;
5782
5783 def int_hexagon_V6_vminb_128B :
5784 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">;
5785
5786 def int_hexagon_V6_vmpauhb :
5787 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">;
5788
5789 def int_hexagon_V6_vmpauhb_128B :
5790 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;
5791
5792 def int_hexagon_V6_vmpauhb_acc :
5793 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;
5794
5795 def int_hexagon_V6_vmpauhb_acc_128B :
5796 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;
5797
5798 def int_hexagon_V6_vmpyewuh_64 :
5799 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;
5800
5801 def int_hexagon_V6_vmpyewuh_64_128B :
5802 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;
5803
5804 def int_hexagon_V6_vmpyiwub :
5805 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">;
5806
5807 def int_hexagon_V6_vmpyiwub_128B :
5808 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;
5809
5810 def int_hexagon_V6_vmpyiwub_acc :
5811 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;
5812
5813 def int_hexagon_V6_vmpyiwub_acc_128B :
5814 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;
5815
5816 def int_hexagon_V6_vmpyowh_64_acc :
5817 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;
5818
5819 def int_hexagon_V6_vmpyowh_64_acc_128B :
5820 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;
5821
5822 def int_hexagon_V6_vrounduhub :
5823 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">;
5824
5825 def int_hexagon_V6_vrounduhub_128B :
5826 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;
5827
5828 def int_hexagon_V6_vrounduwuh :
5829 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">;
5830
5831 def int_hexagon_V6_vrounduwuh_128B :
5832 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;
5833
5834 def int_hexagon_V6_vsatuwuh :
5835 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">;
5836
5837 def int_hexagon_V6_vsatuwuh_128B :
5838 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;
5839
5840 def int_hexagon_V6_vsubbsat :
5841 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;
5842
5843 def int_hexagon_V6_vsubbsat_128B :
5844 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
5845
5846 def int_hexagon_V6_vsubbsat_dv :
5847 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
5848
5849 def int_hexagon_V6_vsubbsat_dv_128B :
5850 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
5851
5852 def int_hexagon_V6_vsubcarry :
5853 Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic;
5854
5855 def int_hexagon_V6_vsubcarry_128B :
5856 Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B;
5857
5858 def int_hexagon_V6_vsubububb_sat :
5859 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">;
5860
5861 def int_hexagon_V6_vsubububb_sat_128B :
5862 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;
5863
5864 def int_hexagon_V6_vsubuwsat :
5865 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;
5866
5867 def int_hexagon_V6_vsubuwsat_128B :
5868 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
5869
5870 def int_hexagon_V6_vsubuwsat_dv :
5871 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
5872
5873 def int_hexagon_V6_vsubuwsat_dv_128B :
5874 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
5875
5876 // V65 HVX Instructions.
5877
5878 def int_hexagon_V6_vabsb :
5879 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">;
5880
5881 def int_hexagon_V6_vabsb_128B :
5882 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">;
5883
5884 def int_hexagon_V6_vabsb_sat :
5885 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">;
5886
5887 def int_hexagon_V6_vabsb_sat_128B :
5888 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
5889
5890 def int_hexagon_V6_vaslh_acc :
5891 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">;
5892
5893 def int_hexagon_V6_vaslh_acc_128B :
5894 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
5895
5896 def int_hexagon_V6_vasrh_acc :
5897 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">;
5898
5899 def int_hexagon_V6_vasrh_acc_128B :
5900 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
5901
5902 def int_hexagon_V6_vasruhubrndsat :
5903 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
5904
5905 def int_hexagon_V6_vasruhubrndsat_128B :
5906 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
5907
5908 def int_hexagon_V6_vasruhubsat :
5909 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">;
5910
5911 def int_hexagon_V6_vasruhubsat_128B :
5912 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
5913
5914 def int_hexagon_V6_vasruwuhsat :
5915 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
5916
5917 def int_hexagon_V6_vasruwuhsat_128B :
5918 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
5919
5920 def int_hexagon_V6_vavgb :
5921 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">;
5922
5923 def int_hexagon_V6_vavgb_128B :
5924 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">;
5925
5926 def int_hexagon_V6_vavgbrnd :
5927 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">;
5928
5929 def int_hexagon_V6_vavgbrnd_128B :
5930 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
5931
5932 def int_hexagon_V6_vavguw :
5933 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">;
5934
5935 def int_hexagon_V6_vavguw_128B :
5936 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">;
5937
5938 def int_hexagon_V6_vavguwrnd :
5939 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">;
5940
5941 def int_hexagon_V6_vavguwrnd_128B :
5942 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
5943
5944 def int_hexagon_V6_vdd0 :
5945 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">;
5946
5947 def int_hexagon_V6_vdd0_128B :
5948 Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">;
5949
5950 def int_hexagon_V6_vgathermh :
5951 Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>;
5952
5953 def int_hexagon_V6_vgathermh_128B :
5954 Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>;
5955
5956 def int_hexagon_V6_vgathermhq :
5957 Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermhq", [IntrArgMemOnly]>;
5958
5959 def int_hexagon_V6_vgathermhq_128B :
5960 Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhq_128B", [IntrArgMemOnly]>;
5961
5962 def int_hexagon_V6_vgathermhw :
5963 Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>;
5964
5965 def int_hexagon_V6_vgathermhw_128B :
5966 Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>;
5967
5968 def int_hexagon_V6_vgathermhwq :
5969 Hexagon__ptrv64i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhwq", [IntrArgMemOnly]>;
5970
5971 def int_hexagon_V6_vgathermhwq_128B :
5972 Hexagon__ptrv128i1i32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhwq_128B", [IntrArgMemOnly]>;
5973
5974 def int_hexagon_V6_vgathermw :
5975 Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>;
5976
5977 def int_hexagon_V6_vgathermw_128B :
5978 Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>;
5979
5980 def int_hexagon_V6_vgathermwq :
5981 Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermwq", [IntrArgMemOnly]>;
5982
5983 def int_hexagon_V6_vgathermwq_128B :
5984 Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermwq_128B", [IntrArgMemOnly]>;
5985
5986 def int_hexagon_V6_vlut4 :
5987 Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">;
5988
5989 def int_hexagon_V6_vlut4_128B :
5990 Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">;
5991
5992 def int_hexagon_V6_vmpabuu :
5993 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">;
5994
5995 def int_hexagon_V6_vmpabuu_128B :
5996 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
5997
5998 def int_hexagon_V6_vmpabuu_acc :
5999 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
6000
6001 def int_hexagon_V6_vmpabuu_acc_128B :
6002 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
6003
6004 def int_hexagon_V6_vmpahhsat :
6005 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">;
6006
6007 def int_hexagon_V6_vmpahhsat_128B :
6008 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
6009
6010 def int_hexagon_V6_vmpauhuhsat :
6011 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
6012
6013 def int_hexagon_V6_vmpauhuhsat_128B :
6014 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
6015
6016 def int_hexagon_V6_vmpsuhuhsat :
6017 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
6018
6019 def int_hexagon_V6_vmpsuhuhsat_128B :
6020 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
6021
6022 def int_hexagon_V6_vmpyh_acc :
6023 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
6024
6025 def int_hexagon_V6_vmpyh_acc_128B :
6026 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
6027
6028 def int_hexagon_V6_vmpyuhe :
6029 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">;
6030
6031 def int_hexagon_V6_vmpyuhe_128B :
6032 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
6033
6034 def int_hexagon_V6_vmpyuhe_acc :
6035 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
6036
6037 def int_hexagon_V6_vmpyuhe_acc_128B :
6038 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
6039
6040 def int_hexagon_V6_vnavgb :
6041 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">;
6042
6043 def int_hexagon_V6_vnavgb_128B :
6044 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
6045
6046 def int_hexagon_V6_vprefixqb :
6047 Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqb">;
6048
6049 def int_hexagon_V6_vprefixqb_128B :
6050 Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
6051
6052 def int_hexagon_V6_vprefixqh :
6053 Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqh">;
6054
6055 def int_hexagon_V6_vprefixqh_128B :
6056 Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
6057
6058 def int_hexagon_V6_vprefixqw :
6059 Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqw">;
6060
6061 def int_hexagon_V6_vprefixqw_128B :
6062 Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
6063
6064 def int_hexagon_V6_vscattermh :
6065 Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>;
6066
6067 def int_hexagon_V6_vscattermh_128B :
6068 Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>;
6069
6070 def int_hexagon_V6_vscattermh_add :
6071 Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>;
6072
6073 def int_hexagon_V6_vscattermh_add_128B :
6074 Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>;
6075
6076 def int_hexagon_V6_vscattermhq :
6077 Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhq", [IntrWriteMem]>;
6078
6079 def int_hexagon_V6_vscattermhq_128B :
6080 Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhq_128B", [IntrWriteMem]>;
6081
6082 def int_hexagon_V6_vscattermhw :
6083 Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>;
6084
6085 def int_hexagon_V6_vscattermhw_128B :
6086 Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>;
6087
6088 def int_hexagon_V6_vscattermhw_add :
6089 Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>;
6090
6091 def int_hexagon_V6_vscattermhw_add_128B :
6092 Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>;
6093
6094 def int_hexagon_V6_vscattermhwq :
6095 Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhwq", [IntrWriteMem]>;
6096
6097 def int_hexagon_V6_vscattermhwq_128B :
6098 Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhwq_128B", [IntrWriteMem]>;
6099
6100 def int_hexagon_V6_vscattermw :
6101 Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>;
6102
6103 def int_hexagon_V6_vscattermw_128B :
6104 Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>;
6105
6106 def int_hexagon_V6_vscattermw_add :
6107 Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>;
6108
6109 def int_hexagon_V6_vscattermw_add_128B :
6110 Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>;
6111
6112 def int_hexagon_V6_vscattermwq :
6113 Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermwq", [IntrWriteMem]>;
6114
6115 def int_hexagon_V6_vscattermwq_128B :
6116 Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermwq_128B", [IntrWriteMem]>;
6117
6118 // V66 HVX Instructions.
6119
6120 def int_hexagon_V6_vaddcarryo :
6121 Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic;
6122
6123 def int_hexagon_V6_vaddcarryo_128B :
6124 Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B;
6125
6126 def int_hexagon_V6_vaddcarrysat :
6127 Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">;
6128
6129 def int_hexagon_V6_vaddcarrysat_128B :
6130 Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">;
6131
6132 def int_hexagon_V6_vasr_into :
6133 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;
6134
6135 def int_hexagon_V6_vasr_into_128B :
6136 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">;
6137
6138 def int_hexagon_V6_vrotr :
6139 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">;
6140
6141 def int_hexagon_V6_vrotr_128B :
6142 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">;
6143
6144 def int_hexagon_V6_vsatdw :
6145 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">;
6146
6147 def int_hexagon_V6_vsatdw_128B :
6148 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">;
6149
6150 def int_hexagon_V6_vsubcarryo :
6151 Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic;
6152
6153 def int_hexagon_V6_vsubcarryo_128B :
6154 Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B;
6155
6156 // V68 HVX Instructions.
6157
6158 def int_hexagon_V6_v6mpyhubs10 :
6159 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
6160
6161 def int_hexagon_V6_v6mpyhubs10_128B :
6162 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
6163
6164 def int_hexagon_V6_v6mpyhubs10_vxx :
6165 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
6166
6167 def int_hexagon_V6_v6mpyhubs10_vxx_128B :
6168 Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
6169
6170 def int_hexagon_V6_v6mpyvubs10 :
6171 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
6172
6173 def int_hexagon_V6_v6mpyvubs10_128B :
6174 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>;
6175
6176 def int_hexagon_V6_v6mpyvubs10_vxx :
6177 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
6178
6179 def int_hexagon_V6_v6mpyvubs10_vxx_128B :
6180 Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>;
6181
6182 def int_hexagon_V6_vabs_hf :
6183 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_hf">;
6184
6185 def int_hexagon_V6_vabs_hf_128B :
6186 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_hf_128B">;
6187
6188 def int_hexagon_V6_vabs_sf :
6189 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_sf">;
6190
6191 def int_hexagon_V6_vabs_sf_128B :
6192 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_sf_128B">;
6193
6194 def int_hexagon_V6_vadd_hf :
6195 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf">;
6196
6197 def int_hexagon_V6_vadd_hf_128B :
6198 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_128B">;
6199
6200 def int_hexagon_V6_vadd_hf_hf :
6201 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf">;
6202
6203 def int_hexagon_V6_vadd_hf_hf_128B :
6204 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf_128B">;
6205
6206 def int_hexagon_V6_vadd_qf16 :
6207 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16">;
6208
6209 def int_hexagon_V6_vadd_qf16_128B :
6210 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_128B">;
6211
6212 def int_hexagon_V6_vadd_qf16_mix :
6213 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix">;
6214
6215 def int_hexagon_V6_vadd_qf16_mix_128B :
6216 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix_128B">;
6217
6218 def int_hexagon_V6_vadd_qf32 :
6219 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32">;
6220
6221 def int_hexagon_V6_vadd_qf32_128B :
6222 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_128B">;
6223
6224 def int_hexagon_V6_vadd_qf32_mix :
6225 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix">;
6226
6227 def int_hexagon_V6_vadd_qf32_mix_128B :
6228 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix_128B">;
6229
6230 def int_hexagon_V6_vadd_sf :
6231 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf">;
6232
6233 def int_hexagon_V6_vadd_sf_128B :
6234 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_128B">;
6235
6236 def int_hexagon_V6_vadd_sf_hf :
6237 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf">;
6238
6239 def int_hexagon_V6_vadd_sf_hf_128B :
6240 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf_128B">;
6241
6242 def int_hexagon_V6_vadd_sf_sf :
6243 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf">;
6244
6245 def int_hexagon_V6_vadd_sf_sf_128B :
6246 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf_128B">;
6247
6248 def int_hexagon_V6_vassign_fp :
6249 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign_fp">;
6250
6251 def int_hexagon_V6_vassign_fp_128B :
6252 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_fp_128B">;
6253
6254 def int_hexagon_V6_vconv_hf_qf16 :
6255 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16">;
6256
6257 def int_hexagon_V6_vconv_hf_qf16_128B :
6258 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16_128B">;
6259
6260 def int_hexagon_V6_vconv_hf_qf32 :
6261 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32">;
6262
6263 def int_hexagon_V6_vconv_hf_qf32_128B :
6264 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32_128B">;
6265
6266 def int_hexagon_V6_vconv_sf_qf32 :
6267 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32">;
6268
6269 def int_hexagon_V6_vconv_sf_qf32_128B :
6270 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32_128B">;
6271
6272 def int_hexagon_V6_vcvt_b_hf :
6273 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf">;
6274
6275 def int_hexagon_V6_vcvt_b_hf_128B :
6276 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf_128B">;
6277
6278 def int_hexagon_V6_vcvt_h_hf :
6279 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf">;
6280
6281 def int_hexagon_V6_vcvt_h_hf_128B :
6282 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf_128B">;
6283
6284 def int_hexagon_V6_vcvt_hf_b :
6285 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b">;
6286
6287 def int_hexagon_V6_vcvt_hf_b_128B :
6288 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b_128B">;
6289
6290 def int_hexagon_V6_vcvt_hf_h :
6291 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h">;
6292
6293 def int_hexagon_V6_vcvt_hf_h_128B :
6294 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h_128B">;
6295
6296 def int_hexagon_V6_vcvt_hf_sf :
6297 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf">;
6298
6299 def int_hexagon_V6_vcvt_hf_sf_128B :
6300 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf_128B">;
6301
6302 def int_hexagon_V6_vcvt_hf_ub :
6303 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub">;
6304
6305 def int_hexagon_V6_vcvt_hf_ub_128B :
6306 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub_128B">;
6307
6308 def int_hexagon_V6_vcvt_hf_uh :
6309 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh">;
6310
6311 def int_hexagon_V6_vcvt_hf_uh_128B :
6312 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh_128B">;
6313
6314 def int_hexagon_V6_vcvt_sf_hf :
6315 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf">;
6316
6317 def int_hexagon_V6_vcvt_sf_hf_128B :
6318 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf_128B">;
6319
6320 def int_hexagon_V6_vcvt_ub_hf :
6321 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf">;
6322
6323 def int_hexagon_V6_vcvt_ub_hf_128B :
6324 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf_128B">;
6325
6326 def int_hexagon_V6_vcvt_uh_hf :
6327 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf">;
6328
6329 def int_hexagon_V6_vcvt_uh_hf_128B :
6330 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf_128B">;
6331
6332 def int_hexagon_V6_vdmpy_sf_hf :
6333 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf">;
6334
6335 def int_hexagon_V6_vdmpy_sf_hf_128B :
6336 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_128B">;
6337
6338 def int_hexagon_V6_vdmpy_sf_hf_acc :
6339 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc">;
6340
6341 def int_hexagon_V6_vdmpy_sf_hf_acc_128B :
6342 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc_128B">;
6343
6344 def int_hexagon_V6_vfmax_hf :
6345 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_hf">;
6346
6347 def int_hexagon_V6_vfmax_hf_128B :
6348 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_hf_128B">;
6349
6350 def int_hexagon_V6_vfmax_sf :
6351 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_sf">;
6352
6353 def int_hexagon_V6_vfmax_sf_128B :
6354 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_sf_128B">;
6355
6356 def int_hexagon_V6_vfmin_hf :
6357 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_hf">;
6358
6359 def int_hexagon_V6_vfmin_hf_128B :
6360 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_hf_128B">;
6361
6362 def int_hexagon_V6_vfmin_sf :
6363 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_sf">;
6364
6365 def int_hexagon_V6_vfmin_sf_128B :
6366 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_sf_128B">;
6367
6368 def int_hexagon_V6_vfneg_hf :
6369 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_hf">;
6370
6371 def int_hexagon_V6_vfneg_hf_128B :
6372 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_hf_128B">;
6373
6374 def int_hexagon_V6_vfneg_sf :
6375 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_sf">;
6376
6377 def int_hexagon_V6_vfneg_sf_128B :
6378 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_sf_128B">;
6379
6380 def int_hexagon_V6_vgthf :
6381 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf">;
6382
6383 def int_hexagon_V6_vgthf_128B :
6384 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_128B">;
6385
6386 def int_hexagon_V6_vgthf_and :
6387 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_and">;
6388
6389 def int_hexagon_V6_vgthf_and_128B :
6390 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_and_128B">;
6391
6392 def int_hexagon_V6_vgthf_or :
6393 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_or">;
6394
6395 def int_hexagon_V6_vgthf_or_128B :
6396 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_or_128B">;
6397
6398 def int_hexagon_V6_vgthf_xor :
6399 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_xor">;
6400
6401 def int_hexagon_V6_vgthf_xor_128B :
6402 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_xor_128B">;
6403
6404 def int_hexagon_V6_vgtsf :
6405 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf">;
6406
6407 def int_hexagon_V6_vgtsf_128B :
6408 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_128B">;
6409
6410 def int_hexagon_V6_vgtsf_and :
6411 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_and">;
6412
6413 def int_hexagon_V6_vgtsf_and_128B :
6414 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_and_128B">;
6415
6416 def int_hexagon_V6_vgtsf_or :
6417 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_or">;
6418
6419 def int_hexagon_V6_vgtsf_or_128B :
6420 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_or_128B">;
6421
6422 def int_hexagon_V6_vgtsf_xor :
6423 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_xor">;
6424
6425 def int_hexagon_V6_vgtsf_xor_128B :
6426 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_xor_128B">;
6427
6428 def int_hexagon_V6_vmax_hf :
6429 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_hf">;
6430
6431 def int_hexagon_V6_vmax_hf_128B :
6432 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_hf_128B">;
6433
6434 def int_hexagon_V6_vmax_sf :
6435 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_sf">;
6436
6437 def int_hexagon_V6_vmax_sf_128B :
6438 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_sf_128B">;
6439
6440 def int_hexagon_V6_vmin_hf :
6441 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_hf">;
6442
6443 def int_hexagon_V6_vmin_hf_128B :
6444 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_hf_128B">;
6445
6446 def int_hexagon_V6_vmin_sf :
6447 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_sf">;
6448
6449 def int_hexagon_V6_vmin_sf_128B :
6450 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_sf_128B">;
6451
6452 def int_hexagon_V6_vmpy_hf_hf :
6453 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf">;
6454
6455 def int_hexagon_V6_vmpy_hf_hf_128B :
6456 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_128B">;
6457
6458 def int_hexagon_V6_vmpy_hf_hf_acc :
6459 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc">;
6460
6461 def int_hexagon_V6_vmpy_hf_hf_acc_128B :
6462 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc_128B">;
6463
6464 def int_hexagon_V6_vmpy_qf16 :
6465 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16">;
6466
6467 def int_hexagon_V6_vmpy_qf16_128B :
6468 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_128B">;
6469
6470 def int_hexagon_V6_vmpy_qf16_hf :
6471 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf">;
6472
6473 def int_hexagon_V6_vmpy_qf16_hf_128B :
6474 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf_128B">;
6475
6476 def int_hexagon_V6_vmpy_qf16_mix_hf :
6477 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf">;
6478
6479 def int_hexagon_V6_vmpy_qf16_mix_hf_128B :
6480 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf_128B">;
6481
6482 def int_hexagon_V6_vmpy_qf32 :
6483 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32">;
6484
6485 def int_hexagon_V6_vmpy_qf32_128B :
6486 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_128B">;
6487
6488 def int_hexagon_V6_vmpy_qf32_hf :
6489 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf">;
6490
6491 def int_hexagon_V6_vmpy_qf32_hf_128B :
6492 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf_128B">;
6493
6494 def int_hexagon_V6_vmpy_qf32_mix_hf :
6495 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf">;
6496
6497 def int_hexagon_V6_vmpy_qf32_mix_hf_128B :
6498 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf_128B">;
6499
6500 def int_hexagon_V6_vmpy_qf32_qf16 :
6501 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16">;
6502
6503 def int_hexagon_V6_vmpy_qf32_qf16_128B :
6504 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16_128B">;
6505
6506 def int_hexagon_V6_vmpy_qf32_sf :
6507 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf">;
6508
6509 def int_hexagon_V6_vmpy_qf32_sf_128B :
6510 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf_128B">;
6511
6512 def int_hexagon_V6_vmpy_sf_hf :
6513 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf">;
6514
6515 def int_hexagon_V6_vmpy_sf_hf_128B :
6516 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_128B">;
6517
6518 def int_hexagon_V6_vmpy_sf_hf_acc :
6519 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc">;
6520
6521 def int_hexagon_V6_vmpy_sf_hf_acc_128B :
6522 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc_128B">;
6523
6524 def int_hexagon_V6_vmpy_sf_sf :
6525 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf">;
6526
6527 def int_hexagon_V6_vmpy_sf_sf_128B :
6528 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf_128B">;
6529
6530 def int_hexagon_V6_vsub_hf :
6531 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf">;
6532
6533 def int_hexagon_V6_vsub_hf_128B :
6534 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_128B">;
6535
6536 def int_hexagon_V6_vsub_hf_hf :
6537 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf">;
6538
6539 def int_hexagon_V6_vsub_hf_hf_128B :
6540 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf_128B">;
6541
6542 def int_hexagon_V6_vsub_qf16 :
6543 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16">;
6544
6545 def int_hexagon_V6_vsub_qf16_128B :
6546 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_128B">;
6547
6548 def int_hexagon_V6_vsub_qf16_mix :
6549 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix">;
6550
6551 def int_hexagon_V6_vsub_qf16_mix_128B :
6552 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix_128B">;
6553
6554 def int_hexagon_V6_vsub_qf32 :
6555 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32">;
6556
6557 def int_hexagon_V6_vsub_qf32_128B :
6558 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_128B">;
6559
6560 def int_hexagon_V6_vsub_qf32_mix :
6561 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix">;
6562
6563 def int_hexagon_V6_vsub_qf32_mix_128B :
6564 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix_128B">;
6565
6566 def int_hexagon_V6_vsub_sf :
6567 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf">;
6568
6569 def int_hexagon_V6_vsub_sf_128B :
6570 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_128B">;
6571
6572 def int_hexagon_V6_vsub_sf_hf :
6573 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf">;
6574
6575 def int_hexagon_V6_vsub_sf_hf_128B :
6576 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf_128B">;
6577
6578 def int_hexagon_V6_vsub_sf_sf :
6579 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf">;
6580
6581 def int_hexagon_V6_vsub_sf_sf_128B :
6582 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf_128B">;
6583
6584 // V69 HVX Instructions.
6585
6586 def int_hexagon_V6_vasrvuhubrndsat :
6587 Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat">;
6588
6589 def int_hexagon_V6_vasrvuhubrndsat_128B :
6590 Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat_128B">;
6591
6592 def int_hexagon_V6_vasrvuhubsat :
6593 Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat">;
6594
6595 def int_hexagon_V6_vasrvuhubsat_128B :
6596 Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat_128B">;
6597
6598 def int_hexagon_V6_vasrvwuhrndsat :
6599 Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat">;
6600
6601 def int_hexagon_V6_vasrvwuhrndsat_128B :
6602 Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat_128B">;
6603
6604 def int_hexagon_V6_vasrvwuhsat :
6605 Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat">;
6606
6607 def int_hexagon_V6_vasrvwuhsat_128B :
6608 Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat_128B">;
6609
6610 def int_hexagon_V6_vmpyuhvs :
6611 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhvs">;
6612
6613 def int_hexagon_V6_vmpyuhvs_128B :
6614 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhvs_128B">;
6615
6616 // V73 HVX Instructions.
6617
6618 def int_hexagon_V6_vadd_sf_bf :
6619 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf">;
6620
6621 def int_hexagon_V6_vadd_sf_bf_128B :
6622 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf_128B">;
6623
6624 def int_hexagon_V6_vconv_h_hf :
6625 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_h_hf">;
6626
6627 def int_hexagon_V6_vconv_h_hf_128B :
6628 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_h_hf_128B">;
6629
6630 def int_hexagon_V6_vconv_hf_h :
6631 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_h">;
6632
6633 def int_hexagon_V6_vconv_hf_h_128B :
6634 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_h_128B">;
6635
6636 def int_hexagon_V6_vconv_sf_w :
6637 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_w">;
6638
6639 def int_hexagon_V6_vconv_sf_w_128B :
6640 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_w_128B">;
6641
6642 def int_hexagon_V6_vconv_w_sf :
6643 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_w_sf">;
6644
6645 def int_hexagon_V6_vconv_w_sf_128B :
6646 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_w_sf_128B">;
6647
6648 def int_hexagon_V6_vcvt_bf_sf :
6649 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf">;
6650
6651 def int_hexagon_V6_vcvt_bf_sf_128B :
6652 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf_128B">;
6653
6654 def int_hexagon_V6_vgtbf :
6655 Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf">;
6656
6657 def int_hexagon_V6_vgtbf_128B :
6658 Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_128B">;
6659
6660 def int_hexagon_V6_vgtbf_and :
6661 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_and">;
6662
6663 def int_hexagon_V6_vgtbf_and_128B :
6664 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_and_128B">;
6665
6666 def int_hexagon_V6_vgtbf_or :
6667 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_or">;
6668
6669 def int_hexagon_V6_vgtbf_or_128B :
6670 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_or_128B">;
6671
6672 def int_hexagon_V6_vgtbf_xor :
6673 Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_xor">;
6674
6675 def int_hexagon_V6_vgtbf_xor_128B :
6676 Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_xor_128B">;
6677
6678 def int_hexagon_V6_vmax_bf :
6679 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_bf">;
6680
6681 def int_hexagon_V6_vmax_bf_128B :
6682 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_bf_128B">;
6683
6684 def int_hexagon_V6_vmin_bf :
6685 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_bf">;
6686
6687 def int_hexagon_V6_vmin_bf_128B :
6688 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_bf_128B">;
6689
6690 def int_hexagon_V6_vmpy_sf_bf :
6691 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf">;
6692
6693 def int_hexagon_V6_vmpy_sf_bf_128B :
6694 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_128B">;
6695
6696 def int_hexagon_V6_vmpy_sf_bf_acc :
6697 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc">;
6698
6699 def int_hexagon_V6_vmpy_sf_bf_acc_128B :
6700 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc_128B">;
6701
6702 def int_hexagon_V6_vsub_sf_bf :
6703 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf">;
6704
6705 def int_hexagon_V6_vsub_sf_bf_128B :
6706 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf_128B">;
6707
6708 // V79 HVX Instructions.
6709
6710 def int_hexagon_V6_get_qfext :
6711 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_get_qfext">;
6712
6713 def int_hexagon_V6_get_qfext_128B :
6714 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_get_qfext_128B">;
6715
6716 def int_hexagon_V6_get_qfext_oracc :
6717 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_get_qfext_oracc">;
6718
6719 def int_hexagon_V6_get_qfext_oracc_128B :
6720 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_get_qfext_oracc_128B">;
6721
6722 def int_hexagon_V6_set_qfext :
6723 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_set_qfext">;
6724
6725 def int_hexagon_V6_set_qfext_128B :
6726 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_set_qfext_128B">;
6727
6728 def int_hexagon_V6_vabs_f8 :
6729 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_f8">;
6730
6731 def int_hexagon_V6_vabs_f8_128B :
6732 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_f8_128B">;
6733
6734 def int_hexagon_V6_vadd_hf_f8 :
6735 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf_f8">;
6736
6737 def int_hexagon_V6_vadd_hf_f8_128B :
6738 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_f8_128B">;
6739
6740 def int_hexagon_V6_vcvt2_b_hf :
6741 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt2_b_hf">;
6742
6743 def int_hexagon_V6_vcvt2_b_hf_128B :
6744 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt2_b_hf_128B">;
6745
6746 def int_hexagon_V6_vcvt2_hf_b :
6747 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_b">;
6748
6749 def int_hexagon_V6_vcvt2_hf_b_128B :
6750 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_b_128B">;
6751
6752 def int_hexagon_V6_vcvt2_hf_ub :
6753 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_ub">;
6754
6755 def int_hexagon_V6_vcvt2_hf_ub_128B :
6756 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_ub_128B">;
6757
6758 def int_hexagon_V6_vcvt2_ub_hf :
6759 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt2_ub_hf">;
6760
6761 def int_hexagon_V6_vcvt2_ub_hf_128B :
6762 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt2_ub_hf_128B">;
6763
6764 def int_hexagon_V6_vcvt_f8_hf :
6765 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_f8_hf">;
6766
6767 def int_hexagon_V6_vcvt_f8_hf_128B :
6768 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_f8_hf_128B">;
6769
6770 def int_hexagon_V6_vcvt_hf_f8 :
6771 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_f8">;
6772
6773 def int_hexagon_V6_vcvt_hf_f8_128B :
6774 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_f8_128B">;
6775
6776 def int_hexagon_V6_vfmax_f8 :
6777 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_f8">;
6778
6779 def int_hexagon_V6_vfmax_f8_128B :
6780 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_f8_128B">;
6781
6782 def int_hexagon_V6_vfmin_f8 :
6783 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_f8">;
6784
6785 def int_hexagon_V6_vfmin_f8_128B :
6786 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_f8_128B">;
6787
6788 def int_hexagon_V6_vfneg_f8 :
6789 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_f8">;
6790
6791 def int_hexagon_V6_vfneg_f8_128B :
6792 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_f8_128B">;
6793
6794 def int_hexagon_V6_vmerge_qf :
6795 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmerge_qf">;
6796
6797 def int_hexagon_V6_vmerge_qf_128B :
6798 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmerge_qf_128B">;
6799
6800 def int_hexagon_V6_vmpy_hf_f8 :
6801 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8">;
6802
6803 def int_hexagon_V6_vmpy_hf_f8_128B :
6804 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_128B">;
6805
6806 def int_hexagon_V6_vmpy_hf_f8_acc :
6807 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_acc">;
6808
6809 def int_hexagon_V6_vmpy_hf_f8_acc_128B :
6810 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_acc_128B">;
6811
6812 def int_hexagon_V6_vmpy_rt_hf :
6813 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_hf">;
6814
6815 def int_hexagon_V6_vmpy_rt_hf_128B :
6816 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_hf_128B">;
6817
6818 def int_hexagon_V6_vmpy_rt_qf16 :
6819 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_qf16">;
6820
6821 def int_hexagon_V6_vmpy_rt_qf16_128B :
6822 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_qf16_128B">;
6823
6824 def int_hexagon_V6_vmpy_rt_sf :
6825 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_sf">;
6826
6827 def int_hexagon_V6_vmpy_rt_sf_128B :
6828 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_sf_128B">;
6829
6830 def int_hexagon_V6_vsub_hf_f8 :
6831 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf_f8">;
6832
6833 def int_hexagon_V6_vsub_hf_f8_128B :
6834 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_f8_128B">;