Warning, /include/llvm/IR/IntrinsicsHexagon.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
0002 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0003 // See https://llvm.org/LICENSE.txt for license information.
0004 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0005 //
0006 //===----------------------------------------------------------------------===//
0007 //
0008 // This file defines all of the Hexagon-specific intrinsics.
0009 //
0010 //===----------------------------------------------------------------------===//
0011
0012 //===----------------------------------------------------------------------===//
0013 // Definitions for all Hexagon intrinsics.
0014 //
0015 // All Hexagon intrinsics start with "llvm.hexagon.".
0016 let TargetPrefix = "hexagon" in {
0017 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
0018 class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
0019 list<LLVMType> param_types,
0020 list<IntrinsicProperty> properties>
0021 : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
0022 DefaultAttrsIntrinsic<ret_types, param_types, properties>;
0023
0024 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
0025 /// intrinsics.
0026 class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
0027 list<LLVMType> param_types,
0028 list<IntrinsicProperty> properties>
0029 : DefaultAttrsIntrinsic<ret_types, param_types, properties>;
0030 }
0031
0032 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
0033 : Hexagon_Intrinsic<GCCIntSuffix,
0034 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
0035 llvm_i32_ty],
0036 [IntrArgMemOnly]>;
0037
0038 class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
0039 : Hexagon_Intrinsic<GCCIntSuffix,
0040 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
0041 llvm_i32_ty],
0042 [IntrWriteMem]>;
0043
0044 class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
0045 : Hexagon_Intrinsic<GCCIntSuffix,
0046 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
0047 llvm_i32_ty],
0048 [IntrWriteMem]>;
0049
0050 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
0051 : Hexagon_Intrinsic<GCCIntSuffix,
0052 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
0053 llvm_i32_ty, llvm_i32_ty],
0054 [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>;
0055
0056 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
0057 : Hexagon_Intrinsic<GCCIntSuffix,
0058 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
0059 llvm_i32_ty, llvm_i32_ty],
0060 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
0061
0062 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
0063 : Hexagon_Intrinsic<GCCIntSuffix,
0064 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
0065 llvm_i32_ty, llvm_i32_ty],
0066 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
0067
0068 //
0069 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
0070 //
0071 def int_hexagon_circ_ldd :
0072 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
0073 //
0074 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
0075 //
0076 def int_hexagon_circ_ldw :
0077 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
0078 //
0079 // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
0080 //
0081 def int_hexagon_circ_ldh :
0082 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
0083 //
0084 // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
0085 //
0086 def int_hexagon_circ_lduh :
0087 Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
0088 //
0089 // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
0090 //
0091 def int_hexagon_circ_ldb :
0092 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
0093 //
0094 // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
0095 //
0096 def int_hexagon_circ_ldub :
0097 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
0098
0099 //
0100 // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
0101 //
0102 def int_hexagon_circ_std :
0103 Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
0104 //
0105 // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
0106 //
0107 def int_hexagon_circ_stw :
0108 Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
0109 //
0110 // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
0111 //
0112 def int_hexagon_circ_sth :
0113 Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
0114 //
0115 // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
0116 //
0117 def int_hexagon_circ_sthhi :
0118 Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
0119 //
0120 // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
0121 //
0122 def int_hexagon_circ_stb :
0123 Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
0124
0125 def int_hexagon_prefetch :
0126 Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
0127
0128 // Mark locked loads as read/write to prevent any accidental reordering.
0129 // These don't use Hexagon_Intrinsic, because they are not nosync, and as such
0130 // cannot use default attributes.
0131 let TargetPrefix = "hexagon" in {
0132 def int_hexagon_L2_loadw_locked :
0133 ClangBuiltin<"__builtin_HEXAGON_L2_loadw_locked">,
0134 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
0135 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0136 def int_hexagon_L4_loadd_locked :
0137 ClangBuiltin<"__builtin__HEXAGON_L4_loadd_locked">,
0138 Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
0139 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0140
0141 def int_hexagon_S2_storew_locked :
0142 ClangBuiltin<"__builtin_HEXAGON_S2_storew_locked">,
0143 Intrinsic<[llvm_i32_ty],
0144 [llvm_ptr_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0145 def int_hexagon_S4_stored_locked :
0146 ClangBuiltin<"__builtin_HEXAGON_S4_stored_locked">,
0147 Intrinsic<[llvm_i32_ty],
0148 [llvm_ptr_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0149 }
0150
0151 def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
0152 [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
0153 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>]>;
0154
0155 def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset",
0156 [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
0157 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>;
0158
0159 multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
0160 def NAME#_pci : Hexagon_NonGCC_Intrinsic<
0161 [ElTy, llvm_ptr_ty],
0162 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
0163 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
0164 def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
0165 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
0166 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>;
0167 }
0168
0169 defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
0170 defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
0171 defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
0172 defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
0173 defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
0174 defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
0175
0176 multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
0177 def NAME#_pci : Hexagon_NonGCC_Intrinsic<
0178 [llvm_ptr_ty],
0179 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
0180 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>;
0181 def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
0182 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
0183 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
0184 }
0185
0186 defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
0187 defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
0188 defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
0189 defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
0190 defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
0191
0192 // The front-end emits the intrinsic call with only two arguments. The third
0193 // argument from the builtin is already used by front-end to write to memory
0194 // by generating a store.
0195 class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
0196 : Hexagon_NonGCC_Intrinsic<
0197 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
0198 [IntrReadMem]>;
0199
0200 def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
0201 def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
0202 def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
0203 def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
0204 def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
0205 def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
0206
0207 def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
0208 def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
0209 def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
0210 def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
0211 def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
0212
0213 // tag : V6_vrmpybub_rtt
0214 class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix>
0215 : Hexagon_Intrinsic<GCCIntSuffix,
0216 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
0217 [IntrNoMem]>;
0218
0219 // tag : V6_vrmpybub_rtt_128B
0220 class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix>
0221 : Hexagon_Intrinsic<GCCIntSuffix,
0222 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
0223 [IntrNoMem]>;
0224
0225 // tag : V6_vrmpybub_rtt_acc
0226 class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix>
0227 : Hexagon_Intrinsic<GCCIntSuffix,
0228 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
0229 [IntrNoMem]>;
0230
0231 // tag : V6_vrmpybub_rtt_acc_128B
0232 class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix>
0233 : Hexagon_Intrinsic<GCCIntSuffix,
0234 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
0235 [IntrNoMem]>;
0236
0237 def int_hexagon_V6_vrmpybub_rtt :
0238 Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
0239
0240 def int_hexagon_V6_vrmpybub_rtt_128B :
0241 Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
0242
0243 def int_hexagon_V6_vrmpybub_rtt_acc :
0244 Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
0245
0246 def int_hexagon_V6_vrmpybub_rtt_acc_128B :
0247 Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
0248
0249 def int_hexagon_V6_vrmpyub_rtt :
0250 Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
0251
0252 def int_hexagon_V6_vrmpyub_rtt_128B :
0253 Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
0254
0255 def int_hexagon_V6_vrmpyub_rtt_acc :
0256 Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
0257
0258 def int_hexagon_V6_vrmpyub_rtt_acc_128B :
0259 Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
0260
0261 // HVX conditional loads/stores
0262
0263 class Hexagon_pred_vload_imm<LLVMType ValTy>
0264 : Hexagon_NonGCC_Intrinsic<
0265 [ValTy],
0266 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty],
0267 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
0268 ImmArg<ArgIndex<2>>]>;
0269
0270 class Hexagon_pred_vload_imm_64B: Hexagon_pred_vload_imm<llvm_v16i32_ty>;
0271 class Hexagon_pred_vload_imm_128B: Hexagon_pred_vload_imm<llvm_v32i32_ty>;
0272
0273 def int_hexagon_V6_vL32b_pred_ai: Hexagon_pred_vload_imm_64B;
0274 def int_hexagon_V6_vL32b_npred_ai: Hexagon_pred_vload_imm_64B;
0275 def int_hexagon_V6_vL32b_nt_pred_ai: Hexagon_pred_vload_imm_64B;
0276 def int_hexagon_V6_vL32b_nt_npred_ai: Hexagon_pred_vload_imm_64B;
0277 def int_hexagon_V6_vL32b_pred_ai_128B: Hexagon_pred_vload_imm_128B;
0278 def int_hexagon_V6_vL32b_npred_ai_128B: Hexagon_pred_vload_imm_128B;
0279 def int_hexagon_V6_vL32b_nt_pred_ai_128B: Hexagon_pred_vload_imm_128B;
0280 def int_hexagon_V6_vL32b_nt_npred_ai_128B: Hexagon_pred_vload_imm_128B;
0281
0282 class Hexagom_pred_vload_upd<LLVMType ValTy, bit TakesImm>
0283 : Hexagon_NonGCC_Intrinsic<
0284 [ValTy, llvm_ptr_ty],
0285 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty],
0286 !if(TakesImm,
0287 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
0288 ImmArg<ArgIndex<2>>],
0289 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>;
0290
0291 class Hexagom_pred_vload_upd_64B<bit TakesImm>
0292 : Hexagom_pred_vload_upd<llvm_v16i32_ty, TakesImm>;
0293 class Hexagom_pred_vload_upd_128B<bit TakesImm>
0294 : Hexagom_pred_vload_upd<llvm_v32i32_ty, TakesImm>;
0295
0296 def int_hexagon_V6_vL32b_pred_pi: Hexagom_pred_vload_upd_64B<1>;
0297 def int_hexagon_V6_vL32b_npred_pi: Hexagom_pred_vload_upd_64B<1>;
0298 def int_hexagon_V6_vL32b_nt_pred_pi: Hexagom_pred_vload_upd_64B<1>;
0299 def int_hexagon_V6_vL32b_nt_npred_pi: Hexagom_pred_vload_upd_64B<1>;
0300 def int_hexagon_V6_vL32b_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
0301 def int_hexagon_V6_vL32b_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
0302 def int_hexagon_V6_vL32b_nt_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
0303 def int_hexagon_V6_vL32b_nt_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
0304
0305 def int_hexagon_V6_vL32b_pred_ppu: Hexagom_pred_vload_upd_64B<0>;
0306 def int_hexagon_V6_vL32b_npred_ppu: Hexagom_pred_vload_upd_64B<0>;
0307 def int_hexagon_V6_vL32b_nt_pred_ppu: Hexagom_pred_vload_upd_64B<0>;
0308 def int_hexagon_V6_vL32b_nt_npred_ppu: Hexagom_pred_vload_upd_64B<0>;
0309 def int_hexagon_V6_vL32b_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
0310 def int_hexagon_V6_vL32b_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
0311 def int_hexagon_V6_vL32b_nt_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
0312 def int_hexagon_V6_vL32b_nt_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
0313
0314
0315 class Hexagon_pred_vstore_imm<LLVMType ValTy>
0316 : Hexagon_NonGCC_Intrinsic<
0317 [],
0318 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty, ValTy],
0319 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
0320 ImmArg<ArgIndex<2>>]>;
0321
0322 class Hexagon_pred_vstore_imm_64B: Hexagon_pred_vstore_imm<llvm_v16i32_ty>;
0323 class Hexagon_pred_vstore_imm_128B: Hexagon_pred_vstore_imm<llvm_v32i32_ty>;
0324
0325 def int_hexagon_V6_vS32b_pred_ai: Hexagon_pred_vstore_imm_64B;
0326 def int_hexagon_V6_vS32b_npred_ai: Hexagon_pred_vstore_imm_64B;
0327 def int_hexagon_V6_vS32Ub_pred_ai: Hexagon_pred_vstore_imm_64B;
0328 def int_hexagon_V6_vS32Ub_npred_ai: Hexagon_pred_vstore_imm_64B;
0329 def int_hexagon_V6_vS32b_nt_pred_ai: Hexagon_pred_vstore_imm_64B;
0330 def int_hexagon_V6_vS32b_nt_npred_ai: Hexagon_pred_vstore_imm_64B;
0331 def int_hexagon_V6_vS32b_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
0332 def int_hexagon_V6_vS32b_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
0333 def int_hexagon_V6_vS32Ub_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
0334 def int_hexagon_V6_vS32Ub_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
0335 def int_hexagon_V6_vS32b_nt_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
0336 def int_hexagon_V6_vS32b_nt_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
0337
0338 class Hexagon_pred_vstore_upd<LLVMType ValTy, bit TakesImm>
0339 : Hexagon_NonGCC_Intrinsic<
0340 [llvm_ptr_ty],
0341 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty, ValTy],
0342 !if(TakesImm,
0343 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
0344 ImmArg<ArgIndex<2>>],
0345 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>;
0346
0347 class Hexagon_pred_vstore_upd_64B<bit TakesImm>
0348 : Hexagon_pred_vstore_upd<llvm_v16i32_ty, TakesImm>;
0349 class Hexagon_pred_vstore_upd_128B<bit TakesImm>
0350 : Hexagon_pred_vstore_upd<llvm_v32i32_ty, TakesImm>;
0351
0352 def int_hexagon_V6_vS32b_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
0353 def int_hexagon_V6_vS32b_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
0354 def int_hexagon_V6_vS32Ub_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
0355 def int_hexagon_V6_vS32Ub_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
0356 def int_hexagon_V6_vS32b_nt_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
0357 def int_hexagon_V6_vS32b_nt_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
0358 def int_hexagon_V6_vS32b_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0359 def int_hexagon_V6_vS32b_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0360 def int_hexagon_V6_vS32Ub_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0361 def int_hexagon_V6_vS32Ub_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0362 def int_hexagon_V6_vS32b_nt_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0363 def int_hexagon_V6_vS32b_nt_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
0364
0365 def int_hexagon_V6_vS32b_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0366 def int_hexagon_V6_vS32b_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0367 def int_hexagon_V6_vS32Ub_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0368 def int_hexagon_V6_vS32Ub_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0369 def int_hexagon_V6_vS32b_nt_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0370 def int_hexagon_V6_vS32b_nt_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
0371 def int_hexagon_V6_vS32b_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0372 def int_hexagon_V6_vS32b_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0373 def int_hexagon_V6_vS32Ub_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0374 def int_hexagon_V6_vS32Ub_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0375 def int_hexagon_V6_vS32b_nt_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0376 def int_hexagon_V6_vS32b_nt_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
0377
0378
0379 // HVX Vector predicate casts.
0380 // These intrinsics do not emit (nor do they correspond to) any instructions,
0381 // they are no-ops.
0382
0383 def int_hexagon_V6_pred_typecast :
0384 Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0385
0386 def int_hexagon_V6_pred_typecast_128B :
0387 Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0388
0389 // HVX full-precision multiplication.
0390 // V6_vmpyss_parts(Vu,Vv) = (MulHS(Vu,Vv), Mul(Vu,Vv))
0391 // V6_vmpyuu_parts(Vu,Vv) = (MulHU(Vu,Vv), Mul(Vu,Vv))
0392 // V6_vmpyus_parts(Vu,Vv) = (MulHUS(Vu,Vv), Mul(Vu,Vv))
0393 //
0394 // Both, the (purportedly) 64b and the _128B versions are exactly equivalent
0395 // regardless of the HVX mode, they are both defined for consistency.
0396 // The purpose of these intrinsics is to have a uniform way of multiplying two
0397 // integer vectors in the LLVM IR. Many HVX multiply operations interleave
0398 // the even-odd results, except for 32x32 multiplications. Also, different
0399 // HVX versions have different instructions that can be used, so defer the
0400 // instruction choice to the isel.
0401 class Hexagon_vv_vv_pure:
0402 Hexagon_NonGCC_Intrinsic<
0403 [llvm_anyvector_ty, LLVMMatchType<0>],
0404 [LLVMMatchType<0>, LLVMMatchType<0>],
0405 [IntrNoMem]>;
0406
0407 def int_hexagon_V6_vmpyss_parts: Hexagon_vv_vv_pure;
0408 def int_hexagon_V6_vmpyss_parts_128B: Hexagon_vv_vv_pure;
0409 def int_hexagon_V6_vmpyuu_parts: Hexagon_vv_vv_pure;
0410 def int_hexagon_V6_vmpyuu_parts_128B: Hexagon_vv_vv_pure;
0411 def int_hexagon_V6_vmpyus_parts: Hexagon_vv_vv_pure;
0412 def int_hexagon_V6_vmpyus_parts_128B: Hexagon_vv_vv_pure;
0413
0414
0415 // Masked vector stores
0416 //
0417 // These are all deprecated, the intrinsics matching instruction names
0418 // should be used instead, e.g. int_hexagon_V6_vS32b_qpred_ai, etc.
0419
0420 class Hexagon_custom_vms_Intrinsic
0421 : Hexagon_NonGCC_Intrinsic<
0422 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], [IntrWriteMem]>;
0423
0424 class Hexagon_custom_vms_Intrinsic_128B
0425 : Hexagon_NonGCC_Intrinsic<
0426 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], [IntrWriteMem]>;
0427
0428 def int_hexagon_V6_vmaskedstoreq: Hexagon_custom_vms_Intrinsic;
0429 def int_hexagon_V6_vmaskedstorenq: Hexagon_custom_vms_Intrinsic;
0430 def int_hexagon_V6_vmaskedstorentq: Hexagon_custom_vms_Intrinsic;
0431 def int_hexagon_V6_vmaskedstorentnq: Hexagon_custom_vms_Intrinsic;
0432
0433 def int_hexagon_V6_vmaskedstoreq_128B: Hexagon_custom_vms_Intrinsic_128B;
0434 def int_hexagon_V6_vmaskedstorenq_128B: Hexagon_custom_vms_Intrinsic_128B;
0435 def int_hexagon_V6_vmaskedstorentq_128B: Hexagon_custom_vms_Intrinsic_128B;
0436 def int_hexagon_V6_vmaskedstorentnq_128B: Hexagon_custom_vms_Intrinsic_128B;
0437
0438
0439 // Intrinsic for instrumentation based profiling using a custom handler. The
0440 // name of the handler is passed as the first operand to the intrinsic. The
0441 // handler can take only one int32 input which is passed as the second
0442 // operand to the intrinsic.
0443 def int_hexagon_instrprof_custom
0444 : Hexagon_NonGCC_Intrinsic<[],
0445 [llvm_ptr_ty, llvm_i32_ty],
0446 [IntrInaccessibleMemOnly]>;
0447
0448
0449 include "llvm/IR/IntrinsicsHexagonDep.td"
