Warning, /include/llvm/IR/IntrinsicsARM.td is written in an unsupported language. File is not indexed.
0001 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines all of the ARM-specific intrinsics.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013
0014 //===----------------------------------------------------------------------===//
0015 // TLS
0016
0017 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
0018
0019 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
0020 // first argument is the number of bytes this "instruction" takes up, the second
0021 // and return value are essentially chains, used to force ordering during ISel.
0022 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
0023
0024 // 16-bit multiplications
0025 def int_arm_smulbb : ClangBuiltin<"__builtin_arm_smulbb">,
0026 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0027 [IntrNoMem]>;
0028 def int_arm_smulbt : ClangBuiltin<"__builtin_arm_smulbt">,
0029 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0030 [IntrNoMem]>;
0031 def int_arm_smultb : ClangBuiltin<"__builtin_arm_smultb">,
0032 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0033 [IntrNoMem]>;
0034 def int_arm_smultt : ClangBuiltin<"__builtin_arm_smultt">,
0035 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0036 [IntrNoMem]>;
0037 def int_arm_smulwb : ClangBuiltin<"__builtin_arm_smulwb">,
0038 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0039 [IntrNoMem]>;
0040 def int_arm_smulwt : ClangBuiltin<"__builtin_arm_smulwt">,
0041 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0042 [IntrNoMem]>;
0043
0044 //===----------------------------------------------------------------------===//
0045 // Saturating Arithmetic
0046
0047 def int_arm_qadd : ClangBuiltin<"__builtin_arm_qadd">,
0048 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0049 [Commutative, IntrNoMem]>;
0050 def int_arm_qsub : ClangBuiltin<"__builtin_arm_qsub">,
0051 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0052 [IntrNoMem]>;
0053 def int_arm_ssat : ClangBuiltin<"__builtin_arm_ssat">,
0054 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0055 [IntrNoMem]>;
0056 def int_arm_usat : ClangBuiltin<"__builtin_arm_usat">,
0057 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0058 [IntrNoMem]>;
0059
0060 // Accumulating multiplications
0061 def int_arm_smlabb : ClangBuiltin<"__builtin_arm_smlabb">,
0062 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0063 llvm_i32_ty],
0064 [IntrNoMem]>;
0065 def int_arm_smlabt : ClangBuiltin<"__builtin_arm_smlabt">,
0066 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0067 llvm_i32_ty],
0068 [IntrNoMem]>;
0069 def int_arm_smlatb : ClangBuiltin<"__builtin_arm_smlatb">,
0070 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0071 llvm_i32_ty],
0072 [IntrNoMem]>;
0073 def int_arm_smlatt : ClangBuiltin<"__builtin_arm_smlatt">,
0074 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0075 llvm_i32_ty],
0076 [IntrNoMem]>;
0077 def int_arm_smlawb : ClangBuiltin<"__builtin_arm_smlawb">,
0078 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0079 llvm_i32_ty],
0080 [IntrNoMem]>;
0081 def int_arm_smlawt : ClangBuiltin<"__builtin_arm_smlawt">,
0082 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0083 llvm_i32_ty],
0084 [IntrNoMem]>;
0085
0086 // Parallel 16-bit saturation
0087 def int_arm_ssat16 : ClangBuiltin<"__builtin_arm_ssat16">,
0088 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0089 [IntrNoMem]>;
0090 def int_arm_usat16 : ClangBuiltin<"__builtin_arm_usat16">,
0091 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0092 [IntrNoMem]>;
0093
0094 // Packing and unpacking
0095 def int_arm_sxtab16 : ClangBuiltin<"__builtin_arm_sxtab16">,
0096 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0097 [IntrNoMem]>;
0098 def int_arm_sxtb16 : ClangBuiltin<"__builtin_arm_sxtb16">,
0099 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
0100 def int_arm_uxtab16 : ClangBuiltin<"__builtin_arm_uxtab16">,
0101 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0102 [IntrNoMem]>;
0103 def int_arm_uxtb16 : ClangBuiltin<"__builtin_arm_uxtb16">,
0104 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
0105
0106 // Parallel selection, reads the GE flags.
0107 def int_arm_sel : ClangBuiltin<"__builtin_arm_sel">,
0108 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0109 [IntrReadMem]>;
0110
0111 // Parallel 8-bit addition and subtraction
0112 def int_arm_qadd8 : ClangBuiltin<"__builtin_arm_qadd8">,
0113 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0114 [IntrNoMem]>;
0115 def int_arm_qsub8 : ClangBuiltin<"__builtin_arm_qsub8">,
0116 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0117 [IntrNoMem]>;
0118 // Writes to the GE bits.
0119 def int_arm_sadd8 : ClangBuiltin<"__builtin_arm_sadd8">,
0120 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0121 def int_arm_shadd8 : ClangBuiltin<"__builtin_arm_shadd8">,
0122 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0123 [IntrNoMem]>;
0124 def int_arm_shsub8 : ClangBuiltin<"__builtin_arm_shsub8">,
0125 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0126 [IntrNoMem]>;
0127 // Writes to the GE bits.
0128 def int_arm_ssub8 : ClangBuiltin<"__builtin_arm_ssub8">,
0129 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0130 // Writes to the GE bits.
0131 def int_arm_uadd8 : ClangBuiltin<"__builtin_arm_uadd8">,
0132 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0133 def int_arm_uhadd8 : ClangBuiltin<"__builtin_arm_uhadd8">,
0134 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0135 [IntrNoMem]>;
0136 def int_arm_uhsub8 : ClangBuiltin<"__builtin_arm_uhsub8">,
0137 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0138 [IntrNoMem]>;
0139 def int_arm_uqadd8 : ClangBuiltin<"__builtin_arm_uqadd8">,
0140 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0141 [IntrNoMem]>;
0142 def int_arm_uqsub8 : ClangBuiltin<"__builtin_arm_uqsub8">,
0143 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0144 [IntrNoMem]>;
0145 // Writes to the GE bits.
0146 def int_arm_usub8 : ClangBuiltin<"__builtin_arm_usub8">,
0147 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0148
0149 // Sum of 8-bit absolute differences
0150 def int_arm_usad8 : ClangBuiltin<"__builtin_arm_usad8">,
0151 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0152 [IntrNoMem]>;
0153 def int_arm_usada8 : ClangBuiltin<"__builtin_arm_usada8">,
0154 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0155 llvm_i32_ty],
0156 [IntrNoMem]>;
0157
0158 // Parallel 16-bit addition and subtraction
0159 def int_arm_qadd16 : ClangBuiltin<"__builtin_arm_qadd16">,
0160 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0161 [IntrNoMem]>;
0162 def int_arm_qasx : ClangBuiltin<"__builtin_arm_qasx">,
0163 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0164 [IntrNoMem]>;
0165 def int_arm_qsax : ClangBuiltin<"__builtin_arm_qsax">,
0166 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0167 [IntrNoMem]>;
0168 def int_arm_qsub16 : ClangBuiltin<"__builtin_arm_qsub16">,
0169 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0170 [IntrNoMem]>;
0171 // Writes to the GE bits.
0172 def int_arm_sadd16 : ClangBuiltin<"__builtin_arm_sadd16">,
0173 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0174 // Writes to the GE bits.
0175 def int_arm_sasx : ClangBuiltin<"__builtin_arm_sasx">,
0176 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0177 def int_arm_shadd16 : ClangBuiltin<"__builtin_arm_shadd16">,
0178 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0179 [IntrNoMem]>;
0180 def int_arm_shasx : ClangBuiltin<"__builtin_arm_shasx">,
0181 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0182 [IntrNoMem]>;
0183 def int_arm_shsax : ClangBuiltin<"__builtin_arm_shsax">,
0184 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0185 [IntrNoMem]>;
0186 def int_arm_shsub16 : ClangBuiltin<"__builtin_arm_shsub16">,
0187 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0188 [IntrNoMem]>;
0189 // Writes to the GE bits.
0190 def int_arm_ssax : ClangBuiltin<"__builtin_arm_ssax">,
0191 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0192 // Writes to the GE bits.
0193 def int_arm_ssub16 : ClangBuiltin<"__builtin_arm_ssub16">,
0194 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0195 // Writes to the GE bits.
0196 def int_arm_uadd16 : ClangBuiltin<"__builtin_arm_uadd16">,
0197 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0198 // Writes to the GE bits.
0199 def int_arm_uasx : ClangBuiltin<"__builtin_arm_uasx">,
0200 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0201 def int_arm_uhadd16 : ClangBuiltin<"__builtin_arm_uhadd16">,
0202 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0203 [IntrNoMem]>;
0204 def int_arm_uhasx : ClangBuiltin<"__builtin_arm_uhasx">,
0205 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0206 [IntrNoMem]>;
0207 def int_arm_uhsax : ClangBuiltin<"__builtin_arm_uhsax">,
0208 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0209 [IntrNoMem]>;
0210 def int_arm_uhsub16 : ClangBuiltin<"__builtin_arm_uhsub16">,
0211 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0212 [IntrNoMem]>;
0213 def int_arm_uqadd16 : ClangBuiltin<"__builtin_arm_uqadd16">,
0214 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0215 [IntrNoMem]>;
0216 def int_arm_uqasx : ClangBuiltin<"__builtin_arm_uqasx">,
0217 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0218 [IntrNoMem]>;
0219 def int_arm_uqsax : ClangBuiltin<"__builtin_arm_uqsax">,
0220 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0221 [IntrNoMem]>;
0222 def int_arm_uqsub16 : ClangBuiltin<"__builtin_arm_uqsub16">,
0223 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0224 [IntrNoMem]>;
0225 // Writes to the GE bits.
0226 def int_arm_usax : ClangBuiltin<"__builtin_arm_usax">,
0227 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0228 // Writes to the GE bits.
0229 def int_arm_usub16 : ClangBuiltin<"__builtin_arm_usub16">,
0230 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
0231
0232 // Parallel 16-bit multiplication
0233 def int_arm_smlad : ClangBuiltin<"__builtin_arm_smlad">,
0234 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0235 llvm_i32_ty],
0236 [IntrNoMem]>;
0237 def int_arm_smladx : ClangBuiltin<"__builtin_arm_smladx">,
0238 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0239 llvm_i32_ty],
0240 [IntrNoMem]>;
0241 def int_arm_smlald : ClangBuiltin<"__builtin_arm_smlald">,
0242 DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
0243 llvm_i64_ty],
0244 [IntrNoMem]>;
0245 def int_arm_smlaldx : ClangBuiltin<"__builtin_arm_smlaldx">,
0246 DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
0247 llvm_i64_ty],
0248 [IntrNoMem]>;
0249 def int_arm_smlsd : ClangBuiltin<"__builtin_arm_smlsd">,
0250 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0251 llvm_i32_ty],
0252 [IntrNoMem]>;
0253 def int_arm_smlsdx : ClangBuiltin<"__builtin_arm_smlsdx">,
0254 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0255 llvm_i32_ty],
0256 [IntrNoMem]>;
0257 def int_arm_smlsld : ClangBuiltin<"__builtin_arm_smlsld">,
0258 DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
0259 llvm_i64_ty],
0260 [IntrNoMem]>;
0261 def int_arm_smlsldx : ClangBuiltin<"__builtin_arm_smlsldx">,
0262 DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
0263 llvm_i64_ty],
0264 [IntrNoMem]>;
0265 def int_arm_smuad : ClangBuiltin<"__builtin_arm_smuad">,
0266 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0267 [IntrNoMem]>;
0268 def int_arm_smuadx : ClangBuiltin<"__builtin_arm_smuadx">,
0269 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0270 [IntrNoMem]>;
0271 def int_arm_smusd : ClangBuiltin<"__builtin_arm_smusd">,
0272 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0273 [IntrNoMem]>;
0274 def int_arm_smusdx : ClangBuiltin<"__builtin_arm_smusdx">,
0275 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
0276 [IntrNoMem]>;
0277
0278
0279 //===----------------------------------------------------------------------===//
0280 // Load, Store and Clear exclusive
0281
0282 // TODO: Add applicable default attributes.
0283 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
0284 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
0285
0286 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
0287 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
0288
0289 def int_arm_clrex : Intrinsic<[]>;
0290
0291 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
0292 llvm_ptr_ty]>;
0293 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
0294
0295 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
0296 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
0297 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
0298
0299 //===----------------------------------------------------------------------===//
0300 // Data barrier instructions
0301
0302 // TODO: Add applicable default attributes.
0303 def int_arm_dmb : ClangBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
0304 Intrinsic<[], [llvm_i32_ty]>;
0305 def int_arm_dsb : ClangBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
0306 Intrinsic<[], [llvm_i32_ty]>;
0307 def int_arm_isb : ClangBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
0308 Intrinsic<[], [llvm_i32_ty]>;
0309
0310 //===----------------------------------------------------------------------===//
0311 // VFP
0312
0313 def int_arm_get_fpscr : ClangBuiltin<"__builtin_arm_get_fpscr">,
0314 DefaultAttrsIntrinsic<[llvm_i32_ty], [], []>;
0315 def int_arm_set_fpscr : ClangBuiltin<"__builtin_arm_set_fpscr">,
0316 DefaultAttrsIntrinsic<[], [llvm_i32_ty], []>;
0317 def int_arm_vcvtr : DefaultAttrsIntrinsic<[llvm_float_ty],
0318 [llvm_anyfloat_ty], [IntrNoMem]>;
0319 def int_arm_vcvtru : DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
0320 [IntrNoMem]>;
0321
0322 //===----------------------------------------------------------------------===//
0323 // Coprocessor
0324
0325 // TODO: Add applicable default attributes.
0326 def int_arm_ldc : ClangBuiltin<"__builtin_arm_ldc">,
0327 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0328 def int_arm_ldcl : ClangBuiltin<"__builtin_arm_ldcl">,
0329 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0330 def int_arm_ldc2 : ClangBuiltin<"__builtin_arm_ldc2">,
0331 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0332 def int_arm_ldc2l : ClangBuiltin<"__builtin_arm_ldc2l">,
0333 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0334
0335 def int_arm_stc : ClangBuiltin<"__builtin_arm_stc">,
0336 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0337 def int_arm_stcl : ClangBuiltin<"__builtin_arm_stcl">,
0338 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0339 def int_arm_stc2 : ClangBuiltin<"__builtin_arm_stc2">,
0340 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0341 def int_arm_stc2l : ClangBuiltin<"__builtin_arm_stc2l">,
0342 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
0343
0344 // Move to coprocessor
0345 def int_arm_mcr : ClangBuiltin<"__builtin_arm_mcr">,
0346 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0347 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
0348 def int_arm_mcr2 : ClangBuiltin<"__builtin_arm_mcr2">,
0349 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0350 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
0351
0352 // Move from coprocessor
0353 def int_arm_mrc : ClangBuiltin<"__builtin_arm_mrc">,
0354 MSBuiltin<"_MoveFromCoprocessor">,
0355 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0356 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
0357 def int_arm_mrc2 : ClangBuiltin<"__builtin_arm_mrc2">,
0358 MSBuiltin<"_MoveFromCoprocessor2">,
0359 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0360 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
0361
0362 // Coprocessor data processing
0363 def int_arm_cdp : ClangBuiltin<"__builtin_arm_cdp">,
0364 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0365 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
0366 def int_arm_cdp2 : ClangBuiltin<"__builtin_arm_cdp2">,
0367 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0368 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
0369
0370 // Move from two registers to coprocessor
0371 def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0372 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
0373 def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
0374 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
0375
0376 def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
0377 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
0378 def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
0379 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
0380
0381 //===----------------------------------------------------------------------===//
0382 // CRC32
0383
0384 def int_arm_crc32b : DefaultAttrsIntrinsic<
0385 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0386 def int_arm_crc32cb : DefaultAttrsIntrinsic<
0387 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0388 def int_arm_crc32h : DefaultAttrsIntrinsic<
0389 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0390 def int_arm_crc32ch : DefaultAttrsIntrinsic<
0391 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0392 def int_arm_crc32w : DefaultAttrsIntrinsic<
0393 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0394 def int_arm_crc32cw : DefaultAttrsIntrinsic<
0395 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
0396
0397 //===----------------------------------------------------------------------===//
0398 // CMSE
0399
0400 // TODO: Add applicable default attributes.
0401 def int_arm_cmse_tt : ClangBuiltin<"__builtin_arm_cmse_TT">,
0402 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
0403 def int_arm_cmse_ttt : ClangBuiltin<"__builtin_arm_cmse_TTT">,
0404 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
0405 def int_arm_cmse_tta : ClangBuiltin<"__builtin_arm_cmse_TTA">,
0406 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
0407 def int_arm_cmse_ttat : ClangBuiltin<"__builtin_arm_cmse_TTAT">,
0408 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
0409
0410 //===----------------------------------------------------------------------===//
0411 // HINT
0412
0413 // TODO: Add applicable default attributes.
0414 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
0415 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
0416
0417 //===----------------------------------------------------------------------===//
0418 // UND (reserved undefined sequence)
0419
0420 // TODO: Add applicable default attributes.
0421 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
0422
0423 //===----------------------------------------------------------------------===//
0424 // Advanced SIMD (NEON)
0425
0426 // The following classes do not correspond directly to GCC builtins.
0427 class Neon_1Arg_Intrinsic
0428 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
0429 class Neon_1Arg_Narrow_Intrinsic
0430 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>],
0431 [IntrNoMem]>;
0432 class Neon_2Arg_Intrinsic
0433 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0434 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
0435 class Neon_2Arg_Narrow_Intrinsic
0436 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0437 [LLVMExtendedType<0>, LLVMExtendedType<0>],
0438 [IntrNoMem]>;
0439 class Neon_2Arg_Long_Intrinsic
0440 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0441 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
0442 [IntrNoMem]>;
0443 class Neon_3Arg_Intrinsic
0444 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0445 [LLVMMatchType<0>, LLVMMatchType<0>,
0446 LLVMMatchType<0>],
0447 [IntrNoMem]>;
0448 class Neon_3Arg_Long_Intrinsic
0449 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0450 [LLVMMatchType<0>, LLVMTruncatedType<0>,
0451 LLVMTruncatedType<0>],
0452 [IntrNoMem]>;
0453
0454 class Neon_1FloatArg_Intrinsic
0455 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
0456
0457 class Neon_CvtFxToFP_Intrinsic
0458 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
0459 [IntrNoMem]>;
0460 class Neon_CvtFPToFx_Intrinsic
0461 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
0462 [IntrNoMem]>;
0463 class Neon_CvtFPtoInt_1Arg_Intrinsic
0464 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
0465 [IntrNoMem]>;
0466
0467 class Neon_Compare_Intrinsic
0468 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0469 [llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>;
0470
0471 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
0472 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
0473 // Overall, the classes range from 2 to 6 v8i8 arguments.
0474 class Neon_Tbl2Arg_Intrinsic
0475 : DefaultAttrsIntrinsic<[llvm_v8i8_ty],
0476 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
0477 class Neon_Tbl3Arg_Intrinsic
0478 : DefaultAttrsIntrinsic<[llvm_v8i8_ty],
0479 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
0480 [IntrNoMem]>;
0481 class Neon_Tbl4Arg_Intrinsic
0482 : DefaultAttrsIntrinsic<[llvm_v8i8_ty],
0483 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
0484 llvm_v8i8_ty],
0485 [IntrNoMem]>;
0486 class Neon_Tbl5Arg_Intrinsic
0487 : DefaultAttrsIntrinsic<[llvm_v8i8_ty],
0488 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
0489 llvm_v8i8_ty, llvm_v8i8_ty],
0490 [IntrNoMem]>;
0491 class Neon_Tbl6Arg_Intrinsic
0492 : DefaultAttrsIntrinsic<[llvm_v8i8_ty],
0493 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
0494 llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
0495 [IntrNoMem]>;
0496
0497 // Arithmetic ops
0498
0499 let IntrProperties = [IntrNoMem, Commutative] in {
0500
0501 // Vector Add.
0502 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
0503 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
0504 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
0505 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
0506 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
0507
0508 // Vector Multiply.
0509 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
0510 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
0511 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
0512 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
0513 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
0514 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
0515 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
0516
0517 // Vector Maximum.
0518 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
0519 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
0520 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
0521
0522 // Vector Minimum.
0523 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
0524 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
0525 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
0526
0527 // Vector Reciprocal Step.
0528 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
0529
0530 // Vector Reciprocal Square Root Step.
0531 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
0532 }
0533
0534 // Vector Subtract.
0535 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
0536 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
0537 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
0538
0539 // Vector Absolute Compare.
0540 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
0541 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
0542
0543 // Vector Absolute Differences.
0544 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
0545 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
0546
0547 // Vector Pairwise Add.
0548 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
0549
0550 // Vector Pairwise Add Long.
0551 // Note: This is different than the other "long" NEON intrinsics because
0552 // the result vector has half as many elements as the source vector.
0553 // The source and destination vector types must be specified separately.
0554 def int_arm_neon_vpaddls : DefaultAttrsIntrinsic<
0555 [llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0556 def int_arm_neon_vpaddlu : DefaultAttrsIntrinsic<
0557 [llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0558
0559 // Vector Pairwise Add and Accumulate Long.
0560 // Note: This is similar to vpaddl but the destination vector also appears
0561 // as the first argument.
0562 def int_arm_neon_vpadals : DefaultAttrsIntrinsic<
0563 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty], [IntrNoMem]>;
0564 def int_arm_neon_vpadalu : DefaultAttrsIntrinsic<
0565 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty], [IntrNoMem]>;
0566
0567 // Vector Pairwise Maximum and Minimum.
0568 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
0569 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
0570 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
0571 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
0572
0573 // Vector Shifts:
0574 //
0575 // The various saturating and rounding vector shift operations need to be
0576 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
0577 // operation cannot be safely translated to LLVM's shift operators. VSHL can
0578 // be used for both left and right shifts, or even combinations of the two,
0579 // depending on the signs of the shift amounts. It also has well-defined
0580 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
0581 // by constants can be represented with LLVM's shift operators.
0582 //
0583 // The shift counts for these intrinsics are always vectors, even for constant
0584 // shifts, where the constant is replicated. For consistency with VSHL (and
0585 // other variable shift instructions), left shifts have positive shift counts
0586 // and right shifts have negative shift counts. This convention is also used
0587 // for constant right shift intrinsics, and to help preserve sanity, the
0588 // intrinsic names use "shift" instead of either "shl" or "shr". Where
0589 // applicable, signed and unsigned versions of the intrinsics are
0590 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
0591 // such as VQSHLU, take signed operands but produce unsigned results; these
0592 // use a "su" suffix.
0593
0594 // Vector Shift.
0595 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
0596 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
0597
0598 // Vector Rounding Shift.
0599 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
0600 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
0601 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
0602
0603 // Vector Saturating Shift.
0604 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
0605 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
0606 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
0607 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
0608 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
0609 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
0610
0611 // Vector Saturating Rounding Shift.
0612 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
0613 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
0614 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
0615 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
0616 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
0617
0618 // Vector Shift and Insert.
0619 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
0620
0621 // Vector Absolute Value and Saturating Absolute Value.
0622 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
0623 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
0624
0625 // Vector Saturating Negate.
0626 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
0627
0628 // Vector Count Leading Sign/Zero Bits.
0629 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
0630
0631 // Vector Reciprocal Estimate.
0632 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
0633
0634 // Vector Reciprocal Square Root Estimate.
0635 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
0636
0637 // Vector Conversions Between Floating-point and Integer
0638 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
0639 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
0640 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
0641 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
0642 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
0643 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
0644 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
0645 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
0646
0647 // Vector Conversions Between Floating-point and Fixed-point.
0648 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
0649 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
0650 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
0651 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
0652
0653 // Vector Conversions Between Half-Precision and Single-Precision.
0654 def int_arm_neon_vcvtfp2hf
0655 : DefaultAttrsIntrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
0656 def int_arm_neon_vcvthf2fp
0657 : DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
0658
0659 // Narrowing Saturating Vector Moves.
0660 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
0661 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
0662 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
0663
0664 // Vector Table Lookup.
0665 // The first 1-4 arguments are the table.
0666 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
0667 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
0668 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
0669 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
0670
0671 // Vector Table Extension.
0672 // Some elements of the destination vector may not be updated, so the original
0673 // value of that vector is passed as the first argument. The next 1-4
0674 // arguments after that are the table.
0675 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
0676 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
0677 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
0678 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
0679
0680 // Vector and Scalar Rounding.
0681 def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
0682 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
0683 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
0684 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
0685 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
0686 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
0687
0688 // De-interleaving vector loads from N-element structures.
0689 // Source operands are the address and alignment.
0690 def int_arm_neon_vld1 : DefaultAttrsIntrinsic<
0691 [llvm_anyvector_ty], [llvm_anyptr_ty, llvm_i32_ty],
0692 [IntrReadMem, IntrArgMemOnly]>;
0693 def int_arm_neon_vld2 : DefaultAttrsIntrinsic<
0694 [llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty, llvm_i32_ty],
0695 [IntrReadMem, IntrArgMemOnly]>;
0696 def int_arm_neon_vld3 : DefaultAttrsIntrinsic<
0697 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
0698 [llvm_anyptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
0699 def int_arm_neon_vld4 : DefaultAttrsIntrinsic<
0700 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
0701 [llvm_anyptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
0702
0703 def int_arm_neon_vld1x2 : DefaultAttrsIntrinsic<
0704 [llvm_anyvector_ty, LLVMMatchType<0>],
0705 [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>;
0706 def int_arm_neon_vld1x3 : DefaultAttrsIntrinsic<
0707 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
0708 [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>;
0709 def int_arm_neon_vld1x4 : DefaultAttrsIntrinsic<
0710 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
0711 [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>;
0712
0713 // Vector load N-element structure to one lane.
0714 // Source operands are: the address, the N input vectors (since only one
0715 // lane is assigned), the lane number, and the alignment.
0716 def int_arm_neon_vld2lane : DefaultAttrsIntrinsic<
0717 [llvm_anyvector_ty, LLVMMatchType<0>],
0718 [llvm_anyptr_ty, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty,
0719 llvm_i32_ty],
0720 [IntrReadMem, IntrArgMemOnly]>;
0721 def int_arm_neon_vld3lane : DefaultAttrsIntrinsic<
0722 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
0723 [llvm_anyptr_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
0724 llvm_i32_ty, llvm_i32_ty],
0725 [IntrReadMem, IntrArgMemOnly]>;
0726 def int_arm_neon_vld4lane : DefaultAttrsIntrinsic<
0727 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
0728 [llvm_anyptr_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
0729 LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
0730 [IntrReadMem, IntrArgMemOnly]>;
0731
0732 // Vector load N-element structure to all lanes.
0733 // Source operands are the address and alignment.
0734 def int_arm_neon_vld2dup : DefaultAttrsIntrinsic<
0735 [llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty, llvm_i32_ty],
0736 [IntrReadMem, IntrArgMemOnly]>;
0737 def int_arm_neon_vld3dup : DefaultAttrsIntrinsic<
0738 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
0739 [llvm_anyptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
0740 def int_arm_neon_vld4dup : DefaultAttrsIntrinsic<
0741 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
0742 [llvm_anyptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
0743
0744 // Interleaving vector stores from N-element structures.
0745 // Source operands are: the address, the N vectors, and the alignment.
0746 def int_arm_neon_vst1 : DefaultAttrsIntrinsic<
0747 [], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_i32_ty], [IntrArgMemOnly]>;
0748 def int_arm_neon_vst2 : DefaultAttrsIntrinsic<
0749 [], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
0750 [IntrArgMemOnly]>;
0751 def int_arm_neon_vst3 : DefaultAttrsIntrinsic<
0752 [],
0753 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
0754 llvm_i32_ty],
0755 [IntrArgMemOnly]>;
0756 def int_arm_neon_vst4 : DefaultAttrsIntrinsic<
0757 [],
0758 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
0759 LLVMMatchType<1>, llvm_i32_ty],
0760 [IntrArgMemOnly]>;
0761
0762 def int_arm_neon_vst1x2 : DefaultAttrsIntrinsic<
0763 [], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>],
0764 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0765 def int_arm_neon_vst1x3 : DefaultAttrsIntrinsic<
0766 [], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>],
0767 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0768 def int_arm_neon_vst1x4 : DefaultAttrsIntrinsic<
0769 [],
0770 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
0771 LLVMMatchType<1>],
0772 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
0773
0774 // Vector store N-element structure from one lane.
0775 // Source operands are: the address, the N vectors, the lane number, and
0776 // the alignment.
0777 def int_arm_neon_vst2lane : DefaultAttrsIntrinsic<
0778 [],
0779 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty,
0780 llvm_i32_ty],
0781 [IntrArgMemOnly]>;
0782 def int_arm_neon_vst3lane : DefaultAttrsIntrinsic<
0783 [],
0784 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
0785 llvm_i32_ty, llvm_i32_ty],
0786 [IntrArgMemOnly]>;
0787 def int_arm_neon_vst4lane : DefaultAttrsIntrinsic<
0788 [],
0789 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
0790 LLVMMatchType<1>, llvm_i32_ty, llvm_i32_ty],
0791 [IntrArgMemOnly]>;
0792
0793 // Vector bitwise select.
0794 def int_arm_neon_vbsl : DefaultAttrsIntrinsic<
0795 [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
0796 [IntrNoMem]>;
0797
0798
0799 // Crypto instructions
0800 class AES_1Arg_Intrinsic : DefaultAttrsIntrinsic<
0801 [llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
0802 class AES_2Arg_Intrinsic : DefaultAttrsIntrinsic<
0803 [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
0804
0805 class SHA_1Arg_Intrinsic : DefaultAttrsIntrinsic<
0806 [llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
0807 class SHA_2Arg_Intrinsic : DefaultAttrsIntrinsic<
0808 [llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
0809 class SHA_3Arg_i32_Intrinsic : DefaultAttrsIntrinsic<
0810 [llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
0811 class SHA_3Arg_v4i32_Intrinsic : DefaultAttrsIntrinsic<
0812 [llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], [IntrNoMem]>;
0813
0814 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
0815 def int_arm_neon_aese : AES_2Arg_Intrinsic;
0816 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
0817 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
0818 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
0819 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
0820 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
0821 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
0822 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
0823 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
0824 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
0825 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
0826 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
0827 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
0828
0829 def int_arm_neon_vqrdmlah : Neon_3Arg_Intrinsic;
0830 def int_arm_neon_vqrdmlsh : Neon_3Arg_Intrinsic;
0831
0832 // Armv8.2-A dot product instructions
0833 class Neon_Dot_Intrinsic
0834 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0835 [LLVMMatchType<0>, llvm_anyvector_ty,
0836 LLVMMatchType<1>],
0837 [IntrNoMem]>;
0838 def int_arm_neon_udot : Neon_Dot_Intrinsic;
0839 def int_arm_neon_sdot : Neon_Dot_Intrinsic;
0840
0841 // v8.6-A Matrix Multiply Intrinsics
0842 class Neon_MatMul_Intrinsic
0843 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0844 [LLVMMatchType<0>, llvm_anyvector_ty,
0845 LLVMMatchType<1>],
0846 [IntrNoMem]>;
0847 def int_arm_neon_ummla : Neon_MatMul_Intrinsic;
0848 def int_arm_neon_smmla : Neon_MatMul_Intrinsic;
0849 def int_arm_neon_usmmla : Neon_MatMul_Intrinsic;
0850 def int_arm_neon_usdot : Neon_Dot_Intrinsic;
0851
0852 // v8.6-A Bfloat Intrinsics
0853 def int_arm_neon_vcvtfp2bf
0854 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v4f32_ty], [IntrNoMem]>;
0855 def int_arm_neon_vcvtbfp2bf
0856 : DefaultAttrsIntrinsic<[llvm_bfloat_ty], [llvm_float_ty], [IntrNoMem]>;
0857
0858 def int_arm_neon_bfdot : Neon_Dot_Intrinsic;
0859 def int_arm_neon_bfmmla
0860 : DefaultAttrsIntrinsic<[llvm_v4f32_ty],
0861 [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty],
0862 [IntrNoMem]>;
0863
0864 class Neon_BF16FML_Intrinsic
0865 : DefaultAttrsIntrinsic<[llvm_v4f32_ty],
0866 [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty],
0867 [IntrNoMem]>;
0868 def int_arm_neon_bfmlalb : Neon_BF16FML_Intrinsic;
0869 def int_arm_neon_bfmlalt : Neon_BF16FML_Intrinsic;
0870
0871 def int_arm_cls: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
0872 [IntrNoMem]>;
0873 def int_arm_cls64: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i64_ty],
0874 [IntrNoMem]>;
0875
0876 def int_arm_mve_vctp8 : DefaultAttrsIntrinsic<[llvm_v16i1_ty], [llvm_i32_ty],
0877 [IntrNoMem]>;
0878 def int_arm_mve_vctp16 : DefaultAttrsIntrinsic<[llvm_v8i1_ty], [llvm_i32_ty],
0879 [IntrNoMem]>;
0880 def int_arm_mve_vctp32 : DefaultAttrsIntrinsic<[llvm_v4i1_ty], [llvm_i32_ty],
0881 [IntrNoMem]>;
0882 def int_arm_mve_vctp64 : DefaultAttrsIntrinsic<[llvm_v2i1_ty], [llvm_i32_ty],
0883 [IntrNoMem]>;
0884
0885 // v8.3-A Floating-point complex add
0886 def int_arm_neon_vcadd_rot90 : Neon_2Arg_Intrinsic;
0887 def int_arm_neon_vcadd_rot270 : Neon_2Arg_Intrinsic;
0888
0889 // GNU eabi mcount
0890 // TODO: Add applicable default attributes.
0891 def int_arm_gnu_eabi_mcount : Intrinsic<[], [], []>;
0892
0893 def int_arm_mve_pred_i2v : DefaultAttrsIntrinsic<
0894 [llvm_anyvector_ty], [llvm_i32_ty], [IntrNoMem]>;
0895 def int_arm_mve_pred_v2i : DefaultAttrsIntrinsic<
0896 [llvm_i32_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0897 def int_arm_mve_vreinterpretq : DefaultAttrsIntrinsic<
0898 [llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
0899
0900 def int_arm_mve_min_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0901 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0902 llvm_anyvector_ty, LLVMMatchType<0>],
0903 [IntrNoMem]>;
0904 def int_arm_mve_max_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0905 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0906 llvm_anyvector_ty, LLVMMatchType<0>],
0907 [IntrNoMem]>;
0908 def int_arm_mve_abd_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0909 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0910 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0911 def int_arm_mve_add_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0912 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0913 [IntrNoMem]>;
0914 def int_arm_mve_and_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0915 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0916 [IntrNoMem]>;
0917 def int_arm_mve_bic_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0918 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0919 [IntrNoMem]>;
0920 def int_arm_mve_eor_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0921 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0922 [IntrNoMem]>;
0923 def int_arm_mve_orn_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0924 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0925 [IntrNoMem]>;
0926 def int_arm_mve_orr_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0927 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0928 [IntrNoMem]>;
0929 def int_arm_mve_sub_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0930 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0931 [IntrNoMem]>;
0932 def int_arm_mve_mul_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0933 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0934 [IntrNoMem]>;
0935 def int_arm_mve_mulh_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0936 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0937 llvm_anyvector_ty, LLVMMatchType<0>],
0938 [IntrNoMem]>;
0939 def int_arm_mve_qdmulh_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0940 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0941 [IntrNoMem]>;
0942 def int_arm_mve_rmulh_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0943 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0944 llvm_anyvector_ty, LLVMMatchType<0>],
0945 [IntrNoMem]>;
0946 def int_arm_mve_qrdmulh_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0947 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
0948 [IntrNoMem]>;
0949 def int_arm_mve_mull_int_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0950 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */,
0951 llvm_i32_ty /* top */, llvm_anyvector_ty, LLVMMatchType<0>],
0952 [IntrNoMem]>;
0953 def int_arm_mve_mull_poly_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0954 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
0955 LLVMMatchType<0>],
0956 [IntrNoMem]>;
0957 def int_arm_mve_qadd_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0958 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0959 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0960 def int_arm_mve_hadd_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0961 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0962 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0963 def int_arm_mve_rhadd_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0964 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0965 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0966 def int_arm_mve_qsub_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0967 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0968 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0969 def int_arm_mve_hsub_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0970 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
0971 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
0972 def int_arm_mve_vmina_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0973 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
0974 [IntrNoMem]>;
0975 def int_arm_mve_vmaxa_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0976 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
0977 [IntrNoMem]>;
0978 def int_arm_mve_vminnma_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0979 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
0980 [IntrNoMem]>;
0981 def int_arm_mve_vmaxnma_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
0982 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
0983 [IntrNoMem]>;
0984
0985 multiclass MVEPredicated<list<LLVMType> rets, list<LLVMType> params,
0986 LLVMType pred = llvm_anyvector_ty,
0987 list<IntrinsicProperty> props = [IntrNoMem],
0988 list<SDNodeProperty> sdprops = []> {
0989 def "": DefaultAttrsIntrinsic<rets, params, props, "", sdprops>;
0990 def _predicated: DefaultAttrsIntrinsic<rets, params # [pred], props, "",
0991 sdprops>;
0992 }
0993 multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params,
0994 LLVMType pred = llvm_anyvector_ty,
0995 list<IntrinsicProperty> props = [IntrNoMem]> {
0996 def "": DefaultAttrsIntrinsic<rets, params, props>;
0997 def _predicated: DefaultAttrsIntrinsic<rets, params # [pred,
0998 !if(!eq(rets[0], llvm_anyvector_ty),
0999 LLVMMatchType<0>, rets[0])], props>;
1000 }
1001
1002 multiclass MVE_minmaxv {
1003 defm v: MVEPredicated<[llvm_i32_ty],
1004 [llvm_i32_ty, llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
1005 defm av: MVEPredicated<[llvm_i32_ty],
1006 [llvm_i32_ty, llvm_anyvector_ty]>;
1007 defm nmv: MVEPredicated<[llvm_anyfloat_ty],
1008 [LLVMMatchType<0>, llvm_anyvector_ty]>;
1009 defm nmav: MVEPredicated<[llvm_anyfloat_ty],
1010 [LLVMMatchType<0>, llvm_anyvector_ty]>;
1011 }
1012 defm int_arm_mve_min: MVE_minmaxv;
1013 defm int_arm_mve_max: MVE_minmaxv;
1014
1015 defm int_arm_mve_addv: MVEPredicated<[llvm_i32_ty],
1016 [llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
1017 defm int_arm_mve_addlv: MVEPredicated<[llvm_i64_ty],
1018 [llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
1019
1020 // Intrinsic with a predicated and a non-predicated case. The predicated case
1021 // has two additional parameters: inactive (the value for inactive lanes, can
1022 // be undef) and predicate.
1023 multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags,
1024 list<LLVMType> params, LLVMType inactive,
1025 LLVMType predicate,
1026 list<IntrinsicProperty> props = [IntrNoMem]> {
1027 def "": DefaultAttrsIntrinsic<rets, flags # params, props>;
1028 def _predicated: DefaultAttrsIntrinsic<
1029 rets, flags # [inactive] # params # [predicate], props>;
1030 }
1031
1032 defm int_arm_mve_vcvt_narrow: MVEPredicated<[llvm_v8f16_ty],
1033 [llvm_v8f16_ty, llvm_v4f32_ty, llvm_i32_ty], llvm_v4i1_ty>;
1034 defm int_arm_mve_vcvt_widen: MVEMXPredicated<[llvm_v4f32_ty], [],
1035 [llvm_v8f16_ty, llvm_i32_ty], llvm_v4f32_ty, llvm_v4i1_ty>;
1036
1037 defm int_arm_mve_vldr_gather_base: MVEPredicated<
1038 [llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty],
1039 llvm_anyvector_ty, [IntrReadMem], [SDNPMemOperand]>;
1040 defm int_arm_mve_vldr_gather_base_wb: MVEPredicated<
1041 [llvm_anyvector_ty, llvm_anyvector_ty],
1042 [LLVMMatchType<1>, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem],
1043 [SDNPMemOperand]>;
1044 defm int_arm_mve_vstr_scatter_base: MVEPredicated<
1045 [], [llvm_anyvector_ty, llvm_i32_ty, llvm_anyvector_ty],
1046 llvm_anyvector_ty, [IntrWriteMem], [SDNPMemOperand]>;
1047 defm int_arm_mve_vstr_scatter_base_wb: MVEPredicated<
1048 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty],
1049 llvm_anyvector_ty, [IntrWriteMem], [SDNPMemOperand]>;
1050
1051 // gather_offset takes three i32 parameters. The first is the size of
1052 // memory element loaded, in bits. The second is a left bit shift to
1053 // apply to each offset in the vector parameter (must be either 0, or
1054 // correspond to the element size of the destination vector type). The
1055 // last is 1 to indicate zero extension (if the load is widening), or
1056 // 0 for sign extension.
1057 //
1058 // scatter_offset has the first two of those parameters, but since it
1059 // narrows rather than widening, it doesn't have the last one.
1060 defm int_arm_mve_vldr_gather_offset: MVEPredicated<
1061 [llvm_anyvector_ty], [llvm_anyptr_ty, llvm_anyvector_ty,
1062 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem],
1063 [SDNPMemOperand]>;
1064 defm int_arm_mve_vstr_scatter_offset: MVEPredicated<
1065 [], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_anyvector_ty,
1066 llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrWriteMem],
1067 [SDNPMemOperand]>;
1068
1069 def int_arm_mve_shl_imm_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1070 [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1071 [IntrNoMem]>;
1072 def int_arm_mve_shr_imm_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1073 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, // extra i32 is unsigned flag
1074 llvm_anyvector_ty, LLVMMatchType<0>],
1075 [IntrNoMem]>;
1076
1077 defm int_arm_mve_vqshl_imm: MVEPredicatedM<[llvm_anyvector_ty],
1078 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>;
1079 defm int_arm_mve_vrshr_imm: MVEPredicatedM<[llvm_anyvector_ty],
1080 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>;
1081 defm int_arm_mve_vqshlu_imm: MVEPredicatedM<[llvm_anyvector_ty],
1082 [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/]>;
1083 defm int_arm_mve_vshll_imm: MVEPredicatedM<[llvm_anyvector_ty],
1084 [llvm_anyvector_ty, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/,
1085 llvm_i32_ty /*top-half*/]>;
1086
1087 defm int_arm_mve_vsli: MVEPredicated<
1088 [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>;
1089 defm int_arm_mve_vsri: MVEPredicated<
1090 [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>;
1091
1092 defm int_arm_mve_vshrn: MVEPredicated<
1093 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty,
1094 llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/,
1095 llvm_i32_ty /*unsigned-out*/, llvm_i32_ty /*unsigned-in*/,
1096 llvm_i32_ty /*top-half*/]>;
1097
1098 defm int_arm_mve_vshl_scalar: MVEPredicated<
1099 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/,
1100 llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>;
1101 defm int_arm_mve_vshl_vector: MVEPredicatedM<
1102 [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty /*shiftcounts*/,
1103 llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>;
1104
1105 // MVE scalar shifts.
1106 class ARM_MVE_qrshift_single<list<LLVMType> value,
1107 list<LLVMType> saturate = []> :
1108 DefaultAttrsIntrinsic<value, value # [llvm_i32_ty] # saturate, [IntrNoMem]>;
1109 multiclass ARM_MVE_qrshift<list<LLVMType> saturate = []> {
1110 // Most of these shifts come in 32- and 64-bit versions. But only
1111 // the 64-bit ones have the extra saturation argument (if any).
1112 def "": ARM_MVE_qrshift_single<[llvm_i32_ty]>;
1113 def l: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty], saturate>;
1114 }
1115 defm int_arm_mve_urshr: ARM_MVE_qrshift;
1116 defm int_arm_mve_uqshl: ARM_MVE_qrshift;
1117 defm int_arm_mve_srshr: ARM_MVE_qrshift;
1118 defm int_arm_mve_sqshl: ARM_MVE_qrshift;
1119 defm int_arm_mve_uqrshl: ARM_MVE_qrshift<[llvm_i32_ty]>;
1120 defm int_arm_mve_sqrshr: ARM_MVE_qrshift<[llvm_i32_ty]>;
1121 // LSLL and ASRL only have 64-bit versions, not 32.
1122 def int_arm_mve_lsll: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
1123 def int_arm_mve_asrl: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
1124
1125 def int_arm_mve_vabd: DefaultAttrsIntrinsic<
1126 [llvm_anyvector_ty],
1127 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1128 [IntrNoMem]>;
1129 def int_arm_mve_vadc: DefaultAttrsIntrinsic<
1130 [llvm_anyvector_ty, llvm_i32_ty],
1131 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
1132 def int_arm_mve_vsbc: DefaultAttrsIntrinsic<
1133 [llvm_anyvector_ty, llvm_i32_ty],
1134 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
1135 def int_arm_mve_vadc_predicated: DefaultAttrsIntrinsic<
1136 [llvm_anyvector_ty, llvm_i32_ty],
1137 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1138 llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>;
1139 def int_arm_mve_vsbc_predicated: DefaultAttrsIntrinsic<
1140 [llvm_anyvector_ty, llvm_i32_ty],
1141 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1142 llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>;
1143 def int_arm_mve_vshlc: DefaultAttrsIntrinsic<
1144 [llvm_i32_ty /* bits shifted out */, llvm_anyvector_ty],
1145 [LLVMMatchType<0>, llvm_i32_ty /* bits shifted in */,
1146 llvm_i32_ty /* shift count */], [IntrNoMem]>;
1147 def int_arm_mve_vshlc_predicated: DefaultAttrsIntrinsic<
1148 [llvm_i32_ty /* bits shifted out */, llvm_anyvector_ty],
1149 [LLVMMatchType<0>, llvm_i32_ty /* bits shifted in */,
1150 llvm_i32_ty /* shift count */, llvm_anyvector_ty], [IntrNoMem]>;
1151 def int_arm_mve_vmulh: DefaultAttrsIntrinsic<
1152 [llvm_anyvector_ty],
1153 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1154 [IntrNoMem]>;
1155 def int_arm_mve_vqdmulh: DefaultAttrsIntrinsic<
1156 [llvm_anyvector_ty],
1157 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
1158 def int_arm_mve_vhadd: DefaultAttrsIntrinsic<
1159 [llvm_anyvector_ty],
1160 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1161 [IntrNoMem]>;
1162 def int_arm_mve_vrhadd: DefaultAttrsIntrinsic<
1163 [llvm_anyvector_ty],
1164 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1165 [IntrNoMem]>;
1166 def int_arm_mve_vhsub: DefaultAttrsIntrinsic<
1167 [llvm_anyvector_ty],
1168 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1169 [IntrNoMem]>;
1170 def int_arm_mve_vrmulh: DefaultAttrsIntrinsic<
1171 [llvm_anyvector_ty],
1172 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1173 [IntrNoMem]>;
1174 def int_arm_mve_vqrdmulh: DefaultAttrsIntrinsic<
1175 [llvm_anyvector_ty],
1176 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
1177 def int_arm_mve_vmull: DefaultAttrsIntrinsic<
1178 [llvm_anyvector_ty],
1179 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */,
1180 llvm_i32_ty /* top */], [IntrNoMem]>;
1181 def int_arm_mve_vmull_poly: DefaultAttrsIntrinsic<
1182 [llvm_anyvector_ty],
1183 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrNoMem]>;
1184
1185 // The first two parameters are compile-time constants:
1186 // * Halving: 0 means halving (vhcaddq), 1 means non-halving (vcaddq)
1187 // instruction. Note: the flag is inverted to match the corresponding
1188 // bit in the instruction encoding
1189 // * Rotation angle: 0 mean 90 deg, 1 means 180 deg
1190 defm int_arm_mve_vcaddq : MVEMXPredicated<
1191 [llvm_anyvector_ty],
1192 [llvm_i32_ty, llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
1193 LLVMMatchType<0>, llvm_anyvector_ty>;
1194
1195 // The first operand of the following two intrinsics is the rotation angle
1196 // (must be a compile-time constant):
1197 // 0 - 0 deg
1198 // 1 - 90 deg
1199 // 2 - 180 deg
1200 // 3 - 270 deg
1201 defm int_arm_mve_vcmulq : MVEMXPredicated<
1202 [llvm_anyvector_ty],
1203 [llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
1204 LLVMMatchType<0>, llvm_anyvector_ty>;
1205
1206 defm int_arm_mve_vcmlaq : MVEPredicated<
1207 [llvm_anyvector_ty],
1208 [llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
1209 llvm_anyvector_ty>;
1210
1211 def int_arm_mve_vld2q: DefaultAttrsIntrinsic<
1212 [llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty],
1213 [IntrReadMem, IntrArgMemOnly]>;
1214 def int_arm_mve_vld4q: DefaultAttrsIntrinsic<
1215 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
1216 [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>;
1217
1218 def int_arm_mve_vst2q: DefaultAttrsIntrinsic<
1219 [], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
1220 [IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
1221 def int_arm_mve_vst4q: DefaultAttrsIntrinsic<
1222 [],
1223 [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
1224 LLVMMatchType<1>, llvm_i32_ty],
1225 [IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
1226
1227 // MVE vector absolute difference and accumulate across vector
1228 // The first operand is an 'unsigned' flag. The remaining operands are:
1229 // * accumulator
1230 // * first vector operand
1231 // * second vector operand
1232 // * mask (only in predicated versions)
1233 defm int_arm_mve_vabav: MVEPredicated<
1234 [llvm_i32_ty],
1235 [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], llvm_anyvector_ty>;
1236
1237 // The following 3 intrinsics are MVE vector reductions with two vector
1238 // operands.
1239 // The first 3 operands are boolean flags (must be compile-time constants):
1240 // * unsigned - the instruction operates on vectors of unsigned values and
1241 // unsigned scalars
1242 // * subtract - the instruction performs subtraction after multiplication of
1243 // lane pairs (e.g., vmlsdav vs vmladav)
1244 // * exchange - the instruction exchanges successive even and odd lanes of
1245 // the first operands before multiplication of lane pairs
1246 // (e.g., vmladavx vs vmladav)
1247 // The remaining operands are:
1248 // * accumulator
1249 // * first vector operand
1250 // * second vector operand
1251 // * mask (only in predicated versions)
1252
1253 // Version with 32-bit result, vml{a,s}dav[a][x]
1254 defm int_arm_mve_vmldava: MVEPredicated<
1255 [llvm_i32_ty],
1256 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1257 llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1258 llvm_anyvector_ty>;
1259
1260 // Version with 64-bit result, vml{a,s}ldav[a][x]
1261 defm int_arm_mve_vmlldava: MVEPredicated<
1262 [llvm_i32_ty, llvm_i32_ty],
1263 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1264 llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1265 llvm_anyvector_ty>;
1266
1267 // Version with 72-bit rounded result, vrml{a,s}ldavh[a][x]
1268 defm int_arm_mve_vrmlldavha: MVEPredicated<
1269 [llvm_i32_ty, llvm_i32_ty],
1270 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1271 llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1272 llvm_anyvector_ty>;
1273
1274 defm int_arm_mve_vidup: MVEMXPredicated<
1275 [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1276 [llvm_i32_ty /* base */, llvm_i32_ty /* step */],
1277 LLVMMatchType<0>, llvm_anyvector_ty>;
1278 defm int_arm_mve_vddup: MVEMXPredicated<
1279 [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1280 [llvm_i32_ty /* base */, llvm_i32_ty /* step */],
1281 LLVMMatchType<0>, llvm_anyvector_ty>;
1282 defm int_arm_mve_viwdup: MVEMXPredicated<
1283 [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1284 [llvm_i32_ty /* base */, llvm_i32_ty /* limit */, llvm_i32_ty /* step */],
1285 LLVMMatchType<0>, llvm_anyvector_ty>;
1286 defm int_arm_mve_vdwdup: MVEMXPredicated<
1287 [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1288 [llvm_i32_ty /* base */, llvm_i32_ty /* limit */, llvm_i32_ty /* step */],
1289 LLVMMatchType<0>, llvm_anyvector_ty>;
1290
1291 // Flags:
1292 // * unsigned
1293 defm int_arm_mve_vcvt_fix: MVEMXPredicated<
1294 [llvm_anyvector_ty /* output */], [llvm_i32_ty],
1295 [llvm_anyvector_ty /* input vector */, llvm_i32_ty /* scale */],
1296 LLVMMatchType<0>, llvm_anyvector_ty>;
1297
1298 def int_arm_mve_vcvt_fp_int_predicated: DefaultAttrsIntrinsic<
1299 [llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty /* unsigned */,
1300 llvm_anyvector_ty /* predicate */, LLVMMatchType<0> /* inactive */],
1301 [IntrNoMem]>;
1302
1303 foreach suffix = ["a","n","p","m"] in {
1304 defm "int_arm_mve_vcvt"#suffix: MVEMXPredicated<
1305 [llvm_anyvector_ty /* output */], [llvm_i32_ty /* unsigned */],
1306 [llvm_anyvector_ty /* input */], LLVMMatchType<0>, llvm_anyvector_ty>;
1307 }
1308
1309 def int_arm_mve_vrintn: DefaultAttrsIntrinsic<
1310 [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
1311 def int_arm_mve_vcls: DefaultAttrsIntrinsic<
1312 [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
1313
1314 defm int_arm_mve_vbrsr: MVEMXPredicated<
1315 [llvm_anyvector_ty], [],
1316 [LLVMMatchType<0>, llvm_i32_ty], LLVMMatchType<0>, llvm_anyvector_ty>;
1317
1318 def int_arm_mve_vqdmull: DefaultAttrsIntrinsic<
1319 [llvm_anyvector_ty],
1320 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
1321 [IntrNoMem]>;
1322 def int_arm_mve_vqdmull_predicated: DefaultAttrsIntrinsic<
1323 [llvm_anyvector_ty],
1324 [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
1325 LLVMMatchType<0>],
1326 [IntrNoMem]>;
1327
1328 class MVESimpleUnaryPredicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1329 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
1330
1331 def int_arm_mve_mvn_predicated: MVESimpleUnaryPredicated;
1332 def int_arm_mve_abs_predicated: MVESimpleUnaryPredicated;
1333 def int_arm_mve_neg_predicated: MVESimpleUnaryPredicated;
1334 def int_arm_mve_qabs_predicated: MVESimpleUnaryPredicated;
1335 def int_arm_mve_qneg_predicated: MVESimpleUnaryPredicated;
1336 def int_arm_mve_clz_predicated: MVESimpleUnaryPredicated;
1337 def int_arm_mve_cls_predicated: MVESimpleUnaryPredicated;
1338 def int_arm_mve_vrintz_predicated: MVESimpleUnaryPredicated;
1339 def int_arm_mve_vrintm_predicated: MVESimpleUnaryPredicated;
1340 def int_arm_mve_vrintp_predicated: MVESimpleUnaryPredicated;
1341 def int_arm_mve_vrinta_predicated: MVESimpleUnaryPredicated;
1342 def int_arm_mve_vrintx_predicated: MVESimpleUnaryPredicated;
1343 def int_arm_mve_vrintn_predicated: MVESimpleUnaryPredicated;
1344
1345 def int_arm_mve_vrev_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1346 [LLVMMatchType<0>, llvm_i32_ty /* size to reverse */,
1347 llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
1348
1349 def int_arm_mve_vmovl_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1350 [llvm_anyvector_ty, llvm_i32_ty /* unsigned */, llvm_i32_ty /* top half */,
1351 llvm_anyvector_ty /* predicate */, LLVMMatchType<0>], [IntrNoMem]>;
1352 def int_arm_mve_vmovn_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1353 [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i32_ty /* top half */,
1354 llvm_anyvector_ty /* predicate */], [IntrNoMem]>;
1355
1356 def int_arm_mve_vqmovn: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1357 [LLVMMatchType<0>, llvm_anyvector_ty,
1358 llvm_i32_ty /* unsigned output */, llvm_i32_ty /* unsigned input */,
1359 llvm_i32_ty /* top half */], [IntrNoMem]>;
1360 def int_arm_mve_vqmovn_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1361 [LLVMMatchType<0>, llvm_anyvector_ty,
1362 llvm_i32_ty /* unsigned output */, llvm_i32_ty /* unsigned input */,
1363 llvm_i32_ty /* top half */, llvm_anyvector_ty /* pred */], [IntrNoMem]>;
1364
1365 // fma_predicated returns the add operand for disabled lanes.
1366 def int_arm_mve_fma_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1367 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1368 LLVMMatchType<0> /* addend */, llvm_anyvector_ty /* pred */], [IntrNoMem]>;
1369 def int_arm_mve_vmla_n_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1370 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1371 llvm_i32_ty /* mult op #2 (scalar) */, llvm_anyvector_ty /* pred */],
1372 [IntrNoMem]>;
1373 def int_arm_mve_vmlas_n_predicated: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
1374 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1375 llvm_i32_ty /* addend (scalar) */, llvm_anyvector_ty /* pred */],
1376 [IntrNoMem]>;
1377
1378 defm int_arm_mve_vqdmlah: MVEPredicated<[llvm_anyvector_ty],
1379 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1380 llvm_i32_ty /* mult op #2 (scalar) */]>;
1381 defm int_arm_mve_vqrdmlah: MVEPredicated<[llvm_anyvector_ty],
1382 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1383 llvm_i32_ty /* mult op #2 (scalar) */]>;
1384 defm int_arm_mve_vqdmlash: MVEPredicated<[llvm_anyvector_ty],
1385 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1386 llvm_i32_ty /* addend (scalar) */]>;
1387 defm int_arm_mve_vqrdmlash: MVEPredicated<[llvm_anyvector_ty],
1388 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1389 llvm_i32_ty /* addend (scalar) */]>;
1390
1391 defm int_arm_mve_vqdmlad: MVEPredicated<[llvm_anyvector_ty],
1392 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1393 llvm_i32_ty /* exchange */, llvm_i32_ty /* round */,
1394 llvm_i32_ty /* subtract */]>;
1395
1396 // CDE (Custom Datapath Extension)
1397
1398 multiclass CDEGPRIntrinsics<list<LLVMType> args> {
1399 def "" : DefaultAttrsIntrinsic<
1400 [llvm_i32_ty],
1401 !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1402 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1403 def a : DefaultAttrsIntrinsic<
1404 [llvm_i32_ty],
1405 !listconcat([llvm_i32_ty /* coproc */, llvm_i32_ty /* acc */], args,
1406 [llvm_i32_ty /* imm */]),
1407 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1408
1409 def d: DefaultAttrsIntrinsic<
1410 [llvm_i32_ty /* lo */, llvm_i32_ty /* hi */],
1411 !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1412 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1413 def da: DefaultAttrsIntrinsic<
1414 [llvm_i32_ty /* lo */, llvm_i32_ty /* hi */],
1415 !listconcat([llvm_i32_ty /* coproc */, llvm_i32_ty /* acc_lo */,
1416 llvm_i32_ty /* acc_hi */], args, [llvm_i32_ty /* imm */]),
1417 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 3)>>]>;
1418 }
1419
1420 defm int_arm_cde_cx1: CDEGPRIntrinsics<[]>;
1421 defm int_arm_cde_cx2: CDEGPRIntrinsics<[llvm_i32_ty]>;
1422 defm int_arm_cde_cx3: CDEGPRIntrinsics<[llvm_i32_ty, llvm_i32_ty]>;
1423
1424 multiclass CDEVCXIntrinsics<list<LLVMType> args> {
1425 def "" : DefaultAttrsIntrinsic<
1426 [llvm_anyfloat_ty],
1427 !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1428 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1429 def a : DefaultAttrsIntrinsic<
1430 [llvm_anyfloat_ty],
1431 !listconcat([llvm_i32_ty /* coproc */, LLVMMatchType<0> /* acc */],
1432 args, [llvm_i32_ty /* imm */]),
1433 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1434 }
1435
1436 defm int_arm_cde_vcx1 : CDEVCXIntrinsics<[]>;
1437 defm int_arm_cde_vcx2 : CDEVCXIntrinsics<[LLVMMatchType<0>]>;
1438 defm int_arm_cde_vcx3 : CDEVCXIntrinsics<[LLVMMatchType<0>, LLVMMatchType<0>]>;
1439
1440 multiclass CDEVCXVecIntrinsics<list<LLVMType> args> {
1441 def "" : DefaultAttrsIntrinsic<
1442 [llvm_v16i8_ty],
1443 !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1444 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1445 def a : DefaultAttrsIntrinsic<
1446 [llvm_v16i8_ty],
1447 !listconcat([llvm_i32_ty /* coproc */, llvm_v16i8_ty /* acc */],
1448 args, [llvm_i32_ty /* imm */]),
1449 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1450
1451 def _predicated : DefaultAttrsIntrinsic<
1452 [llvm_anyvector_ty],
1453 !listconcat([llvm_i32_ty /* coproc */, LLVMMatchType<0> /* inactive */],
1454 args, [llvm_i32_ty /* imm */, llvm_anyvector_ty /* mask */]),
1455 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1456 def a_predicated : DefaultAttrsIntrinsic<
1457 [llvm_anyvector_ty],
1458 !listconcat([llvm_i32_ty /* coproc */, LLVMMatchType<0> /* acc */],
1459 args, [llvm_i32_ty /* imm */, llvm_anyvector_ty /* mask */]),
1460 [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1461 }
1462
1463 defm int_arm_cde_vcx1q : CDEVCXVecIntrinsics<[]>;
1464 defm int_arm_cde_vcx2q : CDEVCXVecIntrinsics<[llvm_v16i8_ty]>;
1465 defm int_arm_cde_vcx3q : CDEVCXVecIntrinsics<[llvm_v16i8_ty, llvm_v16i8_ty]>;
1466
1467 } // end TargetPrefix
