EIC code displayed by LXR |
|
|
|
|||
File indexing completed on 2026-05-10 08:43:50
0001 //===-- riscv.h - Generic JITLink riscv edge kinds, utilities -*- C++ -*-===// 0002 // 0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 0004 // See https://llvm.org/LICENSE.txt for license information. 0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 0006 // 0007 //===----------------------------------------------------------------------===// 0008 // 0009 // Generic utilities for graphs representing riscv objects. 0010 // 0011 //===----------------------------------------------------------------------===// 0012 0013 #ifndef LLVM_EXECUTIONENGINE_JITLINK_RISCV_H 0014 #define LLVM_EXECUTIONENGINE_JITLINK_RISCV_H 0015 0016 #include "llvm/ExecutionEngine/JITLink/JITLink.h" 0017 0018 namespace llvm { 0019 namespace jitlink { 0020 namespace riscv { 0021 0022 /// Represents riscv fixups. Ordered in the same way as the relocations in 0023 /// include/llvm/BinaryFormat/ELFRelocs/RISCV.def. 0024 enum EdgeKind_riscv : Edge::Kind { 0025 0026 // TODO: Capture and replace to generic fixups 0027 /// A plain 32-bit pointer value relocation 0028 /// 0029 /// Fixup expression: 0030 /// Fixup <= Target + Addend : uint32 0031 /// 0032 R_RISCV_32 = Edge::FirstRelocation, 0033 0034 /// A plain 64-bit pointer value relocation 0035 /// 0036 /// Fixup expression: 0037 /// Fixup <- Target + Addend : uint32 0038 /// 0039 R_RISCV_64, 0040 0041 /// PC-relative branch pointer value relocation 0042 /// 0043 /// Fixup expression: 0044 /// Fixup <- (Target - Fixup + Addend) 0045 /// 0046 R_RISCV_BRANCH, 0047 0048 /// High 20 bits of PC-relative jump pointer value relocation 0049 /// 0050 /// Fixup expression: 0051 /// Fixup <- Target - Fixup + Addend 0052 /// 0053 R_RISCV_JAL, 0054 0055 /// PC relative call 0056 /// 0057 /// Fixup expression: 0058 /// Fixup <- (Target - Fixup + Addend) 0059 R_RISCV_CALL, 0060 0061 /// PC relative call by PLT 0062 /// 0063 /// Fixup expression: 0064 /// Fixup <- (Target - Fixup + Addend) 0065 R_RISCV_CALL_PLT, 0066 0067 /// PC relative GOT offset 0068 /// 0069 /// Fixup expression: 0070 /// Fixup <- (GOT - Fixup + Addend) >> 12 0071 R_RISCV_GOT_HI20, 0072 0073 /// High 20 bits of PC relative relocation 0074 /// 0075 /// Fixup expression: 0076 /// Fixup <- (Target - Fixup + Addend + 0x800) >> 12 0077 R_RISCV_PCREL_HI20, 0078 0079 /// Low 12 bits of PC relative relocation, used by I type instruction format 0080 /// 0081 /// Fixup expression: 0082 /// Fixup <- (Target - Fixup + Addend) & 0xFFF 0083 R_RISCV_PCREL_LO12_I, 0084 0085 /// Low 12 bits of PC relative relocation, used by S type instruction format 0086 /// 0087 /// Fixup expression: 0088 /// Fixup <- (Target - Fixup + Addend) & 0xFFF 0089 R_RISCV_PCREL_LO12_S, 0090 0091 /// High 20 bits of 32-bit pointer value relocation 0092 /// 0093 /// Fixup expression 0094 /// Fixup <- (Target + Addend + 0x800) >> 12 0095 R_RISCV_HI20, 0096 0097 /// Low 12 bits of 32-bit pointer value relocation 0098 /// 0099 /// Fixup expression 0100 /// Fixup <- (Target + Addend) & 0xFFF 0101 R_RISCV_LO12_I, 0102 0103 /// Low 12 bits of 32-bit pointer value relocation, used by S type instruction 0104 /// format 0105 /// 0106 /// Fixup expression 0107 /// Fixup <- (Target + Addend) & 0xFFF 0108 R_RISCV_LO12_S, 0109 0110 /// 8 bits label addition 0111 /// 0112 /// Fixup expression 0113 /// Fixup <- (Target + *{1}Fixup + Addend) 0114 R_RISCV_ADD8, 0115 0116 /// 16 bits label addition 0117 /// 0118 /// Fixup expression 0119 /// Fixup <- (Target + *{2}Fixup + Addend) 0120 R_RISCV_ADD16, 0121 0122 /// 32 bits label addition 0123 /// 0124 /// Fixup expression: 0125 /// Fixup <- (Target + *{4}Fixup + Addend) 0126 R_RISCV_ADD32, 0127 0128 /// 64 bits label addition 0129 /// 0130 /// Fixup expression: 0131 /// Fixup <- (Target + *{8}Fixup + Addend) 0132 R_RISCV_ADD64, 0133 0134 /// 8 bits label subtraction 0135 /// 0136 /// Fixup expression 0137 /// Fixup <- (Target - *{1}Fixup - Addend) 0138 R_RISCV_SUB8, 0139 0140 /// 16 bits label subtraction 0141 /// 0142 /// Fixup expression 0143 /// Fixup <- (Target - *{2}Fixup - Addend) 0144 R_RISCV_SUB16, 0145 0146 /// 32 bits label subtraction 0147 /// 0148 /// Fixup expression 0149 /// Fixup <- (Target - *{4}Fixup - Addend) 0150 R_RISCV_SUB32, 0151 0152 /// 64 bits label subtraction 0153 /// 0154 /// Fixup expression 0155 /// Fixup <- (Target - *{8}Fixup - Addend) 0156 R_RISCV_SUB64, 0157 0158 /// 8-bit PC-relative branch offset 0159 /// 0160 /// Fixup expression: 0161 /// Fixup <- (Target - Fixup + Addend) 0162 R_RISCV_RVC_BRANCH, 0163 0164 /// 11-bit PC-relative jump offset 0165 /// 0166 /// Fixup expression: 0167 /// Fixup <- (Target - Fixup + Addend) 0168 R_RISCV_RVC_JUMP, 0169 0170 /// 6 bits label subtraction 0171 /// 0172 /// Fixup expression 0173 /// Fixup <- (Target - *{1}Fixup - Addend) 0174 R_RISCV_SUB6, 0175 0176 /// Local label assignment 0177 /// 0178 /// Fixup expression: 0179 /// Fixup <- (Target + Addend) 0180 R_RISCV_SET6, 0181 0182 /// Local label assignment 0183 /// 0184 /// Fixup expression: 0185 /// Fixup <- (Target + Addend) 0186 R_RISCV_SET8, 0187 0188 /// Local label assignment 0189 /// 0190 /// Fixup expression: 0191 /// Fixup <- (Target + Addend) 0192 R_RISCV_SET16, 0193 0194 /// Local label assignment 0195 /// 0196 /// Fixup expression: 0197 /// Fixup <- (Target + Addend) 0198 R_RISCV_SET32, 0199 0200 /// 32 bits PC relative relocation 0201 /// 0202 /// Fixup expression: 0203 /// Fixup <- (Target - Fixup + Addend) 0204 R_RISCV_32_PCREL, 0205 0206 /// An auipc/jalr pair eligible for linker relaxation. 0207 /// 0208 /// Linker relaxation will replace this with R_RISCV_RVC_JUMP or R_RISCV_JAL 0209 /// if it succeeds, or with R_RISCV_CALL_PLT if it fails. 0210 CallRelaxable, 0211 0212 /// Alignment requirement used by linker relaxation. 0213 /// 0214 /// Linker relaxation will use this to ensure all code sequences are properly 0215 /// aligned and then remove these edges from the graph. 0216 AlignRelaxable, 0217 0218 /// 32-bit negative delta. 0219 /// 0220 /// Fixup expression: 0221 /// Fixup <- Fixup - Target + Addend 0222 NegDelta32, 0223 }; 0224 0225 /// Returns a string name for the given riscv edge. For debugging purposes 0226 /// only 0227 const char *getEdgeKindName(Edge::Kind K); 0228 } // namespace riscv 0229 } // namespace jitlink 0230 } // namespace llvm 0231 0232 #endif
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|