llvm/CodeGen/TargetSchedule.h

0001 //===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines a wrapper around MCSchedModel that allows the interface to
0010 // benefit from information currently only available in TargetInstrInfo.
0011 // Ideally, the scheduling interface would be fully defined in the MC layer.
0012 //
0013 //===----------------------------------------------------------------------===//
0014
0015 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
0016 #define LLVM_CODEGEN_TARGETSCHEDULE_H
0017
0018 #include "llvm/ADT/SmallVector.h"
0019 #include "llvm/CodeGen/TargetSubtargetInfo.h"
0020 #include "llvm/Config/llvm-config.h"
0021 #include "llvm/MC/MCInstrItineraries.h"
0022 #include "llvm/MC/MCSchedule.h"
0023
0024 namespace llvm {
0025
0026 class MachineInstr;
0027 class TargetInstrInfo;
0028
0029 /// Provide an instruction scheduling machine model to CodeGen passes.
0030 class TargetSchedModel {
0031   // For efficiency, hold a copy of the statically defined MCSchedModel for this
0032   // processor.
0033   MCSchedModel SchedModel;
0034   InstrItineraryData InstrItins;
0035   const TargetSubtargetInfo *STI = nullptr;
0036   const TargetInstrInfo *TII = nullptr;
0037
0038   SmallVector<unsigned, 16> ResourceFactors;
0039
0040   // Multiply to normalize microops to resource units.
0041   unsigned MicroOpFactor = 0;
0042
0043   // Resource units per cycle. Latency normalization factor.
0044   unsigned ResourceLCM = 0;
0045
0046   unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
0047
0048 public:
0049   TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
0050
0051   /// Initialize the machine model for instruction scheduling.
0052   ///
0053   /// The machine model API keeps a copy of the top-level MCSchedModel table
0054   /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
0055   /// dynamic properties.
0056   void init(const TargetSubtargetInfo *TSInfo);
0057
0058   /// Return the MCSchedClassDesc for this instruction.
0059   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
0060
0061   /// TargetSubtargetInfo getter.
0062   const TargetSubtargetInfo *getSubtargetInfo() const { return STI; }
0063
0064   /// TargetInstrInfo getter.
0065   const TargetInstrInfo *getInstrInfo() const { return TII; }
0066
0067   /// Return true if this machine model includes an instruction-level
0068   /// scheduling model.
0069   ///
0070   /// This is more detailed than the course grain IssueWidth and default
0071   /// latency properties, but separate from the per-cycle itinerary data.
0072   bool hasInstrSchedModel() const;
0073
0074   const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
0075
0076   /// Return true if this machine model includes cycle-to-cycle itinerary
0077   /// data.
0078   ///
0079   /// This models scheduling at each stage in the processor pipeline.
0080   bool hasInstrItineraries() const;
0081
0082   const InstrItineraryData *getInstrItineraries() const {
0083     if (hasInstrItineraries())
0084       return &InstrItins;
0085     return nullptr;
0086   }
0087
0088   /// Return true if this machine model includes an instruction-level
0089   /// scheduling model or cycle-to-cycle itinerary data.
0090   bool hasInstrSchedModelOrItineraries() const {
0091     return hasInstrSchedModel() || hasInstrItineraries();
0092   }
0093   bool enableIntervals() const;
0094   /// Identify the processor corresponding to the current subtarget.
0095   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
0096
0097   /// Maximum number of micro-ops that may be scheduled per cycle.
0098   unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
0099
0100   /// Return true if new group must begin.
0101   bool mustBeginGroup(const MachineInstr *MI,
0102                           const MCSchedClassDesc *SC = nullptr) const;
0103   /// Return true if current group must end.
0104   bool mustEndGroup(const MachineInstr *MI,
0105                           const MCSchedClassDesc *SC = nullptr) const;
0106
0107   /// Return the number of issue slots required for this MI.
0108   unsigned getNumMicroOps(const MachineInstr *MI,
0109                           const MCSchedClassDesc *SC = nullptr) const;
0110
0111   /// Get the number of kinds of resources for this target.
0112   unsigned getNumProcResourceKinds() const {
0113     return SchedModel.getNumProcResourceKinds();
0114   }
0115
0116   /// Get a processor resource by ID for convenience.
0117   const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
0118     return SchedModel.getProcResource(PIdx);
0119   }
0120
0121 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
0122   const char *getResourceName(unsigned PIdx) const {
0123     if (!PIdx)
0124       return "MOps";
0125     return SchedModel.getProcResource(PIdx)->Name;
0126   }
0127 #endif
0128
0129   using ProcResIter = const MCWriteProcResEntry *;
0130
0131   // Get an iterator into the processor resources consumed by this
0132   // scheduling class.
0133   ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
0134     // The subtarget holds a single resource table for all processors.
0135     return STI->getWriteProcResBegin(SC);
0136   }
0137   ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
0138     return STI->getWriteProcResEnd(SC);
0139   }
0140
0141   /// Multiply the number of units consumed for a resource by this factor
0142   /// to normalize it relative to other resources.
0143   unsigned getResourceFactor(unsigned ResIdx) const {
0144     return ResourceFactors[ResIdx];
0145   }
0146
0147   /// Multiply number of micro-ops by this factor to normalize it
0148   /// relative to other resources.
0149   unsigned getMicroOpFactor() const {
0150     return MicroOpFactor;
0151   }
0152
0153   /// Multiply cycle count by this factor to normalize it relative to
0154   /// other resources. This is the number of resource units per cycle.
0155   unsigned getLatencyFactor() const {
0156     return ResourceLCM;
0157   }
0158
0159   /// Number of micro-ops that may be buffered for OOO execution.
0160   unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
0161
0162   /// Number of resource units that may be buffered for OOO execution.
0163   /// \return The buffer size in resource units or -1 for unlimited.
0164   int getResourceBufferSize(unsigned PIdx) const {
0165     return SchedModel.getProcResource(PIdx)->BufferSize;
0166   }
0167
0168   /// Compute operand latency based on the available machine model.
0169   ///
0170   /// Compute and return the latency of the given data dependent def and use
0171   /// when the operand indices are already known. UseMI may be NULL for an
0172   /// unknown user.
0173   unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
0174                                  const MachineInstr *UseMI, unsigned UseOperIdx)
0175     const;
0176
0177   /// Compute the instruction latency based on the available machine
0178   /// model.
0179   ///
0180   /// Compute and return the expected latency of this instruction independent of
0181   /// a particular use. computeOperandLatency is the preferred API, but this is
0182   /// occasionally useful to help estimate instruction cost.
0183   ///
0184   /// If UseDefaultDefLatency is false and no new machine sched model is
0185   /// present this method falls back to TII->getInstrLatency with an empty
0186   /// instruction itinerary (this is so we preserve the previous behavior of the
0187   /// if converter after moving it to TargetSchedModel).
0188   unsigned computeInstrLatency(const MachineInstr *MI,
0189                                bool UseDefaultDefLatency = true) const;
0190   unsigned computeInstrLatency(const MCInst &Inst) const;
0191   unsigned computeInstrLatency(unsigned Opcode) const;
0192
0193
0194   /// Output dependency latency of a pair of defs of the same register.
0195   ///
0196   /// This is typically one cycle.
0197   unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
0198                                 const MachineInstr *DepMI) const;
0199
0200   /// Compute the reciprocal throughput of the given instruction.
0201   double computeReciprocalThroughput(const MachineInstr *MI) const;
0202   double computeReciprocalThroughput(const MCInst &MI) const;
0203   double computeReciprocalThroughput(unsigned Opcode) const;
0204 };
0205
0206 } // end namespace llvm
0207
0208 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H