llvm/CodeGen/SelectionDAGISel.h

0001 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file implements the SelectionDAGISel class, which is used as the common
0010 // base class for SelectionDAG-based instruction selectors.
0011 //
0012 //===----------------------------------------------------------------------===//
0013
0014 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
0015 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
0016
0017 #include "llvm/Analysis/AliasAnalysis.h"
0018 #include "llvm/CodeGen/MachineFunctionPass.h"
0019 #include "llvm/CodeGen/MachinePassManager.h"
0020 #include "llvm/CodeGen/SelectionDAG.h"
0021 #include "llvm/IR/BasicBlock.h"
0022 #include <memory>
0023
0024 namespace llvm {
0025 class AAResults;
0026 class AssumptionCache;
0027 class TargetInstrInfo;
0028 class TargetMachine;
0029 class SSPLayoutInfo;
0030 class SelectionDAGBuilder;
0031 class SDValue;
0032 class MachineRegisterInfo;
0033 class MachineFunction;
0034 class OptimizationRemarkEmitter;
0035 class TargetLowering;
0036 class TargetLibraryInfo;
0037 class TargetTransformInfo;
0038 class FunctionLoweringInfo;
0039 class SwiftErrorValueTracking;
0040 class GCFunctionInfo;
0041 class ScheduleDAGSDNodes;
0042
0043 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
0044 /// pattern-matching instruction selectors.
0045 class SelectionDAGISel {
0046 public:
0047   TargetMachine &TM;
0048   const TargetLibraryInfo *LibInfo;
0049   std::unique_ptr<FunctionLoweringInfo> FuncInfo;
0050   SwiftErrorValueTracking *SwiftError;
0051   MachineFunction *MF;
0052   MachineModuleInfo *MMI;
0053   MachineRegisterInfo *RegInfo;
0054   SelectionDAG *CurDAG;
0055   std::unique_ptr<SelectionDAGBuilder> SDB;
0056   mutable std::optional<BatchAAResults> BatchAA;
0057   AssumptionCache *AC = nullptr;
0058   GCFunctionInfo *GFI = nullptr;
0059   SSPLayoutInfo *SP = nullptr;
0060 #if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
0061   TargetTransformInfo *TTI = nullptr;
0062 #endif
0063   CodeGenOptLevel OptLevel;
0064   const TargetInstrInfo *TII;
0065   const TargetLowering *TLI;
0066   bool FastISelFailed;
0067   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
0068
0069   /// Current optimization remark emitter.
0070   /// Used to report things like combines and FastISel failures.
0071   std::unique_ptr<OptimizationRemarkEmitter> ORE;
0072
0073   /// True if the function currently processing is in the function printing list
0074   /// (i.e. `-filter-print-funcs`).
0075   /// This is primarily used by ISEL_DUMP, which spans in multiple member
0076   /// functions. Storing the filter result here so that we only need to do the
0077   /// filtering once.
0078   bool MatchFilterFuncName = false;
0079   StringRef FuncName;
0080
0081   explicit SelectionDAGISel(TargetMachine &tm,
0082                             CodeGenOptLevel OL = CodeGenOptLevel::Default);
0083   virtual ~SelectionDAGISel();
0084
0085   /// Returns a (possibly null) pointer to the current BatchAAResults.
0086   BatchAAResults *getBatchAA() const {
0087     if (BatchAA.has_value())
0088       return &BatchAA.value();
0089     return nullptr;
0090   }
0091
0092   const TargetLowering *getTargetLowering() const { return TLI; }
0093
0094   void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM);
0095   void initializeAnalysisResults(MachineFunctionPass &MFP);
0096
0097   virtual bool runOnMachineFunction(MachineFunction &mf);
0098
0099   virtual void emitFunctionEntryCode() {}
0100
0101   /// PreprocessISelDAG - This hook allows targets to hack on the graph before
0102   /// instruction selection starts.
0103   virtual void PreprocessISelDAG() {}
0104
0105   /// PostprocessISelDAG() - This hook allows the target to hack on the graph
0106   /// right after selection.
0107   virtual void PostprocessISelDAG() {}
0108
0109   /// Main hook for targets to transform nodes into machine nodes.
0110   virtual void Select(SDNode *N) = 0;
0111
0112   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
0113   /// addressing mode, according to the specified constraint.  If this does
0114   /// not match or is not implemented, return true.  The resultant operands
0115   /// (which will appear in the machine instruction) should be added to the
0116   /// OutOps vector.
0117   virtual bool
0118   SelectInlineAsmMemoryOperand(const SDValue &Op,
0119                                InlineAsm::ConstraintCode ConstraintID,
0120                                std::vector<SDValue> &OutOps) {
0121     return true;
0122   }
0123
0124   /// IsProfitableToFold - Returns true if it's profitable to fold the specific
0125   /// operand node N of U during instruction selection that starts at Root.
0126   virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
0127
0128   /// IsLegalToFold - Returns true if the specific operand node N of
0129   /// U can be folded during instruction selection that starts at Root.
0130   /// FIXME: This is a static member function because the MSP430/X86
0131   /// targets, which uses it during isel.  This could become a proper member.
0132   static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
0133                             CodeGenOptLevel OptLevel,
0134                             bool IgnoreChains = false);
0135
0136   static void InvalidateNodeId(SDNode *N);
0137   static int getUninvalidatedNodeId(SDNode *N);
0138
0139   static void EnforceNodeIdInvariant(SDNode *N);
0140
0141   // Opcodes used by the DAG state machine:
0142   enum BuiltinOpcodes {
0143     OPC_Scope,
0144     OPC_RecordNode,
0145     OPC_RecordChild0,
0146     OPC_RecordChild1,
0147     OPC_RecordChild2,
0148     OPC_RecordChild3,
0149     OPC_RecordChild4,
0150     OPC_RecordChild5,
0151     OPC_RecordChild6,
0152     OPC_RecordChild7,
0153     OPC_RecordMemRef,
0154     OPC_CaptureGlueInput,
0155     OPC_MoveChild,
0156     OPC_MoveChild0,
0157     OPC_MoveChild1,
0158     OPC_MoveChild2,
0159     OPC_MoveChild3,
0160     OPC_MoveChild4,
0161     OPC_MoveChild5,
0162     OPC_MoveChild6,
0163     OPC_MoveChild7,
0164     OPC_MoveSibling,
0165     OPC_MoveSibling0,
0166     OPC_MoveSibling1,
0167     OPC_MoveSibling2,
0168     OPC_MoveSibling3,
0169     OPC_MoveSibling4,
0170     OPC_MoveSibling5,
0171     OPC_MoveSibling6,
0172     OPC_MoveSibling7,
0173     OPC_MoveParent,
0174     OPC_CheckSame,
0175     OPC_CheckChild0Same,
0176     OPC_CheckChild1Same,
0177     OPC_CheckChild2Same,
0178     OPC_CheckChild3Same,
0179     OPC_CheckPatternPredicate,
0180     OPC_CheckPatternPredicate0,
0181     OPC_CheckPatternPredicate1,
0182     OPC_CheckPatternPredicate2,
0183     OPC_CheckPatternPredicate3,
0184     OPC_CheckPatternPredicate4,
0185     OPC_CheckPatternPredicate5,
0186     OPC_CheckPatternPredicate6,
0187     OPC_CheckPatternPredicate7,
0188     OPC_CheckPatternPredicateTwoByte,
0189     OPC_CheckPredicate,
0190     OPC_CheckPredicate0,
0191     OPC_CheckPredicate1,
0192     OPC_CheckPredicate2,
0193     OPC_CheckPredicate3,
0194     OPC_CheckPredicate4,
0195     OPC_CheckPredicate5,
0196     OPC_CheckPredicate6,
0197     OPC_CheckPredicate7,
0198     OPC_CheckPredicateWithOperands,
0199     OPC_CheckOpcode,
0200     OPC_SwitchOpcode,
0201     OPC_CheckType,
0202     // Space-optimized forms that implicitly encode VT.
0203     OPC_CheckTypeI32,
0204     OPC_CheckTypeI64,
0205     OPC_CheckTypeRes,
0206     OPC_SwitchType,
0207     OPC_CheckChild0Type,
0208     OPC_CheckChild1Type,
0209     OPC_CheckChild2Type,
0210     OPC_CheckChild3Type,
0211     OPC_CheckChild4Type,
0212     OPC_CheckChild5Type,
0213     OPC_CheckChild6Type,
0214     OPC_CheckChild7Type,
0215
0216     OPC_CheckChild0TypeI32,
0217     OPC_CheckChild1TypeI32,
0218     OPC_CheckChild2TypeI32,
0219     OPC_CheckChild3TypeI32,
0220     OPC_CheckChild4TypeI32,
0221     OPC_CheckChild5TypeI32,
0222     OPC_CheckChild6TypeI32,
0223     OPC_CheckChild7TypeI32,
0224
0225     OPC_CheckChild0TypeI64,
0226     OPC_CheckChild1TypeI64,
0227     OPC_CheckChild2TypeI64,
0228     OPC_CheckChild3TypeI64,
0229     OPC_CheckChild4TypeI64,
0230     OPC_CheckChild5TypeI64,
0231     OPC_CheckChild6TypeI64,
0232     OPC_CheckChild7TypeI64,
0233
0234     OPC_CheckInteger,
0235     OPC_CheckChild0Integer,
0236     OPC_CheckChild1Integer,
0237     OPC_CheckChild2Integer,
0238     OPC_CheckChild3Integer,
0239     OPC_CheckChild4Integer,
0240     OPC_CheckCondCode,
0241     OPC_CheckChild2CondCode,
0242     OPC_CheckValueType,
0243     OPC_CheckComplexPat,
0244     OPC_CheckComplexPat0,
0245     OPC_CheckComplexPat1,
0246     OPC_CheckComplexPat2,
0247     OPC_CheckComplexPat3,
0248     OPC_CheckComplexPat4,
0249     OPC_CheckComplexPat5,
0250     OPC_CheckComplexPat6,
0251     OPC_CheckComplexPat7,
0252     OPC_CheckAndImm,
0253     OPC_CheckOrImm,
0254     OPC_CheckImmAllOnesV,
0255     OPC_CheckImmAllZerosV,
0256     OPC_CheckFoldableChainNode,
0257
0258     OPC_EmitInteger,
0259     // Space-optimized forms that implicitly encode integer VT.
0260     OPC_EmitInteger8,
0261     OPC_EmitInteger16,
0262     OPC_EmitInteger32,
0263     OPC_EmitInteger64,
0264     OPC_EmitStringInteger,
0265     // Space-optimized forms that implicitly encode integer VT.
0266     OPC_EmitStringInteger32,
0267     OPC_EmitRegister,
0268     OPC_EmitRegisterI32,
0269     OPC_EmitRegisterI64,
0270     OPC_EmitRegister2,
0271     OPC_EmitConvertToTarget,
0272     OPC_EmitConvertToTarget0,
0273     OPC_EmitConvertToTarget1,
0274     OPC_EmitConvertToTarget2,
0275     OPC_EmitConvertToTarget3,
0276     OPC_EmitConvertToTarget4,
0277     OPC_EmitConvertToTarget5,
0278     OPC_EmitConvertToTarget6,
0279     OPC_EmitConvertToTarget7,
0280     OPC_EmitMergeInputChains,
0281     OPC_EmitMergeInputChains1_0,
0282     OPC_EmitMergeInputChains1_1,
0283     OPC_EmitMergeInputChains1_2,
0284     OPC_EmitCopyToReg,
0285     OPC_EmitCopyToReg0,
0286     OPC_EmitCopyToReg1,
0287     OPC_EmitCopyToReg2,
0288     OPC_EmitCopyToReg3,
0289     OPC_EmitCopyToReg4,
0290     OPC_EmitCopyToReg5,
0291     OPC_EmitCopyToReg6,
0292     OPC_EmitCopyToReg7,
0293     OPC_EmitCopyToRegTwoByte,
0294     OPC_EmitNodeXForm,
0295     OPC_EmitNode,
0296     // Space-optimized forms that implicitly encode number of result VTs.
0297     OPC_EmitNode0,
0298     OPC_EmitNode1,
0299     OPC_EmitNode2,
0300     // Space-optimized forms that implicitly encode EmitNodeInfo.
0301     OPC_EmitNode0None,
0302     OPC_EmitNode1None,
0303     OPC_EmitNode2None,
0304     OPC_EmitNode0Chain,
0305     OPC_EmitNode1Chain,
0306     OPC_EmitNode2Chain,
0307     OPC_MorphNodeTo,
0308     // Space-optimized forms that implicitly encode number of result VTs.
0309     OPC_MorphNodeTo0,
0310     OPC_MorphNodeTo1,
0311     OPC_MorphNodeTo2,
0312     // Space-optimized forms that implicitly encode EmitNodeInfo.
0313     OPC_MorphNodeTo0None,
0314     OPC_MorphNodeTo1None,
0315     OPC_MorphNodeTo2None,
0316     OPC_MorphNodeTo0Chain,
0317     OPC_MorphNodeTo1Chain,
0318     OPC_MorphNodeTo2Chain,
0319     OPC_MorphNodeTo0GlueInput,
0320     OPC_MorphNodeTo1GlueInput,
0321     OPC_MorphNodeTo2GlueInput,
0322     OPC_MorphNodeTo0GlueOutput,
0323     OPC_MorphNodeTo1GlueOutput,
0324     OPC_MorphNodeTo2GlueOutput,
0325     OPC_CompleteMatch,
0326     // Contains 32-bit offset in table for pattern being selected
0327     OPC_Coverage
0328   };
0329
0330   enum {
0331     OPFL_None       = 0,  // Node has no chain or glue input and isn't variadic.
0332     OPFL_Chain      = 1,     // Node has a chain input.
0333     OPFL_GlueInput  = 2,     // Node has a glue input.
0334     OPFL_GlueOutput = 4,     // Node has a glue output.
0335     OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
0336     OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
0337     OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
0338     OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
0339     OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
0340     OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
0341     OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
0342     OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
0343
0344     OPFL_VariadicInfo = OPFL_Variadic6
0345   };
0346
0347   /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
0348   /// number of fixed arity values that should be skipped when copying from the
0349   /// root.
0350   static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
0351     return ((Flags&OPFL_VariadicInfo) >> 4)-1;
0352   }
0353
0354
0355 protected:
0356   /// DAGSize - Size of DAG being instruction selected.
0357   ///
0358   unsigned DAGSize = 0;
0359
0360   /// ReplaceUses - replace all uses of the old node F with the use
0361   /// of the new node T.
0362   void ReplaceUses(SDValue F, SDValue T) {
0363     CurDAG->ReplaceAllUsesOfValueWith(F, T);
0364     EnforceNodeIdInvariant(T.getNode());
0365   }
0366
0367   /// ReplaceUses - replace all uses of the old nodes F with the use
0368   /// of the new nodes T.
0369   void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
0370     CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
0371     for (unsigned i = 0; i < Num; ++i)
0372       EnforceNodeIdInvariant(T[i].getNode());
0373   }
0374
0375   /// ReplaceUses - replace all uses of the old node F with the use
0376   /// of the new node T.
0377   void ReplaceUses(SDNode *F, SDNode *T) {
0378     CurDAG->ReplaceAllUsesWith(F, T);
0379     EnforceNodeIdInvariant(T);
0380   }
0381
0382   /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
0383   void ReplaceNode(SDNode *F, SDNode *T) {
0384     CurDAG->ReplaceAllUsesWith(F, T);
0385     EnforceNodeIdInvariant(T);
0386     CurDAG->RemoveDeadNode(F);
0387   }
0388
0389   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
0390   /// by tblgen.  Others should not call it.
0391   void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
0392                                      const SDLoc &DL);
0393
0394   /// getPatternForIndex - Patterns selected by tablegen during ISEL
0395   virtual StringRef getPatternForIndex(unsigned index) {
0396     llvm_unreachable("Tblgen should generate the implementation of this!");
0397   }
0398
0399   /// getIncludePathForIndex - get the td source location of pattern instantiation
0400   virtual StringRef getIncludePathForIndex(unsigned index) {
0401     llvm_unreachable("Tblgen should generate the implementation of this!");
0402   }
0403
0404   bool shouldOptForSize(const MachineFunction *MF) const {
0405     return CurDAG->shouldOptForSize();
0406   }
0407
0408 public:
0409   // Calls to these predicates are generated by tblgen.
0410   bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
0411                     int64_t DesiredMaskS) const;
0412   bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
0413                     int64_t DesiredMaskS) const;
0414
0415
0416   /// CheckPatternPredicate - This function is generated by tblgen in the
0417   /// target.  It runs the specified pattern predicate and returns true if it
0418   /// succeeds or false if it fails.  The number is a private implementation
0419   /// detail to the code tblgen produces.
0420   virtual bool CheckPatternPredicate(unsigned PredNo) const {
0421     llvm_unreachable("Tblgen should generate the implementation of this!");
0422   }
0423
0424   /// CheckNodePredicate - This function is generated by tblgen in the target.
0425   /// It runs node predicate number PredNo and returns true if it succeeds or
0426   /// false if it fails.  The number is a private implementation
0427   /// detail to the code tblgen produces.
0428   virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
0429     llvm_unreachable("Tblgen should generate the implementation of this!");
0430   }
0431
0432   /// CheckNodePredicateWithOperands - This function is generated by tblgen in
0433   /// the target.
0434   /// It runs node predicate number PredNo and returns true if it succeeds or
0435   /// false if it fails.  The number is a private implementation detail to the
0436   /// code tblgen produces.
0437   virtual bool CheckNodePredicateWithOperands(
0438       SDNode *N, unsigned PredNo,
0439       const SmallVectorImpl<SDValue> &Operands) const {
0440     llvm_unreachable("Tblgen should generate the implementation of this!");
0441   }
0442
0443   virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
0444                                    unsigned PatternNo,
0445                         SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
0446     llvm_unreachable("Tblgen should generate the implementation of this!");
0447   }
0448
0449   virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
0450     llvm_unreachable("Tblgen should generate this!");
0451   }
0452
0453   void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
0454                         unsigned TableSize);
0455
0456   /// Return true if complex patterns for this target can mutate the
0457   /// DAG.
0458   virtual bool ComplexPatternFuncMutatesDAG() const {
0459     return false;
0460   }
0461
0462   /// Return whether the node may raise an FP exception.
0463   bool mayRaiseFPException(SDNode *Node) const;
0464
0465   bool isOrEquivalentToAdd(const SDNode *N) const;
0466
0467 private:
0468
0469   // Calls to these functions are generated by tblgen.
0470   void Select_INLINEASM(SDNode *N);
0471   void Select_READ_REGISTER(SDNode *Op);
0472   void Select_WRITE_REGISTER(SDNode *Op);
0473   void Select_UNDEF(SDNode *N);
0474   void Select_FAKE_USE(SDNode *N);
0475   void CannotYetSelect(SDNode *N);
0476
0477   void Select_FREEZE(SDNode *N);
0478   void Select_ARITH_FENCE(SDNode *N);
0479   void Select_MEMBARRIER(SDNode *N);
0480
0481   void Select_CONVERGENCECTRL_ANCHOR(SDNode *N);
0482   void Select_CONVERGENCECTRL_ENTRY(SDNode *N);
0483   void Select_CONVERGENCECTRL_LOOP(SDNode *N);
0484
0485   void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand,
0486                                 SDLoc DL);
0487   void Select_STACKMAP(SDNode *N);
0488   void Select_PATCHPOINT(SDNode *N);
0489
0490   void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N);
0491
0492 private:
0493   void DoInstructionSelection();
0494   SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
0495                     ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
0496
0497   /// Prepares the landing pad to take incoming values or do other EH
0498   /// personality specific tasks. Returns true if the block should be
0499   /// instruction selected, false if no code should be emitted for it.
0500   bool PrepareEHLandingPad();
0501
0502   // Mark and Report IPToState for each Block under AsynchEH
0503   void reportIPToStateForBlocks(MachineFunction *Fn);
0504
0505   /// Perform instruction selection on all basic blocks in the function.
0506   void SelectAllBasicBlocks(const Function &Fn);
0507
0508   /// Perform instruction selection on a single basic block, for
0509   /// instructions between \p Begin and \p End.  \p HadTailCall will be set
0510   /// to true if a call in the block was translated as a tail call.
0511   void SelectBasicBlock(BasicBlock::const_iterator Begin,
0512                         BasicBlock::const_iterator End,
0513                         bool &HadTailCall);
0514   void FinishBasicBlock();
0515
0516   void CodeGenAndEmitDAG();
0517
0518   /// Generate instructions for lowering the incoming arguments of the
0519   /// given function.
0520   void LowerArguments(const Function &F);
0521
0522   void ComputeLiveOutVRegInfo();
0523
0524   /// Create the scheduler. If a specific scheduler was specified
0525   /// via the SchedulerRegistry, use it, otherwise select the
0526   /// one preferred by the target.
0527   ///
0528   ScheduleDAGSDNodes *CreateScheduler();
0529
0530   /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
0531   /// state machines that start with a OPC_SwitchOpcode node.
0532   std::vector<unsigned> OpcodeOffset;
0533
0534   void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
0535                     SmallVectorImpl<SDNode *> &ChainNodesMatched,
0536                     bool isMorphNodeTo);
0537 };
0538
0539 class SelectionDAGISelLegacy : public MachineFunctionPass {
0540   std::unique_ptr<SelectionDAGISel> Selector;
0541
0542 public:
0543   SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S);
0544
0545   ~SelectionDAGISelLegacy() override = default;
0546
0547   void getAnalysisUsage(AnalysisUsage &AU) const override;
0548
0549   bool runOnMachineFunction(MachineFunction &MF) override;
0550 };
0551
0552 class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> {
0553   std::unique_ptr<SelectionDAGISel> Selector;
0554
0555 protected:
0556   SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)
0557       : Selector(std::move(Selector)) {}
0558
0559 public:
0560   PreservedAnalyses run(MachineFunction &MF,
0561                         MachineFunctionAnalysisManager &MFAM);
0562   static bool isRequired() { return true; }
0563 };
0564 }
0565
0566 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */