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File indexing completed on 2026-05-10 08:43:34
0001 //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===// 0002 // 0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 0004 // See https://llvm.org/LICENSE.txt for license information. 0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 0006 // 0007 //===----------------------------------------------------------------------===// 0008 // 0009 // This file contains the implementation for instruction scheduler function 0010 // pass registry (RegisterScheduler). 0011 // 0012 //===----------------------------------------------------------------------===// 0013 0014 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H 0015 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H 0016 0017 #include "llvm/CodeGen/MachinePassRegistry.h" 0018 #include "llvm/Support/CodeGen.h" 0019 0020 namespace llvm { 0021 0022 //===----------------------------------------------------------------------===// 0023 /// 0024 /// RegisterScheduler class - Track the registration of instruction schedulers. 0025 /// 0026 //===----------------------------------------------------------------------===// 0027 0028 class ScheduleDAGSDNodes; 0029 class SelectionDAGISel; 0030 0031 class RegisterScheduler 0032 : public MachinePassRegistryNode<ScheduleDAGSDNodes *(*)(SelectionDAGISel *, 0033 CodeGenOptLevel)> { 0034 public: 0035 using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel *, 0036 CodeGenOptLevel); 0037 0038 static MachinePassRegistry<FunctionPassCtor> Registry; 0039 0040 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C) 0041 : MachinePassRegistryNode(N, D, C) { 0042 Registry.Add(this); 0043 } 0044 ~RegisterScheduler() { Registry.Remove(this); } 0045 0046 0047 // Accessors. 0048 RegisterScheduler *getNext() const { 0049 return (RegisterScheduler *)MachinePassRegistryNode::getNext(); 0050 } 0051 0052 static RegisterScheduler *getList() { 0053 return (RegisterScheduler *)Registry.getList(); 0054 } 0055 0056 static void setListener(MachinePassRegistryListener<FunctionPassCtor> *L) { 0057 Registry.setListener(L); 0058 } 0059 }; 0060 0061 /// createBURRListDAGScheduler - This creates a bottom up register usage 0062 /// reduction list scheduler. 0063 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, 0064 CodeGenOptLevel OptLevel); 0065 0066 /// createSourceListDAGScheduler - This creates a bottom up list scheduler that 0067 /// schedules nodes in source code order when possible. 0068 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, 0069 CodeGenOptLevel OptLevel); 0070 0071 /// createHybridListDAGScheduler - This creates a bottom up register pressure 0072 /// aware list scheduler that make use of latency information to avoid stalls 0073 /// for long latency instructions in low register pressure mode. In high 0074 /// register pressure mode it schedules to reduce register pressure. 0075 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS, 0076 CodeGenOptLevel); 0077 0078 /// createILPListDAGScheduler - This creates a bottom up register pressure 0079 /// aware list scheduler that tries to increase instruction level parallelism 0080 /// in low register pressure mode. In high register pressure mode it schedules 0081 /// to reduce register pressure. 0082 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS, 0083 CodeGenOptLevel); 0084 0085 /// createFastDAGScheduler - This creates a "fast" scheduler. 0086 /// 0087 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, 0088 CodeGenOptLevel OptLevel); 0089 0090 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down 0091 /// DFA driven list scheduler with clustering heuristic to control 0092 /// register pressure. 0093 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS, 0094 CodeGenOptLevel OptLevel); 0095 /// createDefaultScheduler - This creates an instruction scheduler appropriate 0096 /// for the target. 0097 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, 0098 CodeGenOptLevel OptLevel); 0099 0100 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which 0101 /// linearize the DAG using topological order. 0102 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS, 0103 CodeGenOptLevel OptLevel); 0104 0105 } // end namespace llvm 0106 0107 #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H
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