File indexing completed on 2026-05-10 08:43:34
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0014 #ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
0015 #define LLVM_CODEGEN_REGISTERPRESSURE_H
0016
0017 #include "llvm/ADT/ArrayRef.h"
0018 #include "llvm/ADT/SmallVector.h"
0019 #include "llvm/ADT/SparseSet.h"
0020 #include "llvm/CodeGen/MachineBasicBlock.h"
0021 #include "llvm/CodeGen/SlotIndexes.h"
0022 #include "llvm/CodeGen/TargetRegisterInfo.h"
0023 #include "llvm/MC/LaneBitmask.h"
0024 #include <cassert>
0025 #include <cstdint>
0026 #include <cstdlib>
0027 #include <limits>
0028 #include <vector>
0029
0030 namespace llvm {
0031
0032 class LiveIntervals;
0033 class MachineFunction;
0034 class MachineInstr;
0035 class MachineRegisterInfo;
0036 class RegisterClassInfo;
0037
0038 struct VRegMaskOrUnit {
0039 Register RegUnit;
0040 LaneBitmask LaneMask;
0041
0042 VRegMaskOrUnit(Register RegUnit, LaneBitmask LaneMask)
0043 : RegUnit(RegUnit), LaneMask(LaneMask) {}
0044 };
0045
0046
0047 struct RegisterPressure {
0048
0049 std::vector<unsigned> MaxSetPressure;
0050
0051
0052 SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
0053 SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
0054
0055 void dump(const TargetRegisterInfo *TRI) const;
0056 };
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067 struct IntervalPressure : RegisterPressure {
0068
0069 SlotIndex TopIdx;
0070 SlotIndex BottomIdx;
0071
0072 void reset();
0073
0074 void openTop(SlotIndex NextTop);
0075
0076 void openBottom(SlotIndex PrevBottom);
0077 };
0078
0079
0080
0081
0082 struct RegionPressure : RegisterPressure {
0083
0084 MachineBasicBlock::const_iterator TopPos;
0085 MachineBasicBlock::const_iterator BottomPos;
0086
0087 void reset();
0088
0089 void openTop(MachineBasicBlock::const_iterator PrevTop);
0090
0091 void openBottom(MachineBasicBlock::const_iterator PrevBottom);
0092 };
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102 class PressureChange {
0103 uint16_t PSetID = 0;
0104 int16_t UnitInc = 0;
0105
0106 public:
0107 PressureChange() = default;
0108 PressureChange(unsigned id): PSetID(id + 1) {
0109 assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
0110 }
0111
0112 bool isValid() const { return PSetID > 0; }
0113
0114 unsigned getPSet() const {
0115 assert(isValid() && "invalid PressureChange");
0116 return PSetID - 1;
0117 }
0118
0119
0120 unsigned getPSetOrMax() const {
0121 return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
0122 }
0123
0124 int getUnitInc() const { return UnitInc; }
0125
0126 void setUnitInc(int Inc) { UnitInc = Inc; }
0127
0128 bool operator==(const PressureChange &RHS) const {
0129 return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
0130 }
0131
0132 void dump() const;
0133 };
0134
0135
0136
0137
0138
0139
0140 class PressureDiff {
0141
0142
0143
0144 enum { MaxPSets = 16 };
0145
0146 PressureChange PressureChanges[MaxPSets];
0147
0148 using iterator = PressureChange *;
0149
0150 iterator nonconst_begin() { return &PressureChanges[0]; }
0151 iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
0152
0153 public:
0154 using const_iterator = const PressureChange *;
0155
0156 const_iterator begin() const { return &PressureChanges[0]; }
0157 const_iterator end() const { return &PressureChanges[MaxPSets]; }
0158
0159 void addPressureChange(Register RegUnit, bool IsDec,
0160 const MachineRegisterInfo *MRI);
0161
0162 void dump(const TargetRegisterInfo &TRI) const;
0163 };
0164
0165
0166 class RegisterOperands {
0167 public:
0168
0169 SmallVector<VRegMaskOrUnit, 8> Uses;
0170
0171
0172 SmallVector<VRegMaskOrUnit, 8> Defs;
0173
0174
0175 SmallVector<VRegMaskOrUnit, 8> DeadDefs;
0176
0177
0178
0179 void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
0180 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
0181 bool IgnoreDead);
0182
0183
0184
0185 void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
0186
0187
0188
0189
0190
0191 void adjustLaneLiveness(const LiveIntervals &LIS,
0192 const MachineRegisterInfo &MRI, SlotIndex Pos,
0193 MachineInstr *AddFlagsMI = nullptr);
0194 };
0195
0196
0197 class PressureDiffs {
0198 PressureDiff *PDiffArray = nullptr;
0199 unsigned Size = 0;
0200 unsigned Max = 0;
0201
0202 public:
0203 PressureDiffs() = default;
0204 PressureDiffs &operator=(const PressureDiffs &other) = delete;
0205 PressureDiffs(const PressureDiffs &other) = delete;
0206 ~PressureDiffs() { free(PDiffArray); }
0207
0208 void clear() { Size = 0; }
0209
0210 void init(unsigned N);
0211
0212 PressureDiff &operator[](unsigned Idx) {
0213 assert(Idx < Size && "PressureDiff index out of bounds");
0214 return PDiffArray[Idx];
0215 }
0216 const PressureDiff &operator[](unsigned Idx) const {
0217 return const_cast<PressureDiffs*>(this)->operator[](Idx);
0218 }
0219
0220
0221
0222 void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
0223 const MachineRegisterInfo &MRI);
0224 };
0225
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0227
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0229
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0233
0234
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0237
0238
0239
0240 struct RegPressureDelta {
0241 PressureChange Excess;
0242 PressureChange CriticalMax;
0243 PressureChange CurrentMax;
0244
0245 RegPressureDelta() = default;
0246
0247 bool operator==(const RegPressureDelta &RHS) const {
0248 return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
0249 && CurrentMax == RHS.CurrentMax;
0250 }
0251 bool operator!=(const RegPressureDelta &RHS) const {
0252 return !operator==(RHS);
0253 }
0254 void dump() const;
0255 };
0256
0257
0258
0259
0260
0261 class LiveRegSet {
0262 private:
0263 struct IndexMaskPair {
0264 unsigned Index;
0265 LaneBitmask LaneMask;
0266
0267 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
0268 : Index(Index), LaneMask(LaneMask) {}
0269
0270 unsigned getSparseSetIndex() const {
0271 return Index;
0272 }
0273 };
0274
0275 using RegSet = SparseSet<IndexMaskPair>;
0276 RegSet Regs;
0277 unsigned NumRegUnits = 0u;
0278
0279 unsigned getSparseIndexFromReg(Register Reg) const {
0280 if (Reg.isVirtual())
0281 return Register::virtReg2Index(Reg) + NumRegUnits;
0282 assert(Reg < NumRegUnits);
0283 return Reg;
0284 }
0285
0286 Register getRegFromSparseIndex(unsigned SparseIndex) const {
0287 if (SparseIndex >= NumRegUnits)
0288 return Register::index2VirtReg(SparseIndex - NumRegUnits);
0289 return Register(SparseIndex);
0290 }
0291
0292 public:
0293 void clear();
0294 void init(const MachineRegisterInfo &MRI);
0295
0296 LaneBitmask contains(Register Reg) const {
0297 unsigned SparseIndex = getSparseIndexFromReg(Reg);
0298 RegSet::const_iterator I = Regs.find(SparseIndex);
0299 if (I == Regs.end())
0300 return LaneBitmask::getNone();
0301 return I->LaneMask;
0302 }
0303
0304
0305
0306 LaneBitmask insert(VRegMaskOrUnit Pair) {
0307 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
0308 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
0309 if (!InsertRes.second) {
0310 LaneBitmask PrevMask = InsertRes.first->LaneMask;
0311 InsertRes.first->LaneMask |= Pair.LaneMask;
0312 return PrevMask;
0313 }
0314 return LaneBitmask::getNone();
0315 }
0316
0317
0318
0319 LaneBitmask erase(VRegMaskOrUnit Pair) {
0320 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
0321 RegSet::iterator I = Regs.find(SparseIndex);
0322 if (I == Regs.end())
0323 return LaneBitmask::getNone();
0324 LaneBitmask PrevMask = I->LaneMask;
0325 I->LaneMask &= ~Pair.LaneMask;
0326 return PrevMask;
0327 }
0328
0329 size_t size() const {
0330 return Regs.size();
0331 }
0332
0333 void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
0334 for (const IndexMaskPair &P : Regs) {
0335 Register Reg = getRegFromSparseIndex(P.Index);
0336 if (P.LaneMask.any())
0337 To.emplace_back(Reg, P.LaneMask);
0338 }
0339 }
0340 };
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0357
0358 class RegPressureTracker {
0359 const MachineFunction *MF = nullptr;
0360 const TargetRegisterInfo *TRI = nullptr;
0361 const RegisterClassInfo *RCI = nullptr;
0362 const MachineRegisterInfo *MRI = nullptr;
0363 const LiveIntervals *LIS = nullptr;
0364
0365
0366 const MachineBasicBlock *MBB = nullptr;
0367
0368
0369 RegisterPressure &P;
0370
0371
0372
0373 bool RequireIntervals;
0374
0375
0376 bool TrackUntiedDefs = false;
0377
0378
0379 bool TrackLaneMasks = false;
0380
0381
0382
0383
0384 MachineBasicBlock::const_iterator CurrPos;
0385
0386
0387 std::vector<unsigned> CurrSetPressure;
0388
0389
0390 LiveRegSet LiveRegs;
0391
0392
0393 SparseSet<Register, VirtReg2IndexFunctor> UntiedDefs;
0394
0395 std::vector<unsigned> LiveThruPressure;
0396
0397 public:
0398 RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
0399 RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
0400
0401 void reset();
0402
0403 void init(const MachineFunction *mf, const RegisterClassInfo *rci,
0404 const LiveIntervals *lis, const MachineBasicBlock *mbb,
0405 MachineBasicBlock::const_iterator pos,
0406 bool TrackLaneMasks, bool TrackUntiedDefs);
0407
0408
0409
0410
0411 void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
0412
0413
0414 MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
0415
0416
0417
0418
0419
0420 void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
0421
0422
0423 void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
0424
0425
0426
0427
0428
0429 void recede(const RegisterOperands &RegOpers,
0430 SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
0431
0432
0433 void recedeSkipDebugValues();
0434
0435
0436 void advance();
0437
0438
0439
0440
0441 void advance(const RegisterOperands &RegOpers);
0442
0443
0444 void closeRegion();
0445
0446
0447
0448 void initLiveThru(const RegPressureTracker &RPTracker);
0449
0450
0451 void initLiveThru(ArrayRef<unsigned> PressureSet) {
0452 LiveThruPressure.assign(PressureSet.begin(), PressureSet.end());
0453 }
0454
0455 ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
0456
0457
0458
0459 RegisterPressure &getPressure() { return P; }
0460 const RegisterPressure &getPressure() const { return P; }
0461
0462
0463
0464 const std::vector<unsigned> &getRegSetPressureAtPos() const {
0465 return CurrSetPressure;
0466 }
0467
0468 bool isTopClosed() const;
0469 bool isBottomClosed() const;
0470
0471 void closeTop();
0472 void closeBottom();
0473
0474
0475
0476
0477
0478 void getMaxUpwardPressureDelta(const MachineInstr *MI,
0479 PressureDiff *PDiff,
0480 RegPressureDelta &Delta,
0481 ArrayRef<PressureChange> CriticalPSets,
0482 ArrayRef<unsigned> MaxPressureLimit);
0483
0484 void getUpwardPressureDelta(const MachineInstr *MI,
0485 PressureDiff &PDiff,
0486 RegPressureDelta &Delta,
0487 ArrayRef<PressureChange> CriticalPSets,
0488 ArrayRef<unsigned> MaxPressureLimit) const;
0489
0490
0491
0492
0493
0494 void getMaxDownwardPressureDelta(const MachineInstr *MI,
0495 RegPressureDelta &Delta,
0496 ArrayRef<PressureChange> CriticalPSets,
0497 ArrayRef<unsigned> MaxPressureLimit);
0498
0499
0500
0501
0502 void getMaxPressureDelta(const MachineInstr *MI,
0503 RegPressureDelta &Delta,
0504 ArrayRef<PressureChange> CriticalPSets,
0505 ArrayRef<unsigned> MaxPressureLimit) {
0506 if (isTopClosed())
0507 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
0508 MaxPressureLimit);
0509
0510 assert(isBottomClosed() && "Uninitialized pressure tracker");
0511 return getMaxUpwardPressureDelta(MI, nullptr, Delta, CriticalPSets,
0512 MaxPressureLimit);
0513 }
0514
0515
0516 void getUpwardPressure(const MachineInstr *MI,
0517 std::vector<unsigned> &PressureResult,
0518 std::vector<unsigned> &MaxPressureResult);
0519
0520
0521 void getDownwardPressure(const MachineInstr *MI,
0522 std::vector<unsigned> &PressureResult,
0523 std::vector<unsigned> &MaxPressureResult);
0524
0525 void getPressureAfterInst(const MachineInstr *MI,
0526 std::vector<unsigned> &PressureResult,
0527 std::vector<unsigned> &MaxPressureResult) {
0528 if (isTopClosed())
0529 return getUpwardPressure(MI, PressureResult, MaxPressureResult);
0530
0531 assert(isBottomClosed() && "Uninitialized pressure tracker");
0532 return getDownwardPressure(MI, PressureResult, MaxPressureResult);
0533 }
0534
0535 bool hasUntiedDef(Register VirtReg) const {
0536 return UntiedDefs.count(VirtReg);
0537 }
0538
0539 void dump() const;
0540
0541 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
0542 LaneBitmask NewMask);
0543 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
0544 LaneBitmask NewMask);
0545
0546 protected:
0547
0548 void discoverLiveOut(VRegMaskOrUnit Pair);
0549
0550 void discoverLiveIn(VRegMaskOrUnit Pair);
0551
0552
0553
0554 SlotIndex getCurrSlot() const;
0555
0556 void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
0557
0558 void bumpUpwardPressure(const MachineInstr *MI);
0559 void bumpDownwardPressure(const MachineInstr *MI);
0560
0561 void discoverLiveInOrOut(VRegMaskOrUnit Pair,
0562 SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
0563
0564 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
0565 LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
0566 LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const;
0567 };
0568
0569 void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
0570 const TargetRegisterInfo *TRI);
0571
0572 }
0573
0574 #endif