CodeGen/MIRParser/MIParser.h

0001 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file declares the function that parses the machine instructions.
0010 //
0011 //===----------------------------------------------------------------------===//
0012
0013 #ifndef LLVM_CODEGEN_MIRPARSER_MIPARSER_H
0014 #define LLVM_CODEGEN_MIRPARSER_MIPARSER_H
0015
0016 #include "llvm/ADT/DenseMap.h"
0017 #include "llvm/ADT/StringMap.h"
0018 #include "llvm/CodeGen/MachineMemOperand.h"
0019 #include "llvm/CodeGen/Register.h"
0020 #include "llvm/IR/TrackingMDRef.h"
0021 #include "llvm/Support/Allocator.h"
0022 #include "llvm/Support/SMLoc.h"
0023 #include <map>
0024 #include <utility>
0025
0026 namespace llvm {
0027
0028 class MachineBasicBlock;
0029 class MachineFunction;
0030 class MDNode;
0031 class RegisterBank;
0032 struct SlotMapping;
0033 class SMDiagnostic;
0034 class SourceMgr;
0035 class StringRef;
0036 class TargetRegisterClass;
0037 class TargetSubtargetInfo;
0038
0039 struct VRegInfo {
0040   enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN;
0041   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
0042   union {
0043     const TargetRegisterClass *RC;
0044     const RegisterBank *RegBank;
0045   } D;
0046   Register VReg;
0047   Register PreferredReg;
0048   uint8_t Flags = 0;
0049 };
0050
0051 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
0052 using Name2RegBankMap = StringMap<const RegisterBank *>;
0053
0054 struct PerTargetMIParsingState {
0055 private:
0056   const TargetSubtargetInfo &Subtarget;
0057
0058   /// Maps from instruction names to op codes.
0059   StringMap<unsigned> Names2InstrOpCodes;
0060
0061   /// Maps from register names to registers.
0062   StringMap<Register> Names2Regs;
0063
0064   /// Maps from register mask names to register masks.
0065   StringMap<const uint32_t *> Names2RegMasks;
0066
0067   /// Maps from subregister names to subregister indices.
0068   StringMap<unsigned> Names2SubRegIndices;
0069
0070   /// Maps from target index names to target indices.
0071   StringMap<int> Names2TargetIndices;
0072
0073   /// Maps from direct target flag names to the direct target flag values.
0074   StringMap<unsigned> Names2DirectTargetFlags;
0075
0076   /// Maps from direct target flag names to the bitmask target flag values.
0077   StringMap<unsigned> Names2BitmaskTargetFlags;
0078
0079   /// Maps from MMO target flag names to MMO target flag values.
0080   StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags;
0081
0082   /// Maps from register class names to register classes.
0083   Name2RegClassMap Names2RegClasses;
0084
0085   /// Maps from register bank names to register banks.
0086   Name2RegBankMap Names2RegBanks;
0087
0088   void initNames2InstrOpCodes();
0089   void initNames2Regs();
0090   void initNames2RegMasks();
0091   void initNames2SubRegIndices();
0092   void initNames2TargetIndices();
0093   void initNames2DirectTargetFlags();
0094   void initNames2BitmaskTargetFlags();
0095   void initNames2MMOTargetFlags();
0096
0097   void initNames2RegClasses();
0098   void initNames2RegBanks();
0099
0100 public:
0101   /// Try to convert an instruction name to an opcode. Return true if the
0102   /// instruction name is invalid.
0103   bool parseInstrName(StringRef InstrName, unsigned &OpCode);
0104
0105   /// Try to convert a register name to a register number. Return true if the
0106   /// register name is invalid.
0107   bool getRegisterByName(StringRef RegName, Register &Reg);
0108
0109   /// Check if the given identifier is a name of a register mask.
0110   ///
0111   /// Return null if the identifier isn't a register mask.
0112   const uint32_t *getRegMask(StringRef Identifier);
0113
0114   /// Check if the given identifier is a name of a subregister index.
0115   ///
0116   /// Return 0 if the name isn't a subregister index class.
0117   unsigned getSubRegIndex(StringRef Name);
0118
0119   /// Try to convert a name of target index to the corresponding target index.
0120   ///
0121   /// Return true if the name isn't a name of a target index.
0122   bool getTargetIndex(StringRef Name, int &Index);
0123
0124   /// Try to convert a name of a direct target flag to the corresponding
0125   /// target flag.
0126   ///
0127   /// Return true if the name isn't a name of a direct flag.
0128   bool getDirectTargetFlag(StringRef Name, unsigned &Flag);
0129
0130   /// Try to convert a name of a bitmask target flag to the corresponding
0131   /// target flag.
0132   ///
0133   /// Return true if the name isn't a name of a bitmask target flag.
0134   bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag);
0135
0136   /// Try to convert a name of a MachineMemOperand target flag to the
0137   /// corresponding target flag.
0138   ///
0139   /// Return true if the name isn't a name of a target MMO flag.
0140   bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag);
0141
0142   /// Check if the given identifier is a name of a register class.
0143   ///
0144   /// Return null if the name isn't a register class.
0145   const TargetRegisterClass *getRegClass(StringRef Name);
0146
0147   /// Check if the given identifier is a name of a register bank.
0148   ///
0149   /// Return null if the name isn't a register bank.
0150   const RegisterBank *getRegBank(StringRef Name);
0151
0152   bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const;
0153
0154   PerTargetMIParsingState(const TargetSubtargetInfo &STI)
0155     : Subtarget(STI) {
0156     initNames2RegClasses();
0157     initNames2RegBanks();
0158   }
0159
0160   ~PerTargetMIParsingState() = default;
0161
0162   void setTarget(const TargetSubtargetInfo &NewSubtarget);
0163 };
0164
0165 struct PerFunctionMIParsingState {
0166   BumpPtrAllocator Allocator;
0167   MachineFunction &MF;
0168   SourceMgr *SM;
0169   const SlotMapping &IRSlots;
0170   PerTargetMIParsingState &Target;
0171
0172   std::map<unsigned, TrackingMDNodeRef> MachineMetadataNodes;
0173   std::map<unsigned, std::pair<TempMDTuple, SMLoc>> MachineForwardRefMDNodes;
0174
0175   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
0176   DenseMap<Register, VRegInfo *> VRegInfos;
0177   StringMap<VRegInfo *> VRegInfosNamed;
0178   DenseMap<unsigned, int> FixedStackObjectSlots;
0179   DenseMap<unsigned, int> StackObjectSlots;
0180   DenseMap<unsigned, unsigned> ConstantPoolSlots;
0181   DenseMap<unsigned, unsigned> JumpTableSlots;
0182
0183   /// Maps from slot numbers to function's unnamed values.
0184   DenseMap<unsigned, const Value *> Slots2Values;
0185
0186   PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
0187                             const SlotMapping &IRSlots,
0188                             PerTargetMIParsingState &Target);
0189
0190   VRegInfo &getVRegInfo(Register Num);
0191   VRegInfo &getVRegInfoNamed(StringRef RegName);
0192   const Value *getIRValue(unsigned Slot);
0193 };
0194
0195 /// Parse the machine basic block definitions, and skip the machine
0196 /// instructions.
0197 ///
0198 /// This function runs the first parsing pass on the machine function's body.
0199 /// It parses only the machine basic block definitions and creates the machine
0200 /// basic blocks in the given machine function.
0201 ///
0202 /// The machine instructions aren't parsed during the first pass because all
0203 /// the machine basic blocks aren't defined yet - this makes it impossible to
0204 /// resolve the machine basic block references.
0205 ///
0206 /// Return true if an error occurred.
0207 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
0208                                        StringRef Src, SMDiagnostic &Error);
0209
0210 /// Parse the machine instructions.
0211 ///
0212 /// This function runs the second parsing pass on the machine function's body.
0213 /// It skips the machine basic block definitions and parses only the machine
0214 /// instructions and basic block attributes like liveins and successors.
0215 ///
0216 /// The second parsing pass assumes that the first parsing pass already ran
0217 /// on the given source string.
0218 ///
0219 /// Return true if an error occurred.
0220 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
0221                               SMDiagnostic &Error);
0222
0223 bool parseMBBReference(PerFunctionMIParsingState &PFS,
0224                        MachineBasicBlock *&MBB, StringRef Src,
0225                        SMDiagnostic &Error);
0226
0227 bool parseRegisterReference(PerFunctionMIParsingState &PFS,
0228                             Register &Reg, StringRef Src,
0229                             SMDiagnostic &Error);
0230
0231 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg,
0232                                  StringRef Src, SMDiagnostic &Error);
0233
0234 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
0235                                    VRegInfo *&Info, StringRef Src,
0236                                    SMDiagnostic &Error);
0237
0238 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
0239                                StringRef Src, SMDiagnostic &Error);
0240
0241 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
0242                  SMDiagnostic &Error);
0243
0244 bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src,
0245                           SMRange SourceRange, SMDiagnostic &Error);
0246
0247 } // end namespace llvm
0248
0249 #endif // LLVM_CODEGEN_MIRPARSER_MIPARSER_H