llvm/CodeGen/LiveStacks.h

0001 //===- LiveStacks.h - Live Stack Slot Analysis ------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file implements the live stack slot analysis pass. It is analogous to
0010 // live interval analysis except it's analyzing liveness of stack slots rather
0011 // than registers.
0012 //
0013 //===----------------------------------------------------------------------===//
0014
0015 #ifndef LLVM_CODEGEN_LIVESTACKS_H
0016 #define LLVM_CODEGEN_LIVESTACKS_H
0017
0018 #include "llvm/CodeGen/LiveInterval.h"
0019 #include "llvm/CodeGen/MachineFunctionPass.h"
0020 #include "llvm/IR/PassManager.h"
0021 #include "llvm/InitializePasses.h"
0022 #include "llvm/PassRegistry.h"
0023 #include <cassert>
0024 #include <map>
0025 #include <unordered_map>
0026
0027 namespace llvm {
0028
0029 class AnalysisUsage;
0030 class MachineFunction;
0031 class Module;
0032 class raw_ostream;
0033 class TargetRegisterClass;
0034 class TargetRegisterInfo;
0035
0036 class LiveStacks {
0037   const TargetRegisterInfo *TRI = nullptr;
0038
0039   /// Special pool allocator for VNInfo's (LiveInterval val#).
0040   ///
0041   VNInfo::Allocator VNInfoAllocator;
0042
0043   /// S2IMap - Stack slot indices to live interval mapping.
0044   using SS2IntervalMap = std::unordered_map<int, LiveInterval>;
0045   SS2IntervalMap S2IMap;
0046
0047   /// S2RCMap - Stack slot indices to register class mapping.
0048   std::map<int, const TargetRegisterClass *> S2RCMap;
0049
0050 public:
0051   using iterator = SS2IntervalMap::iterator;
0052   using const_iterator = SS2IntervalMap::const_iterator;
0053
0054   const_iterator begin() const { return S2IMap.begin(); }
0055   const_iterator end() const { return S2IMap.end(); }
0056   iterator begin() { return S2IMap.begin(); }
0057   iterator end() { return S2IMap.end(); }
0058
0059   unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
0060
0061   LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
0062
0063   LiveInterval &getInterval(int Slot) {
0064     assert(Slot >= 0 && "Spill slot indice must be >= 0");
0065     SS2IntervalMap::iterator I = S2IMap.find(Slot);
0066     assert(I != S2IMap.end() && "Interval does not exist for stack slot");
0067     return I->second;
0068   }
0069
0070   const LiveInterval &getInterval(int Slot) const {
0071     assert(Slot >= 0 && "Spill slot indice must be >= 0");
0072     SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
0073     assert(I != S2IMap.end() && "Interval does not exist for stack slot");
0074     return I->second;
0075   }
0076
0077   bool hasInterval(int Slot) const { return S2IMap.count(Slot); }
0078
0079   const TargetRegisterClass *getIntervalRegClass(int Slot) const {
0080     assert(Slot >= 0 && "Spill slot indice must be >= 0");
0081     std::map<int, const TargetRegisterClass *>::const_iterator I =
0082         S2RCMap.find(Slot);
0083     assert(I != S2RCMap.end() &&
0084            "Register class info does not exist for stack slot");
0085     return I->second;
0086   }
0087
0088   VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; }
0089
0090   void releaseMemory();
0091   /// init - analysis entry point
0092   void init(MachineFunction &MF);
0093   void print(raw_ostream &O, const Module *M = nullptr) const;
0094 };
0095
0096 class LiveStacksWrapperLegacy : public MachineFunctionPass {
0097   LiveStacks Impl;
0098
0099 public:
0100   static char ID; // Pass identification, replacement for typeid
0101
0102   LiveStacksWrapperLegacy() : MachineFunctionPass(ID) {
0103     initializeLiveStacksWrapperLegacyPass(*PassRegistry::getPassRegistry());
0104   }
0105
0106   LiveStacks &getLS() { return Impl; }
0107   const LiveStacks &getLS() const { return Impl; }
0108
0109   void getAnalysisUsage(AnalysisUsage &AU) const override;
0110   void releaseMemory() override;
0111
0112   /// runOnMachineFunction - pass entry point
0113   bool runOnMachineFunction(MachineFunction &) override;
0114
0115   /// print - Implement the dump method.
0116   void print(raw_ostream &O, const Module * = nullptr) const override;
0117 };
0118
0119 class LiveStacksAnalysis : public AnalysisInfoMixin<LiveStacksAnalysis> {
0120   static AnalysisKey Key;
0121   friend AnalysisInfoMixin<LiveStacksAnalysis>;
0122
0123 public:
0124   using Result = LiveStacks;
0125
0126   LiveStacks run(MachineFunction &MF, MachineFunctionAnalysisManager &);
0127 };
0128
0129 class LiveStacksPrinterPass : public PassInfoMixin<LiveStacksPrinterPass> {
0130   raw_ostream &OS;
0131
0132 public:
0133   LiveStacksPrinterPass(raw_ostream &OS) : OS(OS) {}
0134   PreservedAnalyses run(MachineFunction &MF,
0135                         MachineFunctionAnalysisManager &AM);
0136 };
0137 } // end namespace llvm
0138
0139 #endif