llvm/CodeGen/DetectDeadLanes.h

0001 //===- DetectDeadLanes.h - SubRegister Lane Usage Analysis --*- C++ -*-----===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 /// \file
0010 /// Analysis that tracks defined/used subregister lanes across COPY instructions
0011 /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
0012 /// INSERT_SUBREG, EXTRACT_SUBREG).
0013 /// The information is used to detect dead definitions and the usage of
0014 /// (completely) undefined values and mark the operands as such.
0015 /// This pass is necessary because the dead/undef status is not obvious anymore
0016 /// when subregisters are involved.
0017 ///
0018 /// Example:
0019 ///    %0 = some definition
0020 ///    %1 = IMPLICIT_DEF
0021 ///    %2 = REG_SEQUENCE %0, sub0, %1, sub1
0022 ///    %3 = EXTRACT_SUBREG %2, sub1
0023 ///       = use %3
0024 /// The %0 definition is dead and %3 contains an undefined value.
0025 //
0026 //===----------------------------------------------------------------------===//
0027
0028 #ifndef LLVM_CODEGEN_DETECTDEADLANES_H
0029 #define LLVM_CODEGEN_DETECTDEADLANES_H
0030
0031 #include "llvm/ADT/BitVector.h"
0032 #include "llvm/MC/LaneBitmask.h"
0033 #include <deque>
0034
0035 namespace llvm {
0036
0037 class MachineInstr;
0038 class MachineOperand;
0039 class MachineRegisterInfo;
0040 class TargetRegisterInfo;
0041
0042 class DeadLaneDetector {
0043 public:
0044   /// Contains a bitmask of which lanes of a given virtual register are
0045   /// defined and which ones are actually used.
0046   struct VRegInfo {
0047     LaneBitmask UsedLanes;
0048     LaneBitmask DefinedLanes;
0049   };
0050
0051   DeadLaneDetector(const MachineRegisterInfo *MRI,
0052                    const TargetRegisterInfo *TRI);
0053
0054   /// Update the \p DefinedLanes and the \p UsedLanes for all virtual registers.
0055   void computeSubRegisterLaneBitInfo();
0056
0057   const VRegInfo &getVRegInfo(unsigned RegIdx) const {
0058     return VRegInfos[RegIdx];
0059   }
0060
0061   bool isDefinedByCopy(unsigned RegIdx) const {
0062     return DefinedByCopy.test(RegIdx);
0063   }
0064
0065 private:
0066   /// Add used lane bits on the register used by operand \p MO. This translates
0067   /// the bitmask based on the operands subregister, and puts the register into
0068   /// the worklist if any new bits were added.
0069   void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
0070
0071   /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
0072   /// COPY-like instruction determine the lanes used on the use operands
0073   /// and call addUsedLanesOnOperand() for them.
0074   void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
0075
0076   /// Given a use regiser operand \p Use and a mask of defined lanes, check
0077   /// if the operand belongs to a lowersToCopies() instruction, transfer the
0078   /// mask to the def and put the instruction into the worklist.
0079   void transferDefinedLanesStep(const MachineOperand &Use,
0080                                 LaneBitmask DefinedLanes);
0081
0082 public:
0083   /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
0084   /// of COPY-like instruction, determine which lanes are defined at the output
0085   /// operand \p Def.
0086   LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
0087                                    LaneBitmask DefinedLanes) const;
0088
0089   /// Given a mask \p UsedLanes used from the output of instruction \p MI
0090   /// determine which lanes are used from operand \p MO of this instruction.
0091   LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
0092                                 const MachineOperand &MO) const;
0093
0094 private:
0095   LaneBitmask determineInitialDefinedLanes(unsigned Reg);
0096   LaneBitmask determineInitialUsedLanes(unsigned Reg);
0097
0098   const MachineRegisterInfo *MRI;
0099   const TargetRegisterInfo *TRI;
0100
0101   void PutInWorklist(unsigned RegIdx) {
0102     if (WorklistMembers.test(RegIdx))
0103       return;
0104     WorklistMembers.set(RegIdx);
0105     Worklist.push_back(RegIdx);
0106   }
0107
0108   std::unique_ptr<VRegInfo[]> VRegInfos;
0109   /// Worklist containing virtreg indexes.
0110   std::deque<unsigned> Worklist;
0111   BitVector WorklistMembers;
0112   /// This bitvector is set for each vreg index where the vreg is defined
0113   /// by an instruction where lowersToCopies()==true.
0114   BitVector DefinedByCopy;
0115 };
0116
0117 } // end namespace llvm
0118
0119 #endif // LLVM_CODEGEN_DETECTDEADLANES_H