llvm/CodeGen/AntiDepBreaker.h

0001 //===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file implements the AntiDepBreaker class, which implements
0010 // anti-dependence breaking heuristics for post-register-allocation scheduling.
0011 //
0012 //===----------------------------------------------------------------------===//
0013
0014 #ifndef LLVM_CODEGEN_ANTIDEPBREAKER_H
0015 #define LLVM_CODEGEN_ANTIDEPBREAKER_H
0016
0017 #include "llvm/ADT/iterator_range.h"
0018 #include "llvm/CodeGen/MachineBasicBlock.h"
0019 #include "llvm/CodeGen/MachineInstr.h"
0020 #include "llvm/CodeGen/TargetSubtargetInfo.h"
0021 #include "llvm/Support/Compiler.h"
0022 #include <utility>
0023 #include <vector>
0024
0025 namespace llvm {
0026
0027 class RegisterClassInfo;
0028
0029 /// This class works in conjunction with the post-RA scheduler to rename
0030 /// registers to break register anti-dependencies (WAR hazards).
0031 class AntiDepBreaker {
0032 public:
0033   using DbgValueVector =
0034       std::vector<std::pair<MachineInstr *, MachineInstr *>>;
0035
0036   virtual ~AntiDepBreaker();
0037
0038   /// Initialize anti-dep breaking for a new basic block.
0039   virtual void StartBlock(MachineBasicBlock *BB) = 0;
0040
0041   /// Identifiy anti-dependencies within a basic-block region and break them by
0042   /// renaming registers. Return the number of anti-dependencies broken.
0043   virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
0044                                          MachineBasicBlock::iterator Begin,
0045                                          MachineBasicBlock::iterator End,
0046                                          unsigned InsertPosIndex,
0047                                          DbgValueVector &DbgValues) = 0;
0048
0049   /// Update liveness information to account for the current
0050   /// instruction, which will not be scheduled.
0051   virtual void Observe(MachineInstr &MI, unsigned Count,
0052                        unsigned InsertPosIndex) = 0;
0053
0054   /// Finish anti-dep breaking for a basic block.
0055   virtual void FinishBlock() = 0;
0056
0057   /// Update DBG_VALUE or DBG_PHI if dependency breaker is updating
0058   /// other machine instruction to use NewReg.
0059   void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
0060     if (MI.isDebugValue()) {
0061       if (MI.getDebugOperand(0).isReg() &&
0062           MI.getDebugOperand(0).getReg() == OldReg)
0063         MI.getDebugOperand(0).setReg(NewReg);
0064     } else if (MI.isDebugPHI()) {
0065       if (MI.getOperand(0).isReg() &&
0066           MI.getOperand(0).getReg() == OldReg)
0067         MI.getOperand(0).setReg(NewReg);
0068     } else {
0069       llvm_unreachable("MI is not DBG_VALUE / DBG_PHI!");
0070     }
0071   }
0072
0073   /// Update all DBG_VALUE instructions that may be affected by the dependency
0074   /// breaker's update of ParentMI to use NewReg.
0075   void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
0076                        unsigned OldReg, unsigned NewReg) {
0077     // The following code is dependent on the order in which the DbgValues are
0078     // constructed in ScheduleDAGInstrs::buildSchedGraph.
0079     MachineInstr *PrevDbgMI = nullptr;
0080     for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
0081       MachineInstr *PrevMI = DV.second;
0082       if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
0083         MachineInstr *DbgMI = DV.first;
0084         UpdateDbgValue(*DbgMI, OldReg, NewReg);
0085         PrevDbgMI = DbgMI;
0086       } else if (PrevDbgMI) {
0087         break; // If no match and already found a DBG_VALUE, we're done.
0088       }
0089     }
0090   }
0091 };
0092
0093 AntiDepBreaker *createAggressiveAntiDepBreaker(
0094     MachineFunction &MFi, const RegisterClassInfo &RCI,
0095     TargetSubtargetInfo::RegClassVector &CriticalPathRCs);
0096
0097 AntiDepBreaker *createCriticalAntiDepBreaker(MachineFunction &MFi,
0098                                              const RegisterClassInfo &RCI);
0099
0100 } // end namespace llvm
0101
0102 #endif // LLVM_CODEGEN_ANTIDEPBREAKER_H