lldb/Utility/ArchSpec.h

0001 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008
0009 #ifndef LLDB_UTILITY_ARCHSPEC_H
0010 #define LLDB_UTILITY_ARCHSPEC_H
0011
0012 #include "lldb/Utility/CompletionRequest.h"
0013 #include "lldb/lldb-enumerations.h"
0014 #include "lldb/lldb-forward.h"
0015 #include "lldb/lldb-private-enumerations.h"
0016 #include "llvm/ADT/StringRef.h"
0017 #include "llvm/TargetParser/Triple.h"
0018 #include <cstddef>
0019 #include <cstdint>
0020 #include <string>
0021
0022 namespace lldb_private {
0023
0024 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
0025 /// specification class.
0026 ///
0027 /// A class designed to be created from a cpu type and subtype, a
0028 /// string representation, or an llvm::Triple.  Keeping all of the conversions
0029 /// of strings to architecture enumeration values confined to this class
0030 /// allows new architecture support to be added easily.
0031 class ArchSpec {
0032 public:
0033   enum MIPSSubType {
0034     eMIPSSubType_unknown,
0035     eMIPSSubType_mips32,
0036     eMIPSSubType_mips32r2,
0037     eMIPSSubType_mips32r6,
0038     eMIPSSubType_mips32el,
0039     eMIPSSubType_mips32r2el,
0040     eMIPSSubType_mips32r6el,
0041     eMIPSSubType_mips64,
0042     eMIPSSubType_mips64r2,
0043     eMIPSSubType_mips64r6,
0044     eMIPSSubType_mips64el,
0045     eMIPSSubType_mips64r2el,
0046     eMIPSSubType_mips64r6el,
0047   };
0048
0049   // Masks for the ases word of an ABI flags structure.
0050   enum MIPSASE {
0051     eMIPSAse_dsp = 0x00000001,       // DSP ASE
0052     eMIPSAse_dspr2 = 0x00000002,     // DSP R2 ASE
0053     eMIPSAse_eva = 0x00000004,       // Enhanced VA Scheme
0054     eMIPSAse_mcu = 0x00000008,       // MCU (MicroController) ASE
0055     eMIPSAse_mdmx = 0x00000010,      // MDMX ASE
0056     eMIPSAse_mips3d = 0x00000020,    // MIPS-3D ASE
0057     eMIPSAse_mt = 0x00000040,        // MT ASE
0058     eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
0059     eMIPSAse_virt = 0x00000100,      // VZ ASE
0060     eMIPSAse_msa = 0x00000200,       // MSA ASE
0061     eMIPSAse_mips16 = 0x00000400,    // MIPS16 ASE
0062     eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
0063     eMIPSAse_xpa = 0x00001000,       // XPA ASE
0064     eMIPSAse_mask = 0x00001fff,
0065     eMIPSABI_O32 = 0x00002000,
0066     eMIPSABI_N32 = 0x00004000,
0067     eMIPSABI_N64 = 0x00008000,
0068     eMIPSABI_O64 = 0x00020000,
0069     eMIPSABI_EABI32 = 0x00040000,
0070     eMIPSABI_EABI64 = 0x00080000,
0071     eMIPSABI_mask = 0x000ff000
0072   };
0073
0074   // MIPS Floating point ABI Values
0075   enum MIPS_ABI_FP {
0076     eMIPS_ABI_FP_ANY = 0x00000000,
0077     eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
0078     eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
0079     eMIPS_ABI_FP_SOFT = 0x00300000,   // soft float
0080     eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
0081     eMIPS_ABI_FP_XX = 0x00500000,     // -mfpxx
0082     eMIPS_ABI_FP_64 = 0x00600000,     // -mips32r2 -mfp64
0083     eMIPS_ABI_FP_64A = 0x00700000,    // -mips32r2 -mfp64 -mno-odd-spreg
0084     eMIPS_ABI_FP_mask = 0x00700000
0085   };
0086
0087   // ARM specific e_flags
0088   enum ARMeflags {
0089     eARM_abi_soft_float = 0x00000200,
0090     eARM_abi_hard_float = 0x00000400
0091   };
0092
0093   enum RISCVeflags {
0094     eRISCV_rvc              = 0x00000001, /// RVC, +c
0095     eRISCV_float_abi_soft   = 0x00000000, /// soft float
0096     eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f
0097     eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d
0098     eRISCV_float_abi_quad   = 0x00000006, /// quad precision floating point, +q
0099     eRISCV_float_abi_mask   = 0x00000006,
0100     eRISCV_rve              = 0x00000008, /// RVE, +e
0101     eRISCV_tso              = 0x00000010, /// RVTSO (total store ordering)
0102   };
0103
0104   enum RISCVSubType {
0105     eRISCVSubType_unknown,
0106     eRISCVSubType_riscv32,
0107     eRISCVSubType_riscv64,
0108   };
0109
0110   enum LoongArcheflags {
0111     eLoongArch_abi_soft_float = 0x00000000, /// soft float
0112     eLoongArch_abi_single_float =
0113         0x00000001, /// single precision floating point, +f
0114     eLoongArch_abi_double_float =
0115         0x00000002, /// double precision floating point, +d
0116     eLoongArch_abi_mask = 0x00000003,
0117   };
0118
0119   enum LoongArchSubType {
0120     eLoongArchSubType_unknown,
0121     eLoongArchSubType_loongarch32,
0122     eLoongArchSubType_loongarch64,
0123   };
0124
0125   enum Core {
0126     eCore_arm_generic,
0127     eCore_arm_armv4,
0128     eCore_arm_armv4t,
0129     eCore_arm_armv5,
0130     eCore_arm_armv5e,
0131     eCore_arm_armv5t,
0132     eCore_arm_armv6,
0133     eCore_arm_armv6m,
0134     eCore_arm_armv7,
0135     eCore_arm_armv7a,
0136     eCore_arm_armv7l,
0137     eCore_arm_armv7f,
0138     eCore_arm_armv7s,
0139     eCore_arm_armv7k,
0140     eCore_arm_armv7m,
0141     eCore_arm_armv7em,
0142     eCore_arm_xscale,
0143
0144     eCore_thumb,
0145     eCore_thumbv4t,
0146     eCore_thumbv5,
0147     eCore_thumbv5e,
0148     eCore_thumbv6,
0149     eCore_thumbv6m,
0150     eCore_thumbv7,
0151     eCore_thumbv7s,
0152     eCore_thumbv7k,
0153     eCore_thumbv7f,
0154     eCore_thumbv7m,
0155     eCore_thumbv7em,
0156     eCore_arm_arm64,
0157     eCore_arm_armv8,
0158     eCore_arm_armv8a,
0159     eCore_arm_armv8l,
0160     eCore_arm_arm64e,
0161     eCore_arm_arm64_32,
0162     eCore_arm_aarch64,
0163
0164     eCore_mips32,
0165     eCore_mips32r2,
0166     eCore_mips32r3,
0167     eCore_mips32r5,
0168     eCore_mips32r6,
0169     eCore_mips32el,
0170     eCore_mips32r2el,
0171     eCore_mips32r3el,
0172     eCore_mips32r5el,
0173     eCore_mips32r6el,
0174     eCore_mips64,
0175     eCore_mips64r2,
0176     eCore_mips64r3,
0177     eCore_mips64r5,
0178     eCore_mips64r6,
0179     eCore_mips64el,
0180     eCore_mips64r2el,
0181     eCore_mips64r3el,
0182     eCore_mips64r5el,
0183     eCore_mips64r6el,
0184
0185     eCore_msp430,
0186
0187     eCore_ppc_generic,
0188     eCore_ppc_ppc601,
0189     eCore_ppc_ppc602,
0190     eCore_ppc_ppc603,
0191     eCore_ppc_ppc603e,
0192     eCore_ppc_ppc603ev,
0193     eCore_ppc_ppc604,
0194     eCore_ppc_ppc604e,
0195     eCore_ppc_ppc620,
0196     eCore_ppc_ppc750,
0197     eCore_ppc_ppc7400,
0198     eCore_ppc_ppc7450,
0199     eCore_ppc_ppc970,
0200
0201     eCore_ppc64le_generic,
0202     eCore_ppc64_generic,
0203     eCore_ppc64_ppc970_64,
0204
0205     eCore_s390x_generic,
0206
0207     eCore_sparc_generic,
0208
0209     eCore_sparc9_generic,
0210
0211     eCore_x86_32_i386,
0212     eCore_x86_32_i486,
0213     eCore_x86_32_i486sx,
0214     eCore_x86_32_i686,
0215
0216     eCore_x86_64_x86_64,
0217     eCore_x86_64_x86_64h, // Haswell enabled x86_64
0218     eCore_x86_64_amd64,
0219
0220     eCore_hexagon_generic,
0221     eCore_hexagon_hexagonv4,
0222     eCore_hexagon_hexagonv5,
0223
0224     eCore_riscv32,
0225     eCore_riscv64,
0226
0227     eCore_loongarch32,
0228     eCore_loongarch64,
0229
0230     eCore_uknownMach32,
0231     eCore_uknownMach64,
0232
0233     eCore_arc, // little endian ARC
0234
0235     eCore_avr,
0236
0237     eCore_wasm32,
0238
0239     kNumCores,
0240
0241     kCore_invalid,
0242     // The following constants are used for wildcard matching only
0243     kCore_any,
0244     kCore_arm_any,
0245     kCore_ppc_any,
0246     kCore_ppc64_any,
0247     kCore_x86_32_any,
0248     kCore_x86_64_any,
0249     kCore_hexagon_any,
0250
0251     kCore_arm_first = eCore_arm_generic,
0252     kCore_arm_last = eCore_arm_xscale,
0253
0254     kCore_thumb_first = eCore_thumb,
0255     kCore_thumb_last = eCore_thumbv7em,
0256
0257     kCore_ppc_first = eCore_ppc_generic,
0258     kCore_ppc_last = eCore_ppc_ppc970,
0259
0260     kCore_ppc64_first = eCore_ppc64_generic,
0261     kCore_ppc64_last = eCore_ppc64_ppc970_64,
0262
0263     kCore_x86_32_first = eCore_x86_32_i386,
0264     kCore_x86_32_last = eCore_x86_32_i686,
0265
0266     kCore_x86_64_first = eCore_x86_64_x86_64,
0267     kCore_x86_64_last = eCore_x86_64_x86_64h,
0268
0269     kCore_hexagon_first = eCore_hexagon_generic,
0270     kCore_hexagon_last = eCore_hexagon_hexagonv5,
0271
0272     kCore_mips32_first = eCore_mips32,
0273     kCore_mips32_last = eCore_mips32r6,
0274
0275     kCore_mips32el_first = eCore_mips32el,
0276     kCore_mips32el_last = eCore_mips32r6el,
0277
0278     kCore_mips64_first = eCore_mips64,
0279     kCore_mips64_last = eCore_mips64r6,
0280
0281     kCore_mips64el_first = eCore_mips64el,
0282     kCore_mips64el_last = eCore_mips64r6el,
0283
0284     kCore_mips_first = eCore_mips32,
0285     kCore_mips_last = eCore_mips64r6el
0286
0287   };
0288
0289   /// Default constructor.
0290   ///
0291   /// Default constructor that initializes the object with invalid cpu type
0292   /// and subtype values.
0293   ArchSpec();
0294
0295   /// Constructor over triple.
0296   ///
0297   /// Constructs an ArchSpec with properties consistent with the given Triple.
0298   explicit ArchSpec(const llvm::Triple &triple);
0299   explicit ArchSpec(const char *triple_cstr);
0300   explicit ArchSpec(llvm::StringRef triple_str);
0301   /// Constructor over architecture name.
0302   ///
0303   /// Constructs an ArchSpec with properties consistent with the given object
0304   /// type and architecture name.
0305   explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
0306                     uint32_t cpu_subtype);
0307
0308   /// Destructor.
0309   ~ArchSpec();
0310
0311   /// Returns true if the OS, vendor and environment fields of the triple are
0312   /// unset. The triple is expected to be normalized
0313   /// (llvm::Triple::normalize).
0314   static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
0315
0316   static void ListSupportedArchNames(StringList &list);
0317   static void AutoComplete(CompletionRequest &request);
0318
0319   /// Returns a static string representing the current architecture.
0320   ///
0321   /// \return A static string corresponding to the current
0322   ///         architecture.
0323   const char *GetArchitectureName() const;
0324
0325   /// if MIPS architecture return true.
0326   ///
0327   ///  \return a boolean value.
0328   bool IsMIPS() const;
0329
0330   /// Returns a string representing current architecture as a target CPU for
0331   /// tools like compiler, disassembler etc.
0332   ///
0333   /// \return A string representing target CPU for the current
0334   ///         architecture.
0335   std::string GetClangTargetCPU() const;
0336
0337   /// Return a string representing target application ABI.
0338   ///
0339   /// \return A string representing target application ABI.
0340   std::string GetTargetABI() const;
0341
0342   /// Clears the object state.
0343   ///
0344   /// Clears the object state back to a default invalid state.
0345   void Clear();
0346
0347   /// Returns the size in bytes of an address of the current architecture.
0348   ///
0349   /// \return The byte size of an address of the current architecture.
0350   uint32_t GetAddressByteSize() const;
0351
0352   /// Returns a machine family for the current architecture.
0353   ///
0354   /// \return An LLVM arch type.
0355   llvm::Triple::ArchType GetMachine() const;
0356
0357   /// Tests if this ArchSpec is valid.
0358   ///
0359   /// \return True if the current architecture is valid, false
0360   ///         otherwise.
0361   bool IsValid() const {
0362     return m_core >= eCore_arm_generic && m_core < kNumCores;
0363   }
0364   explicit operator bool() const { return IsValid(); }
0365
0366   bool TripleVendorWasSpecified() const {
0367     return !m_triple.getVendorName().empty();
0368   }
0369
0370   bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
0371
0372   bool TripleEnvironmentWasSpecified() const {
0373     return m_triple.hasEnvironment();
0374   }
0375
0376   /// Merges fields from another ArchSpec into this ArchSpec.
0377   ///
0378   /// This will use the supplied ArchSpec to fill in any fields of the triple
0379   /// in this ArchSpec which were unspecified.  This can be used to refine a
0380   /// generic ArchSpec with a more specific one. For example, if this
0381   /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
0382   /// have a triple which is x64-pc-windows-msvc, then merging that triple
0383   /// into this one will result in the triple i386-pc-windows-msvc.
0384   ///
0385   void MergeFrom(const ArchSpec &other);
0386
0387   /// Change the architecture object type, CPU type and OS type.
0388   ///
0389   /// \param[in] arch_type The object type of this ArchSpec.
0390   ///
0391   /// \param[in] cpu The required CPU type.
0392   ///
0393   /// \param[in] os The optional OS type
0394   /// The default value of 0 was chosen to from the ELF spec value
0395   /// ELFOSABI_NONE.  ELF is the only one using this parameter.  If another
0396   /// format uses this parameter and 0 does not work, use a value over
0397   /// 255 because in the ELF header this is value is only a byte.
0398   ///
0399   /// \return True if the object, and CPU were successfully set.
0400   ///
0401   /// As a side effect, the vendor value is usually set to unknown. The
0402   /// exceptions are
0403   ///   aarch64-apple-ios
0404   ///   arm-apple-ios
0405   ///   thumb-apple-ios
0406   ///   x86-apple-
0407   ///   x86_64-apple-
0408   ///
0409   /// As a side effect, the os value is usually set to unknown The exceptions
0410   /// are
0411   ///   *-*-aix
0412   ///   aarch64-apple-ios
0413   ///   arm-apple-ios
0414   ///   thumb-apple-ios
0415   ///   powerpc-apple-darwin
0416   ///   *-*-freebsd
0417   ///   *-*-linux
0418   ///   *-*-netbsd
0419   ///   *-*-openbsd
0420   ///   *-*-solaris
0421   bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
0422                        uint32_t os = 0);
0423
0424   /// Returns the byte order for the architecture specification.
0425   ///
0426   /// \return The endian enumeration for the current endianness of
0427   ///     the architecture specification
0428   lldb::ByteOrder GetByteOrder() const;
0429
0430   /// Sets this ArchSpec's byte order.
0431   ///
0432   /// In the common case there is no need to call this method as the byte
0433   /// order can almost always be determined by the architecture. However, many
0434   /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
0435   /// byte order may be incorrect.
0436   void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
0437
0438   uint32_t GetMinimumOpcodeByteSize() const;
0439
0440   uint32_t GetMaximumOpcodeByteSize() const;
0441
0442   Core GetCore() const { return m_core; }
0443
0444   uint32_t GetMachOCPUType() const;
0445
0446   uint32_t GetMachOCPUSubType() const;
0447
0448   /// Architecture data byte width accessor
0449   ///
0450   /// \return the size in 8-bit (host) bytes of a minimum addressable unit
0451   /// from the Architecture's data bus
0452   uint32_t GetDataByteSize() const;
0453
0454   /// Architecture code byte width accessor
0455   ///
0456   /// \return the size in 8-bit (host) bytes of a minimum addressable unit
0457   /// from the Architecture's code bus
0458   uint32_t GetCodeByteSize() const;
0459
0460   /// Architecture triple accessor.
0461   ///
0462   /// \return A triple describing this ArchSpec.
0463   llvm::Triple &GetTriple() { return m_triple; }
0464
0465   /// Architecture triple accessor.
0466   ///
0467   /// \return A triple describing this ArchSpec.
0468   const llvm::Triple &GetTriple() const { return m_triple; }
0469
0470   void DumpTriple(llvm::raw_ostream &s) const;
0471
0472   /// Architecture triple setter.
0473   ///
0474   /// Configures this ArchSpec according to the given triple.  If the triple
0475   /// has unknown components in all of the vendor, OS, and the optional
0476   /// environment field (i.e. "i386-unknown-unknown") then default values are
0477   /// taken from the host.  Architecture and environment components are used
0478   /// to further resolve the CPU type and subtype, endian characteristics,
0479   /// etc.
0480   ///
0481   /// \return A triple describing this ArchSpec.
0482   bool SetTriple(const llvm::Triple &triple);
0483
0484   bool SetTriple(llvm::StringRef triple_str);
0485
0486   /// Returns the default endianness of the architecture.
0487   ///
0488   /// \return The endian enumeration for the default endianness of
0489   ///         the architecture.
0490   lldb::ByteOrder GetDefaultEndian() const;
0491
0492   /// Returns true if 'char' is a signed type by default in the architecture
0493   /// false otherwise
0494   ///
0495   /// \return True if 'char' is a signed type by default on the
0496   ///         architecture and false otherwise.
0497   bool CharIsSignedByDefault() const;
0498
0499   enum MatchType : bool { CompatibleMatch, ExactMatch };
0500
0501   /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of
0502   /// matching that is to be done. CompatibleMatch requires only a compatible
0503   /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an
0504   /// exact match (armv7s is not an exact match with armv7).
0505   ///
0506   /// \return true if the two ArchSpecs match.
0507   bool IsMatch(const ArchSpec &rhs, MatchType match) const;
0508
0509   /// Shorthand for IsMatch(rhs, ExactMatch).
0510   bool IsExactMatch(const ArchSpec &rhs) const {
0511     return IsMatch(rhs, ExactMatch);
0512   }
0513
0514   /// Shorthand for IsMatch(rhs, CompatibleMatch).
0515   bool IsCompatibleMatch(const ArchSpec &rhs) const {
0516     return IsMatch(rhs, CompatibleMatch);
0517   }
0518
0519   bool IsFullySpecifiedTriple() const;
0520
0521   /// Detect whether this architecture uses thumb code exclusively
0522   ///
0523   /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
0524   /// the Thumb instructions, never Arm.  We should normally pick up
0525   /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
0526   /// on each function - but when doing bare-boards low level debugging
0527   /// (especially common with these embedded processors), we may not have
0528   /// those things easily accessible.
0529   ///
0530   /// \return true if this is an arm ArchSpec which can only execute Thumb
0531   ///         instructions
0532   bool IsAlwaysThumbInstructions() const;
0533
0534   uint32_t GetFlags() const { return m_flags; }
0535
0536   void SetFlags(uint32_t flags) { m_flags = flags; }
0537
0538   void SetFlags(const std::string &elf_abi);
0539
0540 protected:
0541   void UpdateCore();
0542
0543   llvm::Triple m_triple;
0544   Core m_core = kCore_invalid;
0545   lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid;
0546
0547   // Additional arch flags which we cannot get from triple and core For MIPS
0548   // these are application specific extensions like micromips, mips16 etc.
0549   uint32_t m_flags = 0;
0550
0551   // Called when m_def or m_entry are changed.  Fills in all remaining members
0552   // with default values.
0553   void CoreUpdated(bool update_triple);
0554 };
0555
0556 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
0557 /// operator.
0558 ///
0559 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
0560 ///
0561 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
0562 /// rhs The Left Hand Side ArchSpec object to compare.
0563 ///
0564 /// \return true if \a lhs is less than \a rhs
0565 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
0566 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
0567
0568 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
0569
0570 } // namespace lldb_private
0571
0572 #endif // LLDB_UTILITY_ARCHSPEC_H