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0001 //===----------------------------------------------------------------------===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //
0008 // Compatible with libunwind API documented at:
0009 //   http://www.nongnu.org/libunwind/man/libunwind(3).html
0010 //
0011 //===----------------------------------------------------------------------===//
0012 
0013 #ifndef __LIBUNWIND__
0014 #define __LIBUNWIND__
0015 
0016 #include <__libunwind_config.h>
0017 
0018 #include <stdint.h>
0019 #include <stddef.h>
0020 
0021 #ifdef __APPLE__
0022   #if __clang__
0023     #if __has_include(<Availability.h>)
0024       #include <Availability.h>
0025     #endif
0026   #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
0027     #include <Availability.h>
0028   #endif
0029 
0030   #ifdef __arm__
0031      #define LIBUNWIND_AVAIL __attribute__((unavailable))
0032   #elif defined(__OSX_AVAILABLE_STARTING)
0033     #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
0034   #else
0035     #include <AvailabilityMacros.h>
0036     #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
0037       #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
0038     #else
0039       #define LIBUNWIND_AVAIL __attribute__((unavailable))
0040     #endif
0041   #endif
0042 #else
0043   #define LIBUNWIND_AVAIL
0044 #endif
0045 
0046 #if defined(_WIN32) && defined(__SEH__)
0047   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16)))
0048 #else
0049   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR
0050 #endif
0051 
0052 /* error codes */
0053 enum {
0054   UNW_ESUCCESS      = 0,     /* no error */
0055   UNW_EUNSPEC       = -6540, /* unspecified (general) error */
0056   UNW_ENOMEM        = -6541, /* out of memory */
0057   UNW_EBADREG       = -6542, /* bad register number */
0058   UNW_EREADONLYREG  = -6543, /* attempt to write read-only register */
0059   UNW_ESTOPUNWIND   = -6544, /* stop unwinding */
0060   UNW_EINVALIDIP    = -6545, /* invalid IP */
0061   UNW_EBADFRAME     = -6546, /* bad frame */
0062   UNW_EINVAL        = -6547, /* unsupported operation or bad value */
0063   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
0064   UNW_ENOINFO       = -6549  /* no unwind info found */
0065 #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
0066   , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
0067 #endif
0068 };
0069 
0070 struct unw_context_t {
0071   uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
0072 };
0073 typedef struct unw_context_t unw_context_t;
0074 
0075 struct unw_cursor_t {
0076   uint64_t data[_LIBUNWIND_CURSOR_SIZE];
0077 } LIBUNWIND_CURSOR_ALIGNMENT_ATTR;
0078 typedef struct unw_cursor_t unw_cursor_t;
0079 
0080 typedef struct unw_addr_space *unw_addr_space_t;
0081 
0082 typedef int unw_regnum_t;
0083 typedef uintptr_t unw_word_t;
0084 #if defined(__arm__) && !defined(__ARM_DWARF_EH__) && !defined(__SEH__)
0085 typedef uint64_t unw_fpreg_t;
0086 #else
0087 typedef double unw_fpreg_t;
0088 #endif
0089 
0090 struct unw_proc_info_t {
0091   unw_word_t  start_ip;         /* start address of function */
0092   unw_word_t  end_ip;           /* address after end of function */
0093   unw_word_t  lsda;             /* address of language specific data area, */
0094                                 /*  or zero if not used */
0095   unw_word_t  handler;          /* personality routine, or zero if not used */
0096   unw_word_t  gp;               /* not used */
0097   unw_word_t  flags;            /* not used */
0098   uint32_t    format;           /* compact unwind encoding, or zero if none */
0099   uint32_t    unwind_info_size; /* size of DWARF unwind info, or zero if none */
0100   unw_word_t  unwind_info;      /* address of DWARF unwind info, or zero */
0101   unw_word_t  extra;            /* mach_header of mach-o image containing func */
0102 };
0103 typedef struct unw_proc_info_t unw_proc_info_t;
0104 
0105 #ifdef __cplusplus
0106 extern "C" {
0107 #endif
0108 
0109 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
0110 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
0111 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
0112 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
0113 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
0114 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
0115 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t)  LIBUNWIND_AVAIL;
0116 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
0117 
0118 #ifdef __arm__
0119 /* Save VFP registers in FSTMX format (instead of FSTMD). */
0120 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
0121 #endif
0122 
0123 #ifdef _AIX
0124 extern uintptr_t unw_get_data_rel_base(unw_cursor_t *) LIBUNWIND_AVAIL;
0125 #endif
0126 
0127 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
0128 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
0129 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
0130 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
0131 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
0132 //extern int       unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
0133 
0134 extern unw_addr_space_t unw_local_addr_space;
0135 
0136 #ifdef __cplusplus
0137 }
0138 #endif
0139 
0140 // architecture independent register numbers
0141 enum {
0142   UNW_REG_IP = -1, // instruction pointer
0143   UNW_REG_SP = -2, // stack pointer
0144 };
0145 
0146 // 32-bit x86 registers
0147 enum {
0148   UNW_X86_EAX = 0,
0149   UNW_X86_ECX = 1,
0150   UNW_X86_EDX = 2,
0151   UNW_X86_EBX = 3,
0152   UNW_X86_EBP = 4,
0153   UNW_X86_ESP = 5,
0154   UNW_X86_ESI = 6,
0155   UNW_X86_EDI = 7
0156 };
0157 
0158 // 64-bit x86_64 registers
0159 enum {
0160   UNW_X86_64_RAX = 0,
0161   UNW_X86_64_RDX = 1,
0162   UNW_X86_64_RCX = 2,
0163   UNW_X86_64_RBX = 3,
0164   UNW_X86_64_RSI = 4,
0165   UNW_X86_64_RDI = 5,
0166   UNW_X86_64_RBP = 6,
0167   UNW_X86_64_RSP = 7,
0168   UNW_X86_64_R8  = 8,
0169   UNW_X86_64_R9  = 9,
0170   UNW_X86_64_R10 = 10,
0171   UNW_X86_64_R11 = 11,
0172   UNW_X86_64_R12 = 12,
0173   UNW_X86_64_R13 = 13,
0174   UNW_X86_64_R14 = 14,
0175   UNW_X86_64_R15 = 15,
0176   UNW_X86_64_RIP = 16,
0177   UNW_X86_64_XMM0 = 17,
0178   UNW_X86_64_XMM1 = 18,
0179   UNW_X86_64_XMM2 = 19,
0180   UNW_X86_64_XMM3 = 20,
0181   UNW_X86_64_XMM4 = 21,
0182   UNW_X86_64_XMM5 = 22,
0183   UNW_X86_64_XMM6 = 23,
0184   UNW_X86_64_XMM7 = 24,
0185   UNW_X86_64_XMM8 = 25,
0186   UNW_X86_64_XMM9 = 26,
0187   UNW_X86_64_XMM10 = 27,
0188   UNW_X86_64_XMM11 = 28,
0189   UNW_X86_64_XMM12 = 29,
0190   UNW_X86_64_XMM13 = 30,
0191   UNW_X86_64_XMM14 = 31,
0192   UNW_X86_64_XMM15 = 32,
0193 };
0194 
0195 
0196 // 32-bit ppc register numbers
0197 enum {
0198   UNW_PPC_R0  = 0,
0199   UNW_PPC_R1  = 1,
0200   UNW_PPC_R2  = 2,
0201   UNW_PPC_R3  = 3,
0202   UNW_PPC_R4  = 4,
0203   UNW_PPC_R5  = 5,
0204   UNW_PPC_R6  = 6,
0205   UNW_PPC_R7  = 7,
0206   UNW_PPC_R8  = 8,
0207   UNW_PPC_R9  = 9,
0208   UNW_PPC_R10 = 10,
0209   UNW_PPC_R11 = 11,
0210   UNW_PPC_R12 = 12,
0211   UNW_PPC_R13 = 13,
0212   UNW_PPC_R14 = 14,
0213   UNW_PPC_R15 = 15,
0214   UNW_PPC_R16 = 16,
0215   UNW_PPC_R17 = 17,
0216   UNW_PPC_R18 = 18,
0217   UNW_PPC_R19 = 19,
0218   UNW_PPC_R20 = 20,
0219   UNW_PPC_R21 = 21,
0220   UNW_PPC_R22 = 22,
0221   UNW_PPC_R23 = 23,
0222   UNW_PPC_R24 = 24,
0223   UNW_PPC_R25 = 25,
0224   UNW_PPC_R26 = 26,
0225   UNW_PPC_R27 = 27,
0226   UNW_PPC_R28 = 28,
0227   UNW_PPC_R29 = 29,
0228   UNW_PPC_R30 = 30,
0229   UNW_PPC_R31 = 31,
0230   UNW_PPC_F0  = 32,
0231   UNW_PPC_F1  = 33,
0232   UNW_PPC_F2  = 34,
0233   UNW_PPC_F3  = 35,
0234   UNW_PPC_F4  = 36,
0235   UNW_PPC_F5  = 37,
0236   UNW_PPC_F6  = 38,
0237   UNW_PPC_F7  = 39,
0238   UNW_PPC_F8  = 40,
0239   UNW_PPC_F9  = 41,
0240   UNW_PPC_F10 = 42,
0241   UNW_PPC_F11 = 43,
0242   UNW_PPC_F12 = 44,
0243   UNW_PPC_F13 = 45,
0244   UNW_PPC_F14 = 46,
0245   UNW_PPC_F15 = 47,
0246   UNW_PPC_F16 = 48,
0247   UNW_PPC_F17 = 49,
0248   UNW_PPC_F18 = 50,
0249   UNW_PPC_F19 = 51,
0250   UNW_PPC_F20 = 52,
0251   UNW_PPC_F21 = 53,
0252   UNW_PPC_F22 = 54,
0253   UNW_PPC_F23 = 55,
0254   UNW_PPC_F24 = 56,
0255   UNW_PPC_F25 = 57,
0256   UNW_PPC_F26 = 58,
0257   UNW_PPC_F27 = 59,
0258   UNW_PPC_F28 = 60,
0259   UNW_PPC_F29 = 61,
0260   UNW_PPC_F30 = 62,
0261   UNW_PPC_F31 = 63,
0262   UNW_PPC_MQ  = 64,
0263   UNW_PPC_LR  = 65,
0264   UNW_PPC_CTR = 66,
0265   UNW_PPC_AP  = 67,
0266   UNW_PPC_CR0 = 68,
0267   UNW_PPC_CR1 = 69,
0268   UNW_PPC_CR2 = 70,
0269   UNW_PPC_CR3 = 71,
0270   UNW_PPC_CR4 = 72,
0271   UNW_PPC_CR5 = 73,
0272   UNW_PPC_CR6 = 74,
0273   UNW_PPC_CR7 = 75,
0274   UNW_PPC_XER = 76,
0275   UNW_PPC_V0  = 77,
0276   UNW_PPC_V1  = 78,
0277   UNW_PPC_V2  = 79,
0278   UNW_PPC_V3  = 80,
0279   UNW_PPC_V4  = 81,
0280   UNW_PPC_V5  = 82,
0281   UNW_PPC_V6  = 83,
0282   UNW_PPC_V7  = 84,
0283   UNW_PPC_V8  = 85,
0284   UNW_PPC_V9  = 86,
0285   UNW_PPC_V10 = 87,
0286   UNW_PPC_V11 = 88,
0287   UNW_PPC_V12 = 89,
0288   UNW_PPC_V13 = 90,
0289   UNW_PPC_V14 = 91,
0290   UNW_PPC_V15 = 92,
0291   UNW_PPC_V16 = 93,
0292   UNW_PPC_V17 = 94,
0293   UNW_PPC_V18 = 95,
0294   UNW_PPC_V19 = 96,
0295   UNW_PPC_V20 = 97,
0296   UNW_PPC_V21 = 98,
0297   UNW_PPC_V22 = 99,
0298   UNW_PPC_V23 = 100,
0299   UNW_PPC_V24 = 101,
0300   UNW_PPC_V25 = 102,
0301   UNW_PPC_V26 = 103,
0302   UNW_PPC_V27 = 104,
0303   UNW_PPC_V28 = 105,
0304   UNW_PPC_V29 = 106,
0305   UNW_PPC_V30 = 107,
0306   UNW_PPC_V31 = 108,
0307   UNW_PPC_VRSAVE  = 109,
0308   UNW_PPC_VSCR    = 110,
0309   UNW_PPC_SPE_ACC = 111,
0310   UNW_PPC_SPEFSCR = 112
0311 };
0312 
0313 // 64-bit ppc register numbers
0314 enum {
0315   UNW_PPC64_R0      = 0,
0316   UNW_PPC64_R1      = 1,
0317   UNW_PPC64_R2      = 2,
0318   UNW_PPC64_R3      = 3,
0319   UNW_PPC64_R4      = 4,
0320   UNW_PPC64_R5      = 5,
0321   UNW_PPC64_R6      = 6,
0322   UNW_PPC64_R7      = 7,
0323   UNW_PPC64_R8      = 8,
0324   UNW_PPC64_R9      = 9,
0325   UNW_PPC64_R10     = 10,
0326   UNW_PPC64_R11     = 11,
0327   UNW_PPC64_R12     = 12,
0328   UNW_PPC64_R13     = 13,
0329   UNW_PPC64_R14     = 14,
0330   UNW_PPC64_R15     = 15,
0331   UNW_PPC64_R16     = 16,
0332   UNW_PPC64_R17     = 17,
0333   UNW_PPC64_R18     = 18,
0334   UNW_PPC64_R19     = 19,
0335   UNW_PPC64_R20     = 20,
0336   UNW_PPC64_R21     = 21,
0337   UNW_PPC64_R22     = 22,
0338   UNW_PPC64_R23     = 23,
0339   UNW_PPC64_R24     = 24,
0340   UNW_PPC64_R25     = 25,
0341   UNW_PPC64_R26     = 26,
0342   UNW_PPC64_R27     = 27,
0343   UNW_PPC64_R28     = 28,
0344   UNW_PPC64_R29     = 29,
0345   UNW_PPC64_R30     = 30,
0346   UNW_PPC64_R31     = 31,
0347   UNW_PPC64_F0      = 32,
0348   UNW_PPC64_F1      = 33,
0349   UNW_PPC64_F2      = 34,
0350   UNW_PPC64_F3      = 35,
0351   UNW_PPC64_F4      = 36,
0352   UNW_PPC64_F5      = 37,
0353   UNW_PPC64_F6      = 38,
0354   UNW_PPC64_F7      = 39,
0355   UNW_PPC64_F8      = 40,
0356   UNW_PPC64_F9      = 41,
0357   UNW_PPC64_F10     = 42,
0358   UNW_PPC64_F11     = 43,
0359   UNW_PPC64_F12     = 44,
0360   UNW_PPC64_F13     = 45,
0361   UNW_PPC64_F14     = 46,
0362   UNW_PPC64_F15     = 47,
0363   UNW_PPC64_F16     = 48,
0364   UNW_PPC64_F17     = 49,
0365   UNW_PPC64_F18     = 50,
0366   UNW_PPC64_F19     = 51,
0367   UNW_PPC64_F20     = 52,
0368   UNW_PPC64_F21     = 53,
0369   UNW_PPC64_F22     = 54,
0370   UNW_PPC64_F23     = 55,
0371   UNW_PPC64_F24     = 56,
0372   UNW_PPC64_F25     = 57,
0373   UNW_PPC64_F26     = 58,
0374   UNW_PPC64_F27     = 59,
0375   UNW_PPC64_F28     = 60,
0376   UNW_PPC64_F29     = 61,
0377   UNW_PPC64_F30     = 62,
0378   UNW_PPC64_F31     = 63,
0379   // 64: reserved
0380   UNW_PPC64_LR      = 65,
0381   UNW_PPC64_CTR     = 66,
0382   // 67: reserved
0383   UNW_PPC64_CR0     = 68,
0384   UNW_PPC64_CR1     = 69,
0385   UNW_PPC64_CR2     = 70,
0386   UNW_PPC64_CR3     = 71,
0387   UNW_PPC64_CR4     = 72,
0388   UNW_PPC64_CR5     = 73,
0389   UNW_PPC64_CR6     = 74,
0390   UNW_PPC64_CR7     = 75,
0391   UNW_PPC64_XER     = 76,
0392   UNW_PPC64_V0      = 77,
0393   UNW_PPC64_V1      = 78,
0394   UNW_PPC64_V2      = 79,
0395   UNW_PPC64_V3      = 80,
0396   UNW_PPC64_V4      = 81,
0397   UNW_PPC64_V5      = 82,
0398   UNW_PPC64_V6      = 83,
0399   UNW_PPC64_V7      = 84,
0400   UNW_PPC64_V8      = 85,
0401   UNW_PPC64_V9      = 86,
0402   UNW_PPC64_V10     = 87,
0403   UNW_PPC64_V11     = 88,
0404   UNW_PPC64_V12     = 89,
0405   UNW_PPC64_V13     = 90,
0406   UNW_PPC64_V14     = 91,
0407   UNW_PPC64_V15     = 92,
0408   UNW_PPC64_V16     = 93,
0409   UNW_PPC64_V17     = 94,
0410   UNW_PPC64_V18     = 95,
0411   UNW_PPC64_V19     = 96,
0412   UNW_PPC64_V20     = 97,
0413   UNW_PPC64_V21     = 98,
0414   UNW_PPC64_V22     = 99,
0415   UNW_PPC64_V23     = 100,
0416   UNW_PPC64_V24     = 101,
0417   UNW_PPC64_V25     = 102,
0418   UNW_PPC64_V26     = 103,
0419   UNW_PPC64_V27     = 104,
0420   UNW_PPC64_V28     = 105,
0421   UNW_PPC64_V29     = 106,
0422   UNW_PPC64_V30     = 107,
0423   UNW_PPC64_V31     = 108,
0424   // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
0425   // Borrowing VRSAVE number from PPC32.
0426   UNW_PPC64_VRSAVE  = 109,
0427   UNW_PPC64_VSCR    = 110,
0428   UNW_PPC64_TFHAR   = 114,
0429   UNW_PPC64_TFIAR   = 115,
0430   UNW_PPC64_TEXASR  = 116,
0431   UNW_PPC64_VS0     = UNW_PPC64_F0,
0432   UNW_PPC64_VS1     = UNW_PPC64_F1,
0433   UNW_PPC64_VS2     = UNW_PPC64_F2,
0434   UNW_PPC64_VS3     = UNW_PPC64_F3,
0435   UNW_PPC64_VS4     = UNW_PPC64_F4,
0436   UNW_PPC64_VS5     = UNW_PPC64_F5,
0437   UNW_PPC64_VS6     = UNW_PPC64_F6,
0438   UNW_PPC64_VS7     = UNW_PPC64_F7,
0439   UNW_PPC64_VS8     = UNW_PPC64_F8,
0440   UNW_PPC64_VS9     = UNW_PPC64_F9,
0441   UNW_PPC64_VS10    = UNW_PPC64_F10,
0442   UNW_PPC64_VS11    = UNW_PPC64_F11,
0443   UNW_PPC64_VS12    = UNW_PPC64_F12,
0444   UNW_PPC64_VS13    = UNW_PPC64_F13,
0445   UNW_PPC64_VS14    = UNW_PPC64_F14,
0446   UNW_PPC64_VS15    = UNW_PPC64_F15,
0447   UNW_PPC64_VS16    = UNW_PPC64_F16,
0448   UNW_PPC64_VS17    = UNW_PPC64_F17,
0449   UNW_PPC64_VS18    = UNW_PPC64_F18,
0450   UNW_PPC64_VS19    = UNW_PPC64_F19,
0451   UNW_PPC64_VS20    = UNW_PPC64_F20,
0452   UNW_PPC64_VS21    = UNW_PPC64_F21,
0453   UNW_PPC64_VS22    = UNW_PPC64_F22,
0454   UNW_PPC64_VS23    = UNW_PPC64_F23,
0455   UNW_PPC64_VS24    = UNW_PPC64_F24,
0456   UNW_PPC64_VS25    = UNW_PPC64_F25,
0457   UNW_PPC64_VS26    = UNW_PPC64_F26,
0458   UNW_PPC64_VS27    = UNW_PPC64_F27,
0459   UNW_PPC64_VS28    = UNW_PPC64_F28,
0460   UNW_PPC64_VS29    = UNW_PPC64_F29,
0461   UNW_PPC64_VS30    = UNW_PPC64_F30,
0462   UNW_PPC64_VS31    = UNW_PPC64_F31,
0463   UNW_PPC64_VS32    = UNW_PPC64_V0,
0464   UNW_PPC64_VS33    = UNW_PPC64_V1,
0465   UNW_PPC64_VS34    = UNW_PPC64_V2,
0466   UNW_PPC64_VS35    = UNW_PPC64_V3,
0467   UNW_PPC64_VS36    = UNW_PPC64_V4,
0468   UNW_PPC64_VS37    = UNW_PPC64_V5,
0469   UNW_PPC64_VS38    = UNW_PPC64_V6,
0470   UNW_PPC64_VS39    = UNW_PPC64_V7,
0471   UNW_PPC64_VS40    = UNW_PPC64_V8,
0472   UNW_PPC64_VS41    = UNW_PPC64_V9,
0473   UNW_PPC64_VS42    = UNW_PPC64_V10,
0474   UNW_PPC64_VS43    = UNW_PPC64_V11,
0475   UNW_PPC64_VS44    = UNW_PPC64_V12,
0476   UNW_PPC64_VS45    = UNW_PPC64_V13,
0477   UNW_PPC64_VS46    = UNW_PPC64_V14,
0478   UNW_PPC64_VS47    = UNW_PPC64_V15,
0479   UNW_PPC64_VS48    = UNW_PPC64_V16,
0480   UNW_PPC64_VS49    = UNW_PPC64_V17,
0481   UNW_PPC64_VS50    = UNW_PPC64_V18,
0482   UNW_PPC64_VS51    = UNW_PPC64_V19,
0483   UNW_PPC64_VS52    = UNW_PPC64_V20,
0484   UNW_PPC64_VS53    = UNW_PPC64_V21,
0485   UNW_PPC64_VS54    = UNW_PPC64_V22,
0486   UNW_PPC64_VS55    = UNW_PPC64_V23,
0487   UNW_PPC64_VS56    = UNW_PPC64_V24,
0488   UNW_PPC64_VS57    = UNW_PPC64_V25,
0489   UNW_PPC64_VS58    = UNW_PPC64_V26,
0490   UNW_PPC64_VS59    = UNW_PPC64_V27,
0491   UNW_PPC64_VS60    = UNW_PPC64_V28,
0492   UNW_PPC64_VS61    = UNW_PPC64_V29,
0493   UNW_PPC64_VS62    = UNW_PPC64_V30,
0494   UNW_PPC64_VS63    = UNW_PPC64_V31
0495 };
0496 
0497 // 64-bit ARM64 registers
0498 enum {
0499   UNW_AARCH64_X0 = 0,
0500   UNW_AARCH64_X1 = 1,
0501   UNW_AARCH64_X2 = 2,
0502   UNW_AARCH64_X3 = 3,
0503   UNW_AARCH64_X4 = 4,
0504   UNW_AARCH64_X5 = 5,
0505   UNW_AARCH64_X6 = 6,
0506   UNW_AARCH64_X7 = 7,
0507   UNW_AARCH64_X8 = 8,
0508   UNW_AARCH64_X9 = 9,
0509   UNW_AARCH64_X10 = 10,
0510   UNW_AARCH64_X11 = 11,
0511   UNW_AARCH64_X12 = 12,
0512   UNW_AARCH64_X13 = 13,
0513   UNW_AARCH64_X14 = 14,
0514   UNW_AARCH64_X15 = 15,
0515   UNW_AARCH64_X16 = 16,
0516   UNW_AARCH64_X17 = 17,
0517   UNW_AARCH64_X18 = 18,
0518   UNW_AARCH64_X19 = 19,
0519   UNW_AARCH64_X20 = 20,
0520   UNW_AARCH64_X21 = 21,
0521   UNW_AARCH64_X22 = 22,
0522   UNW_AARCH64_X23 = 23,
0523   UNW_AARCH64_X24 = 24,
0524   UNW_AARCH64_X25 = 25,
0525   UNW_AARCH64_X26 = 26,
0526   UNW_AARCH64_X27 = 27,
0527   UNW_AARCH64_X28 = 28,
0528   UNW_AARCH64_X29 = 29,
0529   UNW_AARCH64_FP = 29,
0530   UNW_AARCH64_X30 = 30,
0531   UNW_AARCH64_LR = 30,
0532   UNW_AARCH64_X31 = 31,
0533   UNW_AARCH64_SP = 31,
0534   UNW_AARCH64_PC = 32,
0535 
0536   // reserved block
0537   UNW_AARCH64_RA_SIGN_STATE = 34,
0538 
0539   // FP/vector registers
0540   UNW_AARCH64_V0 = 64,
0541   UNW_AARCH64_V1 = 65,
0542   UNW_AARCH64_V2 = 66,
0543   UNW_AARCH64_V3 = 67,
0544   UNW_AARCH64_V4 = 68,
0545   UNW_AARCH64_V5 = 69,
0546   UNW_AARCH64_V6 = 70,
0547   UNW_AARCH64_V7 = 71,
0548   UNW_AARCH64_V8 = 72,
0549   UNW_AARCH64_V9 = 73,
0550   UNW_AARCH64_V10 = 74,
0551   UNW_AARCH64_V11 = 75,
0552   UNW_AARCH64_V12 = 76,
0553   UNW_AARCH64_V13 = 77,
0554   UNW_AARCH64_V14 = 78,
0555   UNW_AARCH64_V15 = 79,
0556   UNW_AARCH64_V16 = 80,
0557   UNW_AARCH64_V17 = 81,
0558   UNW_AARCH64_V18 = 82,
0559   UNW_AARCH64_V19 = 83,
0560   UNW_AARCH64_V20 = 84,
0561   UNW_AARCH64_V21 = 85,
0562   UNW_AARCH64_V22 = 86,
0563   UNW_AARCH64_V23 = 87,
0564   UNW_AARCH64_V24 = 88,
0565   UNW_AARCH64_V25 = 89,
0566   UNW_AARCH64_V26 = 90,
0567   UNW_AARCH64_V27 = 91,
0568   UNW_AARCH64_V28 = 92,
0569   UNW_AARCH64_V29 = 93,
0570   UNW_AARCH64_V30 = 94,
0571   UNW_AARCH64_V31 = 95,
0572 
0573   // Compatibility aliases
0574   UNW_ARM64_X0 = UNW_AARCH64_X0,
0575   UNW_ARM64_X1 = UNW_AARCH64_X1,
0576   UNW_ARM64_X2 = UNW_AARCH64_X2,
0577   UNW_ARM64_X3 = UNW_AARCH64_X3,
0578   UNW_ARM64_X4 = UNW_AARCH64_X4,
0579   UNW_ARM64_X5 = UNW_AARCH64_X5,
0580   UNW_ARM64_X6 = UNW_AARCH64_X6,
0581   UNW_ARM64_X7 = UNW_AARCH64_X7,
0582   UNW_ARM64_X8 = UNW_AARCH64_X8,
0583   UNW_ARM64_X9 = UNW_AARCH64_X9,
0584   UNW_ARM64_X10 = UNW_AARCH64_X10,
0585   UNW_ARM64_X11 = UNW_AARCH64_X11,
0586   UNW_ARM64_X12 = UNW_AARCH64_X12,
0587   UNW_ARM64_X13 = UNW_AARCH64_X13,
0588   UNW_ARM64_X14 = UNW_AARCH64_X14,
0589   UNW_ARM64_X15 = UNW_AARCH64_X15,
0590   UNW_ARM64_X16 = UNW_AARCH64_X16,
0591   UNW_ARM64_X17 = UNW_AARCH64_X17,
0592   UNW_ARM64_X18 = UNW_AARCH64_X18,
0593   UNW_ARM64_X19 = UNW_AARCH64_X19,
0594   UNW_ARM64_X20 = UNW_AARCH64_X20,
0595   UNW_ARM64_X21 = UNW_AARCH64_X21,
0596   UNW_ARM64_X22 = UNW_AARCH64_X22,
0597   UNW_ARM64_X23 = UNW_AARCH64_X23,
0598   UNW_ARM64_X24 = UNW_AARCH64_X24,
0599   UNW_ARM64_X25 = UNW_AARCH64_X25,
0600   UNW_ARM64_X26 = UNW_AARCH64_X26,
0601   UNW_ARM64_X27 = UNW_AARCH64_X27,
0602   UNW_ARM64_X28 = UNW_AARCH64_X28,
0603   UNW_ARM64_X29 = UNW_AARCH64_X29,
0604   UNW_ARM64_FP = UNW_AARCH64_FP,
0605   UNW_ARM64_X30 = UNW_AARCH64_X30,
0606   UNW_ARM64_LR = UNW_AARCH64_LR,
0607   UNW_ARM64_X31 = UNW_AARCH64_X31,
0608   UNW_ARM64_SP = UNW_AARCH64_SP,
0609   UNW_ARM64_PC = UNW_AARCH64_PC,
0610   UNW_ARM64_RA_SIGN_STATE = UNW_AARCH64_RA_SIGN_STATE,
0611   UNW_ARM64_D0 = UNW_AARCH64_V0,
0612   UNW_ARM64_D1 = UNW_AARCH64_V1,
0613   UNW_ARM64_D2 = UNW_AARCH64_V2,
0614   UNW_ARM64_D3 = UNW_AARCH64_V3,
0615   UNW_ARM64_D4 = UNW_AARCH64_V4,
0616   UNW_ARM64_D5 = UNW_AARCH64_V5,
0617   UNW_ARM64_D6 = UNW_AARCH64_V6,
0618   UNW_ARM64_D7 = UNW_AARCH64_V7,
0619   UNW_ARM64_D8 = UNW_AARCH64_V8,
0620   UNW_ARM64_D9 = UNW_AARCH64_V9,
0621   UNW_ARM64_D10 = UNW_AARCH64_V10,
0622   UNW_ARM64_D11 = UNW_AARCH64_V11,
0623   UNW_ARM64_D12 = UNW_AARCH64_V12,
0624   UNW_ARM64_D13 = UNW_AARCH64_V13,
0625   UNW_ARM64_D14 = UNW_AARCH64_V14,
0626   UNW_ARM64_D15 = UNW_AARCH64_V15,
0627   UNW_ARM64_D16 = UNW_AARCH64_V16,
0628   UNW_ARM64_D17 = UNW_AARCH64_V17,
0629   UNW_ARM64_D18 = UNW_AARCH64_V18,
0630   UNW_ARM64_D19 = UNW_AARCH64_V19,
0631   UNW_ARM64_D20 = UNW_AARCH64_V20,
0632   UNW_ARM64_D21 = UNW_AARCH64_V21,
0633   UNW_ARM64_D22 = UNW_AARCH64_V22,
0634   UNW_ARM64_D23 = UNW_AARCH64_V23,
0635   UNW_ARM64_D24 = UNW_AARCH64_V24,
0636   UNW_ARM64_D25 = UNW_AARCH64_V25,
0637   UNW_ARM64_D26 = UNW_AARCH64_V26,
0638   UNW_ARM64_D27 = UNW_AARCH64_V27,
0639   UNW_ARM64_D28 = UNW_AARCH64_V28,
0640   UNW_ARM64_D29 = UNW_AARCH64_V29,
0641   UNW_ARM64_D30 = UNW_AARCH64_V30,
0642   UNW_ARM64_D31 = UNW_AARCH64_V31,
0643 };
0644 
0645 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
0646 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
0647 // In this scheme, even though the 64-bit floating point registers D0-D31
0648 // overlap physically with the 32-bit floating pointer registers S0-S31,
0649 // they are given a non-overlapping range of register numbers.
0650 //
0651 // Commented out ranges are not preserved during unwinding.
0652 enum {
0653   UNW_ARM_R0  = 0,
0654   UNW_ARM_R1  = 1,
0655   UNW_ARM_R2  = 2,
0656   UNW_ARM_R3  = 3,
0657   UNW_ARM_R4  = 4,
0658   UNW_ARM_R5  = 5,
0659   UNW_ARM_R6  = 6,
0660   UNW_ARM_R7  = 7,
0661   UNW_ARM_R8  = 8,
0662   UNW_ARM_R9  = 9,
0663   UNW_ARM_R10 = 10,
0664   UNW_ARM_R11 = 11,
0665   UNW_ARM_R12 = 12,
0666   UNW_ARM_SP  = 13,  // Logical alias for UNW_REG_SP
0667   UNW_ARM_R13 = 13,
0668   UNW_ARM_LR  = 14,
0669   UNW_ARM_R14 = 14,
0670   UNW_ARM_IP  = 15,  // Logical alias for UNW_REG_IP
0671   UNW_ARM_R15 = 15,
0672   // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
0673   UNW_ARM_S0  = 64,
0674   UNW_ARM_S1  = 65,
0675   UNW_ARM_S2  = 66,
0676   UNW_ARM_S3  = 67,
0677   UNW_ARM_S4  = 68,
0678   UNW_ARM_S5  = 69,
0679   UNW_ARM_S6  = 70,
0680   UNW_ARM_S7  = 71,
0681   UNW_ARM_S8  = 72,
0682   UNW_ARM_S9  = 73,
0683   UNW_ARM_S10 = 74,
0684   UNW_ARM_S11 = 75,
0685   UNW_ARM_S12 = 76,
0686   UNW_ARM_S13 = 77,
0687   UNW_ARM_S14 = 78,
0688   UNW_ARM_S15 = 79,
0689   UNW_ARM_S16 = 80,
0690   UNW_ARM_S17 = 81,
0691   UNW_ARM_S18 = 82,
0692   UNW_ARM_S19 = 83,
0693   UNW_ARM_S20 = 84,
0694   UNW_ARM_S21 = 85,
0695   UNW_ARM_S22 = 86,
0696   UNW_ARM_S23 = 87,
0697   UNW_ARM_S24 = 88,
0698   UNW_ARM_S25 = 89,
0699   UNW_ARM_S26 = 90,
0700   UNW_ARM_S27 = 91,
0701   UNW_ARM_S28 = 92,
0702   UNW_ARM_S29 = 93,
0703   UNW_ARM_S30 = 94,
0704   UNW_ARM_S31 = 95,
0705   //  96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
0706   // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
0707   UNW_ARM_WR0 = 112,
0708   UNW_ARM_WR1 = 113,
0709   UNW_ARM_WR2 = 114,
0710   UNW_ARM_WR3 = 115,
0711   UNW_ARM_WR4 = 116,
0712   UNW_ARM_WR5 = 117,
0713   UNW_ARM_WR6 = 118,
0714   UNW_ARM_WR7 = 119,
0715   UNW_ARM_WR8 = 120,
0716   UNW_ARM_WR9 = 121,
0717   UNW_ARM_WR10 = 122,
0718   UNW_ARM_WR11 = 123,
0719   UNW_ARM_WR12 = 124,
0720   UNW_ARM_WR13 = 125,
0721   UNW_ARM_WR14 = 126,
0722   UNW_ARM_WR15 = 127,
0723   // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
0724   // 134-142 -- Reserved
0725   UNW_ARM_RA_AUTH_CODE = 143,
0726   // 144-150 -- R8_USR-R14_USR
0727   // 151-157 -- R8_FIQ-R14_FIQ
0728   // 158-159 -- R13_IRQ-R14_IRQ
0729   // 160-161 -- R13_ABT-R14_ABT
0730   // 162-163 -- R13_UND-R14_UND
0731   // 164-165 -- R13_SVC-R14_SVC
0732   // 166-191 -- Reserved
0733   UNW_ARM_WC0 = 192,
0734   UNW_ARM_WC1 = 193,
0735   UNW_ARM_WC2 = 194,
0736   UNW_ARM_WC3 = 195,
0737   // 196-199 -- wC4-wC7 (Intel wireless MMX control)
0738   // 200-255 -- Reserved
0739   UNW_ARM_D0  = 256,
0740   UNW_ARM_D1  = 257,
0741   UNW_ARM_D2  = 258,
0742   UNW_ARM_D3  = 259,
0743   UNW_ARM_D4  = 260,
0744   UNW_ARM_D5  = 261,
0745   UNW_ARM_D6  = 262,
0746   UNW_ARM_D7  = 263,
0747   UNW_ARM_D8  = 264,
0748   UNW_ARM_D9  = 265,
0749   UNW_ARM_D10 = 266,
0750   UNW_ARM_D11 = 267,
0751   UNW_ARM_D12 = 268,
0752   UNW_ARM_D13 = 269,
0753   UNW_ARM_D14 = 270,
0754   UNW_ARM_D15 = 271,
0755   UNW_ARM_D16 = 272,
0756   UNW_ARM_D17 = 273,
0757   UNW_ARM_D18 = 274,
0758   UNW_ARM_D19 = 275,
0759   UNW_ARM_D20 = 276,
0760   UNW_ARM_D21 = 277,
0761   UNW_ARM_D22 = 278,
0762   UNW_ARM_D23 = 279,
0763   UNW_ARM_D24 = 280,
0764   UNW_ARM_D25 = 281,
0765   UNW_ARM_D26 = 282,
0766   UNW_ARM_D27 = 283,
0767   UNW_ARM_D28 = 284,
0768   UNW_ARM_D29 = 285,
0769   UNW_ARM_D30 = 286,
0770   UNW_ARM_D31 = 287,
0771   // 288-319 -- Reserved for VFP/Neon
0772   // 320-8191 -- Reserved
0773   // 8192-16383 -- Unspecified vendor co-processor register.
0774 };
0775 
0776 // OpenRISC1000 register numbers
0777 enum {
0778   UNW_OR1K_R0  = 0,
0779   UNW_OR1K_R1  = 1,
0780   UNW_OR1K_R2  = 2,
0781   UNW_OR1K_R3  = 3,
0782   UNW_OR1K_R4  = 4,
0783   UNW_OR1K_R5  = 5,
0784   UNW_OR1K_R6  = 6,
0785   UNW_OR1K_R7  = 7,
0786   UNW_OR1K_R8  = 8,
0787   UNW_OR1K_R9  = 9,
0788   UNW_OR1K_R10 = 10,
0789   UNW_OR1K_R11 = 11,
0790   UNW_OR1K_R12 = 12,
0791   UNW_OR1K_R13 = 13,
0792   UNW_OR1K_R14 = 14,
0793   UNW_OR1K_R15 = 15,
0794   UNW_OR1K_R16 = 16,
0795   UNW_OR1K_R17 = 17,
0796   UNW_OR1K_R18 = 18,
0797   UNW_OR1K_R19 = 19,
0798   UNW_OR1K_R20 = 20,
0799   UNW_OR1K_R21 = 21,
0800   UNW_OR1K_R22 = 22,
0801   UNW_OR1K_R23 = 23,
0802   UNW_OR1K_R24 = 24,
0803   UNW_OR1K_R25 = 25,
0804   UNW_OR1K_R26 = 26,
0805   UNW_OR1K_R27 = 27,
0806   UNW_OR1K_R28 = 28,
0807   UNW_OR1K_R29 = 29,
0808   UNW_OR1K_R30 = 30,
0809   UNW_OR1K_R31 = 31,
0810   UNW_OR1K_EPCR = 32,
0811 };
0812 
0813 // MIPS registers
0814 enum {
0815   UNW_MIPS_R0  = 0,
0816   UNW_MIPS_R1  = 1,
0817   UNW_MIPS_R2  = 2,
0818   UNW_MIPS_R3  = 3,
0819   UNW_MIPS_R4  = 4,
0820   UNW_MIPS_R5  = 5,
0821   UNW_MIPS_R6  = 6,
0822   UNW_MIPS_R7  = 7,
0823   UNW_MIPS_R8  = 8,
0824   UNW_MIPS_R9  = 9,
0825   UNW_MIPS_R10 = 10,
0826   UNW_MIPS_R11 = 11,
0827   UNW_MIPS_R12 = 12,
0828   UNW_MIPS_R13 = 13,
0829   UNW_MIPS_R14 = 14,
0830   UNW_MIPS_R15 = 15,
0831   UNW_MIPS_R16 = 16,
0832   UNW_MIPS_R17 = 17,
0833   UNW_MIPS_R18 = 18,
0834   UNW_MIPS_R19 = 19,
0835   UNW_MIPS_R20 = 20,
0836   UNW_MIPS_R21 = 21,
0837   UNW_MIPS_R22 = 22,
0838   UNW_MIPS_R23 = 23,
0839   UNW_MIPS_R24 = 24,
0840   UNW_MIPS_R25 = 25,
0841   UNW_MIPS_R26 = 26,
0842   UNW_MIPS_R27 = 27,
0843   UNW_MIPS_R28 = 28,
0844   UNW_MIPS_R29 = 29,
0845   UNW_MIPS_R30 = 30,
0846   UNW_MIPS_R31 = 31,
0847   UNW_MIPS_F0  = 32,
0848   UNW_MIPS_F1  = 33,
0849   UNW_MIPS_F2  = 34,
0850   UNW_MIPS_F3  = 35,
0851   UNW_MIPS_F4  = 36,
0852   UNW_MIPS_F5  = 37,
0853   UNW_MIPS_F6  = 38,
0854   UNW_MIPS_F7  = 39,
0855   UNW_MIPS_F8  = 40,
0856   UNW_MIPS_F9  = 41,
0857   UNW_MIPS_F10 = 42,
0858   UNW_MIPS_F11 = 43,
0859   UNW_MIPS_F12 = 44,
0860   UNW_MIPS_F13 = 45,
0861   UNW_MIPS_F14 = 46,
0862   UNW_MIPS_F15 = 47,
0863   UNW_MIPS_F16 = 48,
0864   UNW_MIPS_F17 = 49,
0865   UNW_MIPS_F18 = 50,
0866   UNW_MIPS_F19 = 51,
0867   UNW_MIPS_F20 = 52,
0868   UNW_MIPS_F21 = 53,
0869   UNW_MIPS_F22 = 54,
0870   UNW_MIPS_F23 = 55,
0871   UNW_MIPS_F24 = 56,
0872   UNW_MIPS_F25 = 57,
0873   UNW_MIPS_F26 = 58,
0874   UNW_MIPS_F27 = 59,
0875   UNW_MIPS_F28 = 60,
0876   UNW_MIPS_F29 = 61,
0877   UNW_MIPS_F30 = 62,
0878   UNW_MIPS_F31 = 63,
0879   // HI,LO have been dropped since r6, we keep them here.
0880   // So, when we add DSP/MSA etc, we can use the same register indexes
0881   // for r6 and pre-r6.
0882   UNW_MIPS_HI = 64,
0883   UNW_MIPS_LO = 65,
0884 };
0885 
0886 // SPARC registers
0887 enum {
0888   UNW_SPARC_G0 = 0,
0889   UNW_SPARC_G1 = 1,
0890   UNW_SPARC_G2 = 2,
0891   UNW_SPARC_G3 = 3,
0892   UNW_SPARC_G4 = 4,
0893   UNW_SPARC_G5 = 5,
0894   UNW_SPARC_G6 = 6,
0895   UNW_SPARC_G7 = 7,
0896   UNW_SPARC_O0 = 8,
0897   UNW_SPARC_O1 = 9,
0898   UNW_SPARC_O2 = 10,
0899   UNW_SPARC_O3 = 11,
0900   UNW_SPARC_O4 = 12,
0901   UNW_SPARC_O5 = 13,
0902   UNW_SPARC_O6 = 14,
0903   UNW_SPARC_O7 = 15,
0904   UNW_SPARC_L0 = 16,
0905   UNW_SPARC_L1 = 17,
0906   UNW_SPARC_L2 = 18,
0907   UNW_SPARC_L3 = 19,
0908   UNW_SPARC_L4 = 20,
0909   UNW_SPARC_L5 = 21,
0910   UNW_SPARC_L6 = 22,
0911   UNW_SPARC_L7 = 23,
0912   UNW_SPARC_I0 = 24,
0913   UNW_SPARC_I1 = 25,
0914   UNW_SPARC_I2 = 26,
0915   UNW_SPARC_I3 = 27,
0916   UNW_SPARC_I4 = 28,
0917   UNW_SPARC_I5 = 29,
0918   UNW_SPARC_I6 = 30,
0919   UNW_SPARC_I7 = 31,
0920 };
0921 
0922 // Hexagon register numbers
0923 enum {
0924   UNW_HEXAGON_R0,
0925   UNW_HEXAGON_R1,
0926   UNW_HEXAGON_R2,
0927   UNW_HEXAGON_R3,
0928   UNW_HEXAGON_R4,
0929   UNW_HEXAGON_R5,
0930   UNW_HEXAGON_R6,
0931   UNW_HEXAGON_R7,
0932   UNW_HEXAGON_R8,
0933   UNW_HEXAGON_R9,
0934   UNW_HEXAGON_R10,
0935   UNW_HEXAGON_R11,
0936   UNW_HEXAGON_R12,
0937   UNW_HEXAGON_R13,
0938   UNW_HEXAGON_R14,
0939   UNW_HEXAGON_R15,
0940   UNW_HEXAGON_R16,
0941   UNW_HEXAGON_R17,
0942   UNW_HEXAGON_R18,
0943   UNW_HEXAGON_R19,
0944   UNW_HEXAGON_R20,
0945   UNW_HEXAGON_R21,
0946   UNW_HEXAGON_R22,
0947   UNW_HEXAGON_R23,
0948   UNW_HEXAGON_R24,
0949   UNW_HEXAGON_R25,
0950   UNW_HEXAGON_R26,
0951   UNW_HEXAGON_R27,
0952   UNW_HEXAGON_R28,
0953   UNW_HEXAGON_R29,
0954   UNW_HEXAGON_R30,
0955   UNW_HEXAGON_R31,
0956   UNW_HEXAGON_P3_0,
0957   UNW_HEXAGON_PC,
0958 };
0959 
0960 // RISC-V registers. These match the DWARF register numbers defined by section
0961 // 4 of the RISC-V ELF psABI specification, which can be found at:
0962 //
0963 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
0964 enum {
0965   UNW_RISCV_X0  = 0,
0966   UNW_RISCV_X1  = 1,
0967   UNW_RISCV_X2  = 2,
0968   UNW_RISCV_X3  = 3,
0969   UNW_RISCV_X4  = 4,
0970   UNW_RISCV_X5  = 5,
0971   UNW_RISCV_X6  = 6,
0972   UNW_RISCV_X7  = 7,
0973   UNW_RISCV_X8  = 8,
0974   UNW_RISCV_X9  = 9,
0975   UNW_RISCV_X10 = 10,
0976   UNW_RISCV_X11 = 11,
0977   UNW_RISCV_X12 = 12,
0978   UNW_RISCV_X13 = 13,
0979   UNW_RISCV_X14 = 14,
0980   UNW_RISCV_X15 = 15,
0981   UNW_RISCV_X16 = 16,
0982   UNW_RISCV_X17 = 17,
0983   UNW_RISCV_X18 = 18,
0984   UNW_RISCV_X19 = 19,
0985   UNW_RISCV_X20 = 20,
0986   UNW_RISCV_X21 = 21,
0987   UNW_RISCV_X22 = 22,
0988   UNW_RISCV_X23 = 23,
0989   UNW_RISCV_X24 = 24,
0990   UNW_RISCV_X25 = 25,
0991   UNW_RISCV_X26 = 26,
0992   UNW_RISCV_X27 = 27,
0993   UNW_RISCV_X28 = 28,
0994   UNW_RISCV_X29 = 29,
0995   UNW_RISCV_X30 = 30,
0996   UNW_RISCV_X31 = 31,
0997   UNW_RISCV_F0  = 32,
0998   UNW_RISCV_F1  = 33,
0999   UNW_RISCV_F2  = 34,
1000   UNW_RISCV_F3  = 35,
1001   UNW_RISCV_F4  = 36,
1002   UNW_RISCV_F5  = 37,
1003   UNW_RISCV_F6  = 38,
1004   UNW_RISCV_F7  = 39,
1005   UNW_RISCV_F8  = 40,
1006   UNW_RISCV_F9  = 41,
1007   UNW_RISCV_F10 = 42,
1008   UNW_RISCV_F11 = 43,
1009   UNW_RISCV_F12 = 44,
1010   UNW_RISCV_F13 = 45,
1011   UNW_RISCV_F14 = 46,
1012   UNW_RISCV_F15 = 47,
1013   UNW_RISCV_F16 = 48,
1014   UNW_RISCV_F17 = 49,
1015   UNW_RISCV_F18 = 50,
1016   UNW_RISCV_F19 = 51,
1017   UNW_RISCV_F20 = 52,
1018   UNW_RISCV_F21 = 53,
1019   UNW_RISCV_F22 = 54,
1020   UNW_RISCV_F23 = 55,
1021   UNW_RISCV_F24 = 56,
1022   UNW_RISCV_F25 = 57,
1023   UNW_RISCV_F26 = 58,
1024   UNW_RISCV_F27 = 59,
1025   UNW_RISCV_F28 = 60,
1026   UNW_RISCV_F29 = 61,
1027   UNW_RISCV_F30 = 62,
1028   UNW_RISCV_F31 = 63,
1029   // 65-95 -- Reserved for future standard extensions
1030   // 96-127 -- v0-v31 (Vector registers)
1031   // 128-3071 -- Reserved for future standard extensions
1032   // 3072-4095 -- Reserved for custom extensions
1033   // 4096-8191 -- CSRs
1034   //
1035   // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec:
1036   // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model
1037   // VLENB DWARF number: 0x1000 + 0xC22
1038   UNW_RISCV_VLENB = 0x1C22,
1039 };
1040 
1041 // VE register numbers
1042 enum {
1043   UNW_VE_S0   = 0,
1044   UNW_VE_S1   = 1,
1045   UNW_VE_S2   = 2,
1046   UNW_VE_S3   = 3,
1047   UNW_VE_S4   = 4,
1048   UNW_VE_S5   = 5,
1049   UNW_VE_S6   = 6,
1050   UNW_VE_S7   = 7,
1051   UNW_VE_S8   = 8,
1052   UNW_VE_S9   = 9,
1053   UNW_VE_S10  = 10,
1054   UNW_VE_S11  = 11,
1055   UNW_VE_S12  = 12,
1056   UNW_VE_S13  = 13,
1057   UNW_VE_S14  = 14,
1058   UNW_VE_S15  = 15,
1059   UNW_VE_S16  = 16,
1060   UNW_VE_S17  = 17,
1061   UNW_VE_S18  = 18,
1062   UNW_VE_S19  = 19,
1063   UNW_VE_S20  = 20,
1064   UNW_VE_S21  = 21,
1065   UNW_VE_S22  = 22,
1066   UNW_VE_S23  = 23,
1067   UNW_VE_S24  = 24,
1068   UNW_VE_S25  = 25,
1069   UNW_VE_S26  = 26,
1070   UNW_VE_S27  = 27,
1071   UNW_VE_S28  = 28,
1072   UNW_VE_S29  = 29,
1073   UNW_VE_S30  = 30,
1074   UNW_VE_S31  = 31,
1075   UNW_VE_S32  = 32,
1076   UNW_VE_S33  = 33,
1077   UNW_VE_S34  = 34,
1078   UNW_VE_S35  = 35,
1079   UNW_VE_S36  = 36,
1080   UNW_VE_S37  = 37,
1081   UNW_VE_S38  = 38,
1082   UNW_VE_S39  = 39,
1083   UNW_VE_S40  = 40,
1084   UNW_VE_S41  = 41,
1085   UNW_VE_S42  = 42,
1086   UNW_VE_S43  = 43,
1087   UNW_VE_S44  = 44,
1088   UNW_VE_S45  = 45,
1089   UNW_VE_S46  = 46,
1090   UNW_VE_S47  = 47,
1091   UNW_VE_S48  = 48,
1092   UNW_VE_S49  = 49,
1093   UNW_VE_S50  = 50,
1094   UNW_VE_S51  = 51,
1095   UNW_VE_S52  = 52,
1096   UNW_VE_S53  = 53,
1097   UNW_VE_S54  = 54,
1098   UNW_VE_S55  = 55,
1099   UNW_VE_S56  = 56,
1100   UNW_VE_S57  = 57,
1101   UNW_VE_S58  = 58,
1102   UNW_VE_S59  = 59,
1103   UNW_VE_S60  = 60,
1104   UNW_VE_S61  = 61,
1105   UNW_VE_S62  = 62,
1106   UNW_VE_S63  = 63,
1107   UNW_VE_V0   = 64 + 0,
1108   UNW_VE_V1   = 64 + 1,
1109   UNW_VE_V2   = 64 + 2,
1110   UNW_VE_V3   = 64 + 3,
1111   UNW_VE_V4   = 64 + 4,
1112   UNW_VE_V5   = 64 + 5,
1113   UNW_VE_V6   = 64 + 6,
1114   UNW_VE_V7   = 64 + 7,
1115   UNW_VE_V8   = 64 + 8,
1116   UNW_VE_V9   = 64 + 9,
1117   UNW_VE_V10  = 64 + 10,
1118   UNW_VE_V11  = 64 + 11,
1119   UNW_VE_V12  = 64 + 12,
1120   UNW_VE_V13  = 64 + 13,
1121   UNW_VE_V14  = 64 + 14,
1122   UNW_VE_V15  = 64 + 15,
1123   UNW_VE_V16  = 64 + 16,
1124   UNW_VE_V17  = 64 + 17,
1125   UNW_VE_V18  = 64 + 18,
1126   UNW_VE_V19  = 64 + 19,
1127   UNW_VE_V20  = 64 + 20,
1128   UNW_VE_V21  = 64 + 21,
1129   UNW_VE_V22  = 64 + 22,
1130   UNW_VE_V23  = 64 + 23,
1131   UNW_VE_V24  = 64 + 24,
1132   UNW_VE_V25  = 64 + 25,
1133   UNW_VE_V26  = 64 + 26,
1134   UNW_VE_V27  = 64 + 27,
1135   UNW_VE_V28  = 64 + 28,
1136   UNW_VE_V29  = 64 + 29,
1137   UNW_VE_V30  = 64 + 30,
1138   UNW_VE_V31  = 64 + 31,
1139   UNW_VE_V32  = 64 + 32,
1140   UNW_VE_V33  = 64 + 33,
1141   UNW_VE_V34  = 64 + 34,
1142   UNW_VE_V35  = 64 + 35,
1143   UNW_VE_V36  = 64 + 36,
1144   UNW_VE_V37  = 64 + 37,
1145   UNW_VE_V38  = 64 + 38,
1146   UNW_VE_V39  = 64 + 39,
1147   UNW_VE_V40  = 64 + 40,
1148   UNW_VE_V41  = 64 + 41,
1149   UNW_VE_V42  = 64 + 42,
1150   UNW_VE_V43  = 64 + 43,
1151   UNW_VE_V44  = 64 + 44,
1152   UNW_VE_V45  = 64 + 45,
1153   UNW_VE_V46  = 64 + 46,
1154   UNW_VE_V47  = 64 + 47,
1155   UNW_VE_V48  = 64 + 48,
1156   UNW_VE_V49  = 64 + 49,
1157   UNW_VE_V50  = 64 + 50,
1158   UNW_VE_V51  = 64 + 51,
1159   UNW_VE_V52  = 64 + 52,
1160   UNW_VE_V53  = 64 + 53,
1161   UNW_VE_V54  = 64 + 54,
1162   UNW_VE_V55  = 64 + 55,
1163   UNW_VE_V56  = 64 + 56,
1164   UNW_VE_V57  = 64 + 57,
1165   UNW_VE_V58  = 64 + 58,
1166   UNW_VE_V59  = 64 + 59,
1167   UNW_VE_V60  = 64 + 60,
1168   UNW_VE_V61  = 64 + 61,
1169   UNW_VE_V62  = 64 + 62,
1170   UNW_VE_V63  = 64 + 63,
1171   UNW_VE_VM0  = 128 + 0,
1172   UNW_VE_VM1  = 128 + 1,
1173   UNW_VE_VM2  = 128 + 2,
1174   UNW_VE_VM3  = 128 + 3,
1175   UNW_VE_VM4  = 128 + 4,
1176   UNW_VE_VM5  = 128 + 5,
1177   UNW_VE_VM6  = 128 + 6,
1178   UNW_VE_VM7  = 128 + 7,
1179   UNW_VE_VM8  = 128 + 8,
1180   UNW_VE_VM9  = 128 + 9,
1181   UNW_VE_VM10 = 128 + 10,
1182   UNW_VE_VM11 = 128 + 11,
1183   UNW_VE_VM12 = 128 + 12,
1184   UNW_VE_VM13 = 128 + 13,
1185   UNW_VE_VM14 = 128 + 14,
1186   UNW_VE_VM15 = 128 + 15, // = 143
1187 
1188   // Following registers don't have DWARF register numbers.
1189   UNW_VE_VIXR = 144,
1190   UNW_VE_VL   = 145,
1191 };
1192 
1193 // s390x register numbers
1194 enum {
1195   UNW_S390X_R0      = 0,
1196   UNW_S390X_R1      = 1,
1197   UNW_S390X_R2      = 2,
1198   UNW_S390X_R3      = 3,
1199   UNW_S390X_R4      = 4,
1200   UNW_S390X_R5      = 5,
1201   UNW_S390X_R6      = 6,
1202   UNW_S390X_R7      = 7,
1203   UNW_S390X_R8      = 8,
1204   UNW_S390X_R9      = 9,
1205   UNW_S390X_R10     = 10,
1206   UNW_S390X_R11     = 11,
1207   UNW_S390X_R12     = 12,
1208   UNW_S390X_R13     = 13,
1209   UNW_S390X_R14     = 14,
1210   UNW_S390X_R15     = 15,
1211   UNW_S390X_F0      = 16,
1212   UNW_S390X_F2      = 17,
1213   UNW_S390X_F4      = 18,
1214   UNW_S390X_F6      = 19,
1215   UNW_S390X_F1      = 20,
1216   UNW_S390X_F3      = 21,
1217   UNW_S390X_F5      = 22,
1218   UNW_S390X_F7      = 23,
1219   UNW_S390X_F8      = 24,
1220   UNW_S390X_F10     = 25,
1221   UNW_S390X_F12     = 26,
1222   UNW_S390X_F14     = 27,
1223   UNW_S390X_F9      = 28,
1224   UNW_S390X_F11     = 29,
1225   UNW_S390X_F13     = 30,
1226   UNW_S390X_F15     = 31,
1227   // 32-47 Control Registers
1228   // 48-63 Access Registers
1229   UNW_S390X_PSWM    = 64,
1230   UNW_S390X_PSWA    = 65,
1231   // 66-67 Reserved
1232   // 68-83 Vector Registers %v16-%v31
1233 };
1234 
1235 // LoongArch registers.
1236 enum {
1237   UNW_LOONGARCH_R0 = 0,
1238   UNW_LOONGARCH_R1 = 1,
1239   UNW_LOONGARCH_R2 = 2,
1240   UNW_LOONGARCH_R3 = 3,
1241   UNW_LOONGARCH_R4 = 4,
1242   UNW_LOONGARCH_R5 = 5,
1243   UNW_LOONGARCH_R6 = 6,
1244   UNW_LOONGARCH_R7 = 7,
1245   UNW_LOONGARCH_R8 = 8,
1246   UNW_LOONGARCH_R9 = 9,
1247   UNW_LOONGARCH_R10 = 10,
1248   UNW_LOONGARCH_R11 = 11,
1249   UNW_LOONGARCH_R12 = 12,
1250   UNW_LOONGARCH_R13 = 13,
1251   UNW_LOONGARCH_R14 = 14,
1252   UNW_LOONGARCH_R15 = 15,
1253   UNW_LOONGARCH_R16 = 16,
1254   UNW_LOONGARCH_R17 = 17,
1255   UNW_LOONGARCH_R18 = 18,
1256   UNW_LOONGARCH_R19 = 19,
1257   UNW_LOONGARCH_R20 = 20,
1258   UNW_LOONGARCH_R21 = 21,
1259   UNW_LOONGARCH_R22 = 22,
1260   UNW_LOONGARCH_R23 = 23,
1261   UNW_LOONGARCH_R24 = 24,
1262   UNW_LOONGARCH_R25 = 25,
1263   UNW_LOONGARCH_R26 = 26,
1264   UNW_LOONGARCH_R27 = 27,
1265   UNW_LOONGARCH_R28 = 28,
1266   UNW_LOONGARCH_R29 = 29,
1267   UNW_LOONGARCH_R30 = 30,
1268   UNW_LOONGARCH_R31 = 31,
1269   UNW_LOONGARCH_F0 = 32,
1270   UNW_LOONGARCH_F1 = 33,
1271   UNW_LOONGARCH_F2 = 34,
1272   UNW_LOONGARCH_F3 = 35,
1273   UNW_LOONGARCH_F4 = 36,
1274   UNW_LOONGARCH_F5 = 37,
1275   UNW_LOONGARCH_F6 = 38,
1276   UNW_LOONGARCH_F7 = 39,
1277   UNW_LOONGARCH_F8 = 40,
1278   UNW_LOONGARCH_F9 = 41,
1279   UNW_LOONGARCH_F10 = 42,
1280   UNW_LOONGARCH_F11 = 43,
1281   UNW_LOONGARCH_F12 = 44,
1282   UNW_LOONGARCH_F13 = 45,
1283   UNW_LOONGARCH_F14 = 46,
1284   UNW_LOONGARCH_F15 = 47,
1285   UNW_LOONGARCH_F16 = 48,
1286   UNW_LOONGARCH_F17 = 49,
1287   UNW_LOONGARCH_F18 = 50,
1288   UNW_LOONGARCH_F19 = 51,
1289   UNW_LOONGARCH_F20 = 52,
1290   UNW_LOONGARCH_F21 = 53,
1291   UNW_LOONGARCH_F22 = 54,
1292   UNW_LOONGARCH_F23 = 55,
1293   UNW_LOONGARCH_F24 = 56,
1294   UNW_LOONGARCH_F25 = 57,
1295   UNW_LOONGARCH_F26 = 58,
1296   UNW_LOONGARCH_F27 = 59,
1297   UNW_LOONGARCH_F28 = 60,
1298   UNW_LOONGARCH_F29 = 61,
1299   UNW_LOONGARCH_F30 = 62,
1300   UNW_LOONGARCH_F31 = 63,
1301 };
1302 
1303 #endif
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