include/libdrm/mga_drm.h

0001 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
0002  * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
0003  *
0004  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
0005  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0006  * All rights reserved.
0007  *
0008  * Permission is hereby granted, free of charge, to any person obtaining a
0009  * copy of this software and associated documentation files (the "Software"),
0010  * to deal in the Software without restriction, including without limitation
0011  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0012  * and/or sell copies of the Software, and to permit persons to whom the
0013  * Software is furnished to do so, subject to the following conditions:
0014  *
0015  * The above copyright notice and this permission notice (including the next
0016  * paragraph) shall be included in all copies or substantial portions of the
0017  * Software.
0018  *
0019  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0020  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0021  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0022  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0023  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0024  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0025  * OTHER DEALINGS IN THE SOFTWARE.
0026  *
0027  * Authors:
0028  *    Jeff Hartmann <jhartmann@valinux.com>
0029  *    Keith Whitwell <keith@tungstengraphics.com>
0030  *
0031  * Rewritten by:
0032  *    Gareth Hughes <gareth@valinux.com>
0033  */
0034
0035 #ifndef __MGA_DRM_H__
0036 #define __MGA_DRM_H__
0037
0038 #include "drm.h"
0039
0040 #if defined(__cplusplus)
0041 extern "C" {
0042 #endif
0043
0044 /* WARNING: If you change any of these defines, make sure to change the
0045  * defines in the Xserver file (mga_sarea.h)
0046  */
0047
0048 #ifndef __MGA_SAREA_DEFINES__
0049 #define __MGA_SAREA_DEFINES__
0050
0051 /* WARP pipe flags
0052  */
0053 #define MGA_F           0x1 /* fog */
0054 #define MGA_A           0x2 /* alpha */
0055 #define MGA_S           0x4 /* specular */
0056 #define MGA_T2          0x8 /* multitexture */
0057
0058 #define MGA_WARP_TGZ        0
0059 #define MGA_WARP_TGZF       (MGA_F)
0060 #define MGA_WARP_TGZA       (MGA_A)
0061 #define MGA_WARP_TGZAF      (MGA_F|MGA_A)
0062 #define MGA_WARP_TGZS       (MGA_S)
0063 #define MGA_WARP_TGZSF      (MGA_S|MGA_F)
0064 #define MGA_WARP_TGZSA      (MGA_S|MGA_A)
0065 #define MGA_WARP_TGZSAF     (MGA_S|MGA_F|MGA_A)
0066 #define MGA_WARP_T2GZ       (MGA_T2)
0067 #define MGA_WARP_T2GZF      (MGA_T2|MGA_F)
0068 #define MGA_WARP_T2GZA      (MGA_T2|MGA_A)
0069 #define MGA_WARP_T2GZAF     (MGA_T2|MGA_A|MGA_F)
0070 #define MGA_WARP_T2GZS      (MGA_T2|MGA_S)
0071 #define MGA_WARP_T2GZSF     (MGA_T2|MGA_S|MGA_F)
0072 #define MGA_WARP_T2GZSA     (MGA_T2|MGA_S|MGA_A)
0073 #define MGA_WARP_T2GZSAF    (MGA_T2|MGA_S|MGA_F|MGA_A)
0074
0075 #define MGA_MAX_G200_PIPES  8   /* no multitex */
0076 #define MGA_MAX_G400_PIPES  16
0077 #define MGA_MAX_WARP_PIPES  MGA_MAX_G400_PIPES
0078 #define MGA_WARP_UCODE_SIZE 32768   /* in bytes */
0079
0080 #define MGA_CARD_TYPE_G200  1
0081 #define MGA_CARD_TYPE_G400  2
0082 #define MGA_CARD_TYPE_G450  3   /* not currently used */
0083 #define MGA_CARD_TYPE_G550  4
0084
0085 #define MGA_FRONT       0x1
0086 #define MGA_BACK        0x2
0087 #define MGA_DEPTH       0x4
0088
0089 /* What needs to be changed for the current vertex dma buffer?
0090  */
0091 #define MGA_UPLOAD_CONTEXT  0x1
0092 #define MGA_UPLOAD_TEX0     0x2
0093 #define MGA_UPLOAD_TEX1     0x4
0094 #define MGA_UPLOAD_PIPE     0x8
0095 #define MGA_UPLOAD_TEX0IMAGE    0x10    /* handled client-side */
0096 #define MGA_UPLOAD_TEX1IMAGE    0x20    /* handled client-side */
0097 #define MGA_UPLOAD_2D       0x40
0098 #define MGA_WAIT_AGE        0x80    /* handled client-side */
0099 #define MGA_UPLOAD_CLIPRECTS    0x100   /* handled client-side */
0100 #if 0
0101 #define MGA_DMA_FLUSH       0x200   /* set when someone gets the lock
0102                        quiescent */
0103 #endif
0104
0105 /* 32 buffers of 64k each, total 2 meg.
0106  */
0107 #define MGA_BUFFER_SIZE     (1 << 16)
0108 #define MGA_NUM_BUFFERS     128
0109
0110 /* Keep these small for testing.
0111  */
0112 #define MGA_NR_SAREA_CLIPRECTS  8
0113
0114 /* 2 heaps (1 for card, 1 for agp), each divided into up to 128
0115  * regions, subject to a minimum region size of (1<<16) == 64k.
0116  *
0117  * Clients may subdivide regions internally, but when sharing between
0118  * clients, the region size is the minimum granularity.
0119  */
0120
0121 #define MGA_CARD_HEAP           0
0122 #define MGA_AGP_HEAP            1
0123 #define MGA_NR_TEX_HEAPS        2
0124 #define MGA_NR_TEX_REGIONS      16
0125 #define MGA_LOG_MIN_TEX_REGION_SIZE 16
0126
0127 #define  DRM_MGA_IDLE_RETRY          2048
0128
0129 #endif              /* __MGA_SAREA_DEFINES__ */
0130
0131 /* Setup registers for 3D context
0132  */
0133 typedef struct {
0134     unsigned int dstorg;
0135     unsigned int maccess;
0136     unsigned int plnwt;
0137     unsigned int dwgctl;
0138     unsigned int alphactrl;
0139     unsigned int fogcolor;
0140     unsigned int wflag;
0141     unsigned int tdualstage0;
0142     unsigned int tdualstage1;
0143     unsigned int fcol;
0144     unsigned int stencil;
0145     unsigned int stencilctl;
0146 } drm_mga_context_regs_t;
0147
0148 /* Setup registers for 2D, X server
0149  */
0150 typedef struct {
0151     unsigned int pitch;
0152 } drm_mga_server_regs_t;
0153
0154 /* Setup registers for each texture unit
0155  */
0156 typedef struct {
0157     unsigned int texctl;
0158     unsigned int texctl2;
0159     unsigned int texfilter;
0160     unsigned int texbordercol;
0161     unsigned int texorg;
0162     unsigned int texwidth;
0163     unsigned int texheight;
0164     unsigned int texorg1;
0165     unsigned int texorg2;
0166     unsigned int texorg3;
0167     unsigned int texorg4;
0168 } drm_mga_texture_regs_t;
0169
0170 /* General aging mechanism
0171  */
0172 typedef struct {
0173     unsigned int head;  /* Position of head pointer          */
0174     unsigned int wrap;  /* Primary DMA wrap count            */
0175 } drm_mga_age_t;
0176
0177 typedef struct _drm_mga_sarea {
0178     /* The channel for communication of state information to the kernel
0179      * on firing a vertex dma buffer.
0180      */
0181     drm_mga_context_regs_t context_state;
0182     drm_mga_server_regs_t server_state;
0183     drm_mga_texture_regs_t tex_state[2];
0184     unsigned int warp_pipe;
0185     unsigned int dirty;
0186     unsigned int vertsize;
0187
0188     /* The current cliprects, or a subset thereof.
0189      */
0190     struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
0191     unsigned int nbox;
0192
0193     /* Information about the most recently used 3d drawable.  The
0194      * client fills in the req_* fields, the server fills in the
0195      * exported_ fields and puts the cliprects into boxes, above.
0196      *
0197      * The client clears the exported_drawable field before
0198      * clobbering the boxes data.
0199      */
0200     unsigned int req_drawable;  /* the X drawable id */
0201     unsigned int req_draw_buffer;   /* MGA_FRONT or MGA_BACK */
0202
0203     unsigned int exported_drawable;
0204     unsigned int exported_index;
0205     unsigned int exported_stamp;
0206     unsigned int exported_buffers;
0207     unsigned int exported_nfront;
0208     unsigned int exported_nback;
0209     int exported_back_x, exported_front_x, exported_w;
0210     int exported_back_y, exported_front_y, exported_h;
0211     struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
0212
0213     /* Counters for aging textures and for client-side throttling.
0214      */
0215     unsigned int status[4];
0216     unsigned int last_wrap;
0217
0218     drm_mga_age_t last_frame;
0219     unsigned int last_enqueue;  /* last time a buffer was enqueued */
0220     unsigned int last_dispatch; /* age of the most recently dispatched buffer */
0221     unsigned int last_quiescent;    /*  */
0222
0223     /* LRU lists for texture memory in agp space and on the card.
0224      */
0225     struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
0226     unsigned int texAge[MGA_NR_TEX_HEAPS];
0227
0228     /* Mechanism to validate card state.
0229      */
0230     int ctxOwner;
0231 } drm_mga_sarea_t;
0232
0233 /* MGA specific ioctls
0234  * The device specific ioctl range is 0x40 to 0x79.
0235  */
0236 #define DRM_MGA_INIT     0x00
0237 #define DRM_MGA_FLUSH    0x01
0238 #define DRM_MGA_RESET    0x02
0239 #define DRM_MGA_SWAP     0x03
0240 #define DRM_MGA_CLEAR    0x04
0241 #define DRM_MGA_VERTEX   0x05
0242 #define DRM_MGA_INDICES  0x06
0243 #define DRM_MGA_ILOAD    0x07
0244 #define DRM_MGA_BLIT     0x08
0245 #define DRM_MGA_GETPARAM 0x09
0246
0247 /* 3.2:
0248  * ioctls for operating on fences.
0249  */
0250 #define DRM_MGA_SET_FENCE      0x0a
0251 #define DRM_MGA_WAIT_FENCE     0x0b
0252 #define DRM_MGA_DMA_BOOTSTRAP  0x0c
0253
0254 #define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
0255 #define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
0256 #define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
0257 #define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
0258 #define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
0259 #define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
0260 #define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
0261 #define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
0262 #define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
0263 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
0264 #define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
0265 #define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
0266 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
0267
0268 typedef struct _drm_mga_warp_index {
0269     int installed;
0270     unsigned long phys_addr;
0271     int size;
0272 } drm_mga_warp_index_t;
0273
0274 typedef struct drm_mga_init {
0275     enum {
0276         MGA_INIT_DMA = 0x01,
0277         MGA_CLEANUP_DMA = 0x02
0278     } func;
0279
0280     unsigned long sarea_priv_offset;
0281
0282     int chipset;
0283     int sgram;
0284
0285     unsigned int maccess;
0286
0287     unsigned int fb_cpp;
0288     unsigned int front_offset, front_pitch;
0289     unsigned int back_offset, back_pitch;
0290
0291     unsigned int depth_cpp;
0292     unsigned int depth_offset, depth_pitch;
0293
0294     unsigned int texture_offset[MGA_NR_TEX_HEAPS];
0295     unsigned int texture_size[MGA_NR_TEX_HEAPS];
0296
0297     unsigned long fb_offset;
0298     unsigned long mmio_offset;
0299     unsigned long status_offset;
0300     unsigned long warp_offset;
0301     unsigned long primary_offset;
0302     unsigned long buffers_offset;
0303 } drm_mga_init_t;
0304
0305 typedef struct drm_mga_dma_bootstrap {
0306     /**
0307      * \name AGP texture region
0308      *
0309      * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
0310      * be filled in with the actual AGP texture settings.
0311      *
0312      * \warning
0313      * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
0314      * is zero, it means that PCI memory (most likely through the use of
0315      * an IOMMU) is being used for "AGP" textures.
0316      */
0317     /*@{ */
0318     unsigned long texture_handle; /**< Handle used to map AGP textures. */
0319     __u32 texture_size;       /**< Size of the AGP texture region. */
0320     /*@} */
0321
0322     /**
0323      * Requested size of the primary DMA region.
0324      *
0325      * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
0326      * filled in with the actual AGP mode.  If AGP was not available
0327      */
0328     __u32 primary_size;
0329
0330     /**
0331      * Requested number of secondary DMA buffers.
0332      *
0333      * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
0334      * filled in with the actual number of secondary DMA buffers
0335      * allocated.  Particularly when PCI DMA is used, this may be
0336      * (subtantially) less than the number requested.
0337      */
0338     __u32 secondary_bin_count;
0339
0340     /**
0341      * Requested size of each secondary DMA buffer.
0342      *
0343      * While the kernel \b is free to reduce
0344      * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
0345      * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
0346      */
0347     __u32 secondary_bin_size;
0348
0349     /**
0350      * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
0351      * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported.  If this value is
0352      * zero, it means that PCI DMA should be used, even if AGP is
0353      * possible.
0354      *
0355      * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
0356      * filled in with the actual AGP mode.  If AGP was not available
0357      * (i.e., PCI DMA was used), this value will be zero.
0358      */
0359     __u32 agp_mode;
0360
0361     /**
0362      * Desired AGP GART size, measured in megabytes.
0363      */
0364     __u8 agp_size;
0365 } drm_mga_dma_bootstrap_t;
0366
0367 typedef struct drm_mga_clear {
0368     unsigned int flags;
0369     unsigned int clear_color;
0370     unsigned int clear_depth;
0371     unsigned int color_mask;
0372     unsigned int depth_mask;
0373 } drm_mga_clear_t;
0374
0375 typedef struct drm_mga_vertex {
0376     int idx;        /* buffer to queue */
0377     int used;       /* bytes in use */
0378     int discard;        /* client finished with buffer?  */
0379 } drm_mga_vertex_t;
0380
0381 typedef struct drm_mga_indices {
0382     int idx;        /* buffer to queue */
0383     unsigned int start;
0384     unsigned int end;
0385     int discard;        /* client finished with buffer?  */
0386 } drm_mga_indices_t;
0387
0388 typedef struct drm_mga_iload {
0389     int idx;
0390     unsigned int dstorg;
0391     unsigned int length;
0392 } drm_mga_iload_t;
0393
0394 typedef struct _drm_mga_blit {
0395     unsigned int planemask;
0396     unsigned int srcorg;
0397     unsigned int dstorg;
0398     int src_pitch, dst_pitch;
0399     int delta_sx, delta_sy;
0400     int delta_dx, delta_dy;
0401     int height, ydir;   /* flip image vertically */
0402     int source_pitch, dest_pitch;
0403 } drm_mga_blit_t;
0404
0405 /* 3.1: An ioctl to get parameters that aren't available to the 3d
0406  * client any other way.
0407  */
0408 #define MGA_PARAM_IRQ_NR            1
0409
0410 /* 3.2: Query the actual card type.  The DDX only distinguishes between
0411  * G200 chips and non-G200 chips, which it calls G400.  It turns out that
0412  * there are some very sublte differences between the G4x0 chips and the G550
0413  * chips.  Using this parameter query, a client-side driver can detect the
0414  * difference between a G4x0 and a G550.
0415  */
0416 #define MGA_PARAM_CARD_TYPE         2
0417
0418 typedef struct drm_mga_getparam {
0419     int param;
0420     void *value;
0421 } drm_mga_getparam_t;
0422
0423 #if defined(__cplusplus)
0424 }
0425 #endif
0426
0427 #endif