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Warning, /include/clang/Basic/arm_mve_builtin_sema.inc is written in an unsupported language. File is not indexed. 

0001 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_f32:
0002 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_s32:
0003 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_u32:
0004 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_f32:
0005 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_s32:
0006 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_u32:
0007 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_f32:
0008 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_s32:
0009 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_u32:
0010 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_f32:
0011 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_s32:
0012 case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_u32:
0013 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_f32:
0014 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_f32:
0015 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_s32:
0016 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_u32:
0017 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_s32:
0018 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_u32:
0019 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_f32:
0020 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_f32:
0021 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_s32:
0022 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_u32:
0023 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_s32:
0024 case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_u32:
0025   return SemaRef.BuiltinConstantArgRange(TheCall, 1, -0x1FC, 0x1FC) ||
0026          SemaRef.BuiltinConstantArgMultiple(TheCall, 1, 4);
0027 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_s64:
0028 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_u64:
0029 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_s64:
0030 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_u64:
0031 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_s64:
0032 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_u64:
0033 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_s64:
0034 case ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_u64:
0035 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_s64:
0036 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_u64:
0037 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_s64:
0038 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_u64:
0039 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_s64:
0040 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_u64:
0041 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_s64:
0042 case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_u64:
0043   return SemaRef.BuiltinConstantArgRange(TheCall, 1, -0x3F8, 0x3F8) ||
0044          SemaRef.BuiltinConstantArgMultiple(TheCall, 1, 8);
0045 case ARM::BI__builtin_arm_mve_vgetq_lane_s64:
0046 case ARM::BI__builtin_arm_mve_vgetq_lane_u64:
0047   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x0, 0x1);
0048 case ARM::BI__builtin_arm_mve_vqshlq_n_s32:
0049 case ARM::BI__builtin_arm_mve_vqshlq_n_u32:
0050 case ARM::BI__builtin_arm_mve_vqshluq_n_s32:
0051 case ARM::BI__builtin_arm_mve_vshlq_n_s32:
0052 case ARM::BI__builtin_arm_mve_vshlq_n_u32:
0053 case ARM::BI__builtin_arm_mve_vshlq_x_n_s32:
0054 case ARM::BI__builtin_arm_mve_vshlq_x_n_u32:
0055   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x0, 0x1F);
0056 case ARM::BI__builtin_arm_mve_vgetq_lane_f32:
0057 case ARM::BI__builtin_arm_mve_vgetq_lane_s32:
0058 case ARM::BI__builtin_arm_mve_vgetq_lane_u32:
0059   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x0, 0x3);
0060 case ARM::BI__builtin_arm_mve_vgetq_lane_f16:
0061 case ARM::BI__builtin_arm_mve_vgetq_lane_s16:
0062 case ARM::BI__builtin_arm_mve_vgetq_lane_u16:
0063 case ARM::BI__builtin_arm_mve_vqshlq_n_s8:
0064 case ARM::BI__builtin_arm_mve_vqshlq_n_u8:
0065 case ARM::BI__builtin_arm_mve_vqshluq_n_s8:
0066 case ARM::BI__builtin_arm_mve_vshlq_n_s8:
0067 case ARM::BI__builtin_arm_mve_vshlq_n_u8:
0068 case ARM::BI__builtin_arm_mve_vshlq_x_n_s8:
0069 case ARM::BI__builtin_arm_mve_vshlq_x_n_u8:
0070   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x0, 0x7);
0071 case ARM::BI__builtin_arm_mve_vgetq_lane_s8:
0072 case ARM::BI__builtin_arm_mve_vgetq_lane_u8:
0073 case ARM::BI__builtin_arm_mve_vqshlq_n_s16:
0074 case ARM::BI__builtin_arm_mve_vqshlq_n_u16:
0075 case ARM::BI__builtin_arm_mve_vqshluq_n_s16:
0076 case ARM::BI__builtin_arm_mve_vshlq_n_s16:
0077 case ARM::BI__builtin_arm_mve_vshlq_n_u16:
0078 case ARM::BI__builtin_arm_mve_vshlq_x_n_s16:
0079 case ARM::BI__builtin_arm_mve_vshlq_x_n_u16:
0080   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x0, 0xF);
0081 case ARM::BI__builtin_arm_mve_vcvtq_n_f16_s16:
0082 case ARM::BI__builtin_arm_mve_vcvtq_n_f16_u16:
0083 case ARM::BI__builtin_arm_mve_vcvtq_n_s16_f16:
0084 case ARM::BI__builtin_arm_mve_vcvtq_n_u16_f16:
0085 case ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_s16:
0086 case ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_u16:
0087 case ARM::BI__builtin_arm_mve_vcvtq_x_n_s16_f16:
0088 case ARM::BI__builtin_arm_mve_vcvtq_x_n_u16_f16:
0089 case ARM::BI__builtin_arm_mve_vrshrq_n_s16:
0090 case ARM::BI__builtin_arm_mve_vrshrq_n_u16:
0091 case ARM::BI__builtin_arm_mve_vrshrq_x_n_s16:
0092 case ARM::BI__builtin_arm_mve_vrshrq_x_n_u16:
0093 case ARM::BI__builtin_arm_mve_vshllbq_n_s16:
0094 case ARM::BI__builtin_arm_mve_vshllbq_n_u16:
0095 case ARM::BI__builtin_arm_mve_vshllbq_x_n_s16:
0096 case ARM::BI__builtin_arm_mve_vshllbq_x_n_u16:
0097 case ARM::BI__builtin_arm_mve_vshlltq_n_s16:
0098 case ARM::BI__builtin_arm_mve_vshlltq_n_u16:
0099 case ARM::BI__builtin_arm_mve_vshlltq_x_n_s16:
0100 case ARM::BI__builtin_arm_mve_vshlltq_x_n_u16:
0101 case ARM::BI__builtin_arm_mve_vshrq_n_s16:
0102 case ARM::BI__builtin_arm_mve_vshrq_n_u16:
0103 case ARM::BI__builtin_arm_mve_vshrq_x_n_s16:
0104 case ARM::BI__builtin_arm_mve_vshrq_x_n_u16:
0105   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x1, 0x10);
0106 case ARM::BI__builtin_arm_mve_sqshl:
0107 case ARM::BI__builtin_arm_mve_sqshll:
0108 case ARM::BI__builtin_arm_mve_srshr:
0109 case ARM::BI__builtin_arm_mve_srshrl:
0110 case ARM::BI__builtin_arm_mve_uqshl:
0111 case ARM::BI__builtin_arm_mve_uqshll:
0112 case ARM::BI__builtin_arm_mve_urshr:
0113 case ARM::BI__builtin_arm_mve_urshrl:
0114 case ARM::BI__builtin_arm_mve_vcvtq_n_f32_s32:
0115 case ARM::BI__builtin_arm_mve_vcvtq_n_f32_u32:
0116 case ARM::BI__builtin_arm_mve_vcvtq_n_s32_f32:
0117 case ARM::BI__builtin_arm_mve_vcvtq_n_u32_f32:
0118 case ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_s32:
0119 case ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_u32:
0120 case ARM::BI__builtin_arm_mve_vcvtq_x_n_s32_f32:
0121 case ARM::BI__builtin_arm_mve_vcvtq_x_n_u32_f32:
0122 case ARM::BI__builtin_arm_mve_vrshrq_n_s32:
0123 case ARM::BI__builtin_arm_mve_vrshrq_n_u32:
0124 case ARM::BI__builtin_arm_mve_vrshrq_x_n_s32:
0125 case ARM::BI__builtin_arm_mve_vrshrq_x_n_u32:
0126 case ARM::BI__builtin_arm_mve_vshrq_n_s32:
0127 case ARM::BI__builtin_arm_mve_vshrq_n_u32:
0128 case ARM::BI__builtin_arm_mve_vshrq_x_n_s32:
0129 case ARM::BI__builtin_arm_mve_vshrq_x_n_u32:
0130   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x1, 0x20);
0131 case ARM::BI__builtin_arm_mve_vddupq_n_u16:
0132 case ARM::BI__builtin_arm_mve_vddupq_n_u32:
0133 case ARM::BI__builtin_arm_mve_vddupq_n_u8:
0134 case ARM::BI__builtin_arm_mve_vddupq_wb_u16:
0135 case ARM::BI__builtin_arm_mve_vddupq_wb_u32:
0136 case ARM::BI__builtin_arm_mve_vddupq_wb_u8:
0137 case ARM::BI__builtin_arm_mve_vddupq_x_n_u16:
0138 case ARM::BI__builtin_arm_mve_vddupq_x_n_u32:
0139 case ARM::BI__builtin_arm_mve_vddupq_x_n_u8:
0140 case ARM::BI__builtin_arm_mve_vddupq_x_wb_u16:
0141 case ARM::BI__builtin_arm_mve_vddupq_x_wb_u32:
0142 case ARM::BI__builtin_arm_mve_vddupq_x_wb_u8:
0143 case ARM::BI__builtin_arm_mve_vidupq_n_u16:
0144 case ARM::BI__builtin_arm_mve_vidupq_n_u32:
0145 case ARM::BI__builtin_arm_mve_vidupq_n_u8:
0146 case ARM::BI__builtin_arm_mve_vidupq_wb_u16:
0147 case ARM::BI__builtin_arm_mve_vidupq_wb_u32:
0148 case ARM::BI__builtin_arm_mve_vidupq_wb_u8:
0149 case ARM::BI__builtin_arm_mve_vidupq_x_n_u16:
0150 case ARM::BI__builtin_arm_mve_vidupq_x_n_u32:
0151 case ARM::BI__builtin_arm_mve_vidupq_x_n_u8:
0152 case ARM::BI__builtin_arm_mve_vidupq_x_wb_u16:
0153 case ARM::BI__builtin_arm_mve_vidupq_x_wb_u32:
0154 case ARM::BI__builtin_arm_mve_vidupq_x_wb_u8:
0155   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x1, 0x8) ||
0156          SemaRef.BuiltinConstantArgPower2(TheCall, 1);
0157 case ARM::BI__builtin_arm_mve_vrshrq_n_s8:
0158 case ARM::BI__builtin_arm_mve_vrshrq_n_u8:
0159 case ARM::BI__builtin_arm_mve_vrshrq_x_n_s8:
0160 case ARM::BI__builtin_arm_mve_vrshrq_x_n_u8:
0161 case ARM::BI__builtin_arm_mve_vshllbq_n_s8:
0162 case ARM::BI__builtin_arm_mve_vshllbq_n_u8:
0163 case ARM::BI__builtin_arm_mve_vshllbq_x_n_s8:
0164 case ARM::BI__builtin_arm_mve_vshllbq_x_n_u8:
0165 case ARM::BI__builtin_arm_mve_vshlltq_n_s8:
0166 case ARM::BI__builtin_arm_mve_vshlltq_n_u8:
0167 case ARM::BI__builtin_arm_mve_vshlltq_x_n_s8:
0168 case ARM::BI__builtin_arm_mve_vshlltq_x_n_u8:
0169 case ARM::BI__builtin_arm_mve_vshrq_n_s8:
0170 case ARM::BI__builtin_arm_mve_vshrq_n_u8:
0171 case ARM::BI__builtin_arm_mve_vshrq_x_n_s8:
0172 case ARM::BI__builtin_arm_mve_vshrq_x_n_u8:
0173   return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0x1, 0x8);
0174 case ARM::BI__builtin_arm_mve_vsetq_lane_s64:
0175 case ARM::BI__builtin_arm_mve_vsetq_lane_u64:
0176   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x0, 0x1);
0177 case ARM::BI__builtin_arm_mve_vqshlq_m_n_s32:
0178 case ARM::BI__builtin_arm_mve_vqshlq_m_n_u32:
0179 case ARM::BI__builtin_arm_mve_vqshluq_m_n_s32:
0180 case ARM::BI__builtin_arm_mve_vshlq_m_n_s32:
0181 case ARM::BI__builtin_arm_mve_vshlq_m_n_u32:
0182 case ARM::BI__builtin_arm_mve_vsliq_m_n_s32:
0183 case ARM::BI__builtin_arm_mve_vsliq_m_n_u32:
0184 case ARM::BI__builtin_arm_mve_vsliq_n_s32:
0185 case ARM::BI__builtin_arm_mve_vsliq_n_u32:
0186   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x0, 0x1F);
0187 case ARM::BI__builtin_arm_mve_vsetq_lane_f32:
0188 case ARM::BI__builtin_arm_mve_vsetq_lane_s32:
0189 case ARM::BI__builtin_arm_mve_vsetq_lane_u32:
0190   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x0, 0x3);
0191 case ARM::BI__builtin_arm_mve_vqshlq_m_n_s8:
0192 case ARM::BI__builtin_arm_mve_vqshlq_m_n_u8:
0193 case ARM::BI__builtin_arm_mve_vqshluq_m_n_s8:
0194 case ARM::BI__builtin_arm_mve_vsetq_lane_f16:
0195 case ARM::BI__builtin_arm_mve_vsetq_lane_s16:
0196 case ARM::BI__builtin_arm_mve_vsetq_lane_u16:
0197 case ARM::BI__builtin_arm_mve_vshlq_m_n_s8:
0198 case ARM::BI__builtin_arm_mve_vshlq_m_n_u8:
0199 case ARM::BI__builtin_arm_mve_vsliq_m_n_s8:
0200 case ARM::BI__builtin_arm_mve_vsliq_m_n_u8:
0201 case ARM::BI__builtin_arm_mve_vsliq_n_s8:
0202 case ARM::BI__builtin_arm_mve_vsliq_n_u8:
0203   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x0, 0x7);
0204 case ARM::BI__builtin_arm_mve_vqshlq_m_n_s16:
0205 case ARM::BI__builtin_arm_mve_vqshlq_m_n_u16:
0206 case ARM::BI__builtin_arm_mve_vqshluq_m_n_s16:
0207 case ARM::BI__builtin_arm_mve_vsetq_lane_s8:
0208 case ARM::BI__builtin_arm_mve_vsetq_lane_u8:
0209 case ARM::BI__builtin_arm_mve_vshlq_m_n_s16:
0210 case ARM::BI__builtin_arm_mve_vshlq_m_n_u16:
0211 case ARM::BI__builtin_arm_mve_vsliq_m_n_s16:
0212 case ARM::BI__builtin_arm_mve_vsliq_m_n_u16:
0213 case ARM::BI__builtin_arm_mve_vsliq_n_s16:
0214 case ARM::BI__builtin_arm_mve_vsliq_n_u16:
0215   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x0, 0xF);
0216 case ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_s16:
0217 case ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_u16:
0218 case ARM::BI__builtin_arm_mve_vcvtq_m_n_s16_f16:
0219 case ARM::BI__builtin_arm_mve_vcvtq_m_n_u16_f16:
0220 case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s32:
0221 case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u32:
0222 case ARM::BI__builtin_arm_mve_vqrshrnbq_n_s32:
0223 case ARM::BI__builtin_arm_mve_vqrshrnbq_n_u32:
0224 case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s32:
0225 case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u32:
0226 case ARM::BI__builtin_arm_mve_vqrshrntq_n_s32:
0227 case ARM::BI__builtin_arm_mve_vqrshrntq_n_u32:
0228 case ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s32:
0229 case ARM::BI__builtin_arm_mve_vqrshrunbq_n_s32:
0230 case ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s32:
0231 case ARM::BI__builtin_arm_mve_vqrshruntq_n_s32:
0232 case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s32:
0233 case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u32:
0234 case ARM::BI__builtin_arm_mve_vqshrnbq_n_s32:
0235 case ARM::BI__builtin_arm_mve_vqshrnbq_n_u32:
0236 case ARM::BI__builtin_arm_mve_vqshrntq_m_n_s32:
0237 case ARM::BI__builtin_arm_mve_vqshrntq_m_n_u32:
0238 case ARM::BI__builtin_arm_mve_vqshrntq_n_s32:
0239 case ARM::BI__builtin_arm_mve_vqshrntq_n_u32:
0240 case ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s32:
0241 case ARM::BI__builtin_arm_mve_vqshrunbq_n_s32:
0242 case ARM::BI__builtin_arm_mve_vqshruntq_m_n_s32:
0243 case ARM::BI__builtin_arm_mve_vqshruntq_n_s32:
0244 case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s32:
0245 case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u32:
0246 case ARM::BI__builtin_arm_mve_vrshrnbq_n_s32:
0247 case ARM::BI__builtin_arm_mve_vrshrnbq_n_u32:
0248 case ARM::BI__builtin_arm_mve_vrshrntq_m_n_s32:
0249 case ARM::BI__builtin_arm_mve_vrshrntq_m_n_u32:
0250 case ARM::BI__builtin_arm_mve_vrshrntq_n_s32:
0251 case ARM::BI__builtin_arm_mve_vrshrntq_n_u32:
0252 case ARM::BI__builtin_arm_mve_vrshrq_m_n_s16:
0253 case ARM::BI__builtin_arm_mve_vrshrq_m_n_u16:
0254 case ARM::BI__builtin_arm_mve_vshllbq_m_n_s16:
0255 case ARM::BI__builtin_arm_mve_vshllbq_m_n_u16:
0256 case ARM::BI__builtin_arm_mve_vshlltq_m_n_s16:
0257 case ARM::BI__builtin_arm_mve_vshlltq_m_n_u16:
0258 case ARM::BI__builtin_arm_mve_vshrnbq_m_n_s32:
0259 case ARM::BI__builtin_arm_mve_vshrnbq_m_n_u32:
0260 case ARM::BI__builtin_arm_mve_vshrnbq_n_s32:
0261 case ARM::BI__builtin_arm_mve_vshrnbq_n_u32:
0262 case ARM::BI__builtin_arm_mve_vshrntq_m_n_s32:
0263 case ARM::BI__builtin_arm_mve_vshrntq_m_n_u32:
0264 case ARM::BI__builtin_arm_mve_vshrntq_n_s32:
0265 case ARM::BI__builtin_arm_mve_vshrntq_n_u32:
0266 case ARM::BI__builtin_arm_mve_vshrq_m_n_s16:
0267 case ARM::BI__builtin_arm_mve_vshrq_m_n_u16:
0268 case ARM::BI__builtin_arm_mve_vsriq_m_n_s16:
0269 case ARM::BI__builtin_arm_mve_vsriq_m_n_u16:
0270 case ARM::BI__builtin_arm_mve_vsriq_n_s16:
0271 case ARM::BI__builtin_arm_mve_vsriq_n_u16:
0272   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x1, 0x10);
0273 case ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_s32:
0274 case ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_u32:
0275 case ARM::BI__builtin_arm_mve_vcvtq_m_n_s32_f32:
0276 case ARM::BI__builtin_arm_mve_vcvtq_m_n_u32_f32:
0277 case ARM::BI__builtin_arm_mve_vrshrq_m_n_s32:
0278 case ARM::BI__builtin_arm_mve_vrshrq_m_n_u32:
0279 case ARM::BI__builtin_arm_mve_vshlcq_m_s16:
0280 case ARM::BI__builtin_arm_mve_vshlcq_m_s32:
0281 case ARM::BI__builtin_arm_mve_vshlcq_m_s8:
0282 case ARM::BI__builtin_arm_mve_vshlcq_m_u16:
0283 case ARM::BI__builtin_arm_mve_vshlcq_m_u32:
0284 case ARM::BI__builtin_arm_mve_vshlcq_m_u8:
0285 case ARM::BI__builtin_arm_mve_vshlcq_s16:
0286 case ARM::BI__builtin_arm_mve_vshlcq_s32:
0287 case ARM::BI__builtin_arm_mve_vshlcq_s8:
0288 case ARM::BI__builtin_arm_mve_vshlcq_u16:
0289 case ARM::BI__builtin_arm_mve_vshlcq_u32:
0290 case ARM::BI__builtin_arm_mve_vshlcq_u8:
0291 case ARM::BI__builtin_arm_mve_vshrq_m_n_s32:
0292 case ARM::BI__builtin_arm_mve_vshrq_m_n_u32:
0293 case ARM::BI__builtin_arm_mve_vsriq_m_n_s32:
0294 case ARM::BI__builtin_arm_mve_vsriq_m_n_u32:
0295 case ARM::BI__builtin_arm_mve_vsriq_n_s32:
0296 case ARM::BI__builtin_arm_mve_vsriq_n_u32:
0297   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x1, 0x20);
0298 case ARM::BI__builtin_arm_mve_vddupq_m_n_u16:
0299 case ARM::BI__builtin_arm_mve_vddupq_m_n_u32:
0300 case ARM::BI__builtin_arm_mve_vddupq_m_n_u8:
0301 case ARM::BI__builtin_arm_mve_vddupq_m_wb_u16:
0302 case ARM::BI__builtin_arm_mve_vddupq_m_wb_u32:
0303 case ARM::BI__builtin_arm_mve_vddupq_m_wb_u8:
0304 case ARM::BI__builtin_arm_mve_vdwdupq_n_u16:
0305 case ARM::BI__builtin_arm_mve_vdwdupq_n_u32:
0306 case ARM::BI__builtin_arm_mve_vdwdupq_n_u8:
0307 case ARM::BI__builtin_arm_mve_vdwdupq_wb_u16:
0308 case ARM::BI__builtin_arm_mve_vdwdupq_wb_u32:
0309 case ARM::BI__builtin_arm_mve_vdwdupq_wb_u8:
0310 case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u16:
0311 case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u32:
0312 case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u8:
0313 case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u16:
0314 case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u32:
0315 case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u8:
0316 case ARM::BI__builtin_arm_mve_vidupq_m_n_u16:
0317 case ARM::BI__builtin_arm_mve_vidupq_m_n_u32:
0318 case ARM::BI__builtin_arm_mve_vidupq_m_n_u8:
0319 case ARM::BI__builtin_arm_mve_vidupq_m_wb_u16:
0320 case ARM::BI__builtin_arm_mve_vidupq_m_wb_u32:
0321 case ARM::BI__builtin_arm_mve_vidupq_m_wb_u8:
0322 case ARM::BI__builtin_arm_mve_viwdupq_n_u16:
0323 case ARM::BI__builtin_arm_mve_viwdupq_n_u32:
0324 case ARM::BI__builtin_arm_mve_viwdupq_n_u8:
0325 case ARM::BI__builtin_arm_mve_viwdupq_wb_u16:
0326 case ARM::BI__builtin_arm_mve_viwdupq_wb_u32:
0327 case ARM::BI__builtin_arm_mve_viwdupq_wb_u8:
0328 case ARM::BI__builtin_arm_mve_viwdupq_x_n_u16:
0329 case ARM::BI__builtin_arm_mve_viwdupq_x_n_u32:
0330 case ARM::BI__builtin_arm_mve_viwdupq_x_n_u8:
0331 case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u16:
0332 case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u32:
0333 case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u8:
0334   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x1, 0x8) ||
0335          SemaRef.BuiltinConstantArgPower2(TheCall, 2);
0336 case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s16:
0337 case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u16:
0338 case ARM::BI__builtin_arm_mve_vqrshrnbq_n_s16:
0339 case ARM::BI__builtin_arm_mve_vqrshrnbq_n_u16:
0340 case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s16:
0341 case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u16:
0342 case ARM::BI__builtin_arm_mve_vqrshrntq_n_s16:
0343 case ARM::BI__builtin_arm_mve_vqrshrntq_n_u16:
0344 case ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s16:
0345 case ARM::BI__builtin_arm_mve_vqrshrunbq_n_s16:
0346 case ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s16:
0347 case ARM::BI__builtin_arm_mve_vqrshruntq_n_s16:
0348 case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s16:
0349 case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u16:
0350 case ARM::BI__builtin_arm_mve_vqshrnbq_n_s16:
0351 case ARM::BI__builtin_arm_mve_vqshrnbq_n_u16:
0352 case ARM::BI__builtin_arm_mve_vqshrntq_m_n_s16:
0353 case ARM::BI__builtin_arm_mve_vqshrntq_m_n_u16:
0354 case ARM::BI__builtin_arm_mve_vqshrntq_n_s16:
0355 case ARM::BI__builtin_arm_mve_vqshrntq_n_u16:
0356 case ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s16:
0357 case ARM::BI__builtin_arm_mve_vqshrunbq_n_s16:
0358 case ARM::BI__builtin_arm_mve_vqshruntq_m_n_s16:
0359 case ARM::BI__builtin_arm_mve_vqshruntq_n_s16:
0360 case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s16:
0361 case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u16:
0362 case ARM::BI__builtin_arm_mve_vrshrnbq_n_s16:
0363 case ARM::BI__builtin_arm_mve_vrshrnbq_n_u16:
0364 case ARM::BI__builtin_arm_mve_vrshrntq_m_n_s16:
0365 case ARM::BI__builtin_arm_mve_vrshrntq_m_n_u16:
0366 case ARM::BI__builtin_arm_mve_vrshrntq_n_s16:
0367 case ARM::BI__builtin_arm_mve_vrshrntq_n_u16:
0368 case ARM::BI__builtin_arm_mve_vrshrq_m_n_s8:
0369 case ARM::BI__builtin_arm_mve_vrshrq_m_n_u8:
0370 case ARM::BI__builtin_arm_mve_vshllbq_m_n_s8:
0371 case ARM::BI__builtin_arm_mve_vshllbq_m_n_u8:
0372 case ARM::BI__builtin_arm_mve_vshlltq_m_n_s8:
0373 case ARM::BI__builtin_arm_mve_vshlltq_m_n_u8:
0374 case ARM::BI__builtin_arm_mve_vshrnbq_m_n_s16:
0375 case ARM::BI__builtin_arm_mve_vshrnbq_m_n_u16:
0376 case ARM::BI__builtin_arm_mve_vshrnbq_n_s16:
0377 case ARM::BI__builtin_arm_mve_vshrnbq_n_u16:
0378 case ARM::BI__builtin_arm_mve_vshrntq_m_n_s16:
0379 case ARM::BI__builtin_arm_mve_vshrntq_m_n_u16:
0380 case ARM::BI__builtin_arm_mve_vshrntq_n_s16:
0381 case ARM::BI__builtin_arm_mve_vshrntq_n_u16:
0382 case ARM::BI__builtin_arm_mve_vshrq_m_n_s8:
0383 case ARM::BI__builtin_arm_mve_vshrq_m_n_u8:
0384 case ARM::BI__builtin_arm_mve_vsriq_m_n_s8:
0385 case ARM::BI__builtin_arm_mve_vsriq_m_n_u8:
0386 case ARM::BI__builtin_arm_mve_vsriq_n_s8:
0387 case ARM::BI__builtin_arm_mve_vsriq_n_u8:
0388   return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0x1, 0x8);
0389 case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u16:
0390 case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u32:
0391 case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u8:
0392 case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u16:
0393 case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u32:
0394 case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u8:
0395 case ARM::BI__builtin_arm_mve_viwdupq_m_n_u16:
0396 case ARM::BI__builtin_arm_mve_viwdupq_m_n_u32:
0397 case ARM::BI__builtin_arm_mve_viwdupq_m_n_u8:
0398 case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u16:
0399 case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u32:
0400 case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u8:
0401   return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0x1, 0x8) ||
0402          SemaRef.BuiltinConstantArgPower2(TheCall, 3);
0403 case ARM::BI__builtin_arm_mve_vbicq_m_n_s16:
0404 case ARM::BI__builtin_arm_mve_vbicq_m_n_u16:
0405 case ARM::BI__builtin_arm_mve_vbicq_n_s16:
0406 case ARM::BI__builtin_arm_mve_vbicq_n_u16:
0407 case ARM::BI__builtin_arm_mve_vorrq_m_n_s16:
0408 case ARM::BI__builtin_arm_mve_vorrq_m_n_u16:
0409 case ARM::BI__builtin_arm_mve_vorrq_n_s16:
0410 case ARM::BI__builtin_arm_mve_vorrq_n_u16:
0411   return SemaRef.BuiltinConstantArgShiftedByte(TheCall, 1, 16);
0412 case ARM::BI__builtin_arm_mve_vbicq_m_n_s32:
0413 case ARM::BI__builtin_arm_mve_vbicq_m_n_u32:
0414 case ARM::BI__builtin_arm_mve_vbicq_n_s32:
0415 case ARM::BI__builtin_arm_mve_vbicq_n_u32:
0416 case ARM::BI__builtin_arm_mve_vorrq_m_n_s32:
0417 case ARM::BI__builtin_arm_mve_vorrq_m_n_u32:
0418 case ARM::BI__builtin_arm_mve_vorrq_n_s32:
0419 case ARM::BI__builtin_arm_mve_vorrq_n_u32:
0420   return SemaRef.BuiltinConstantArgShiftedByte(TheCall, 1, 32);
0421 case ARM::BI__builtin_arm_mve_vmvnq_n_s16:
0422 case ARM::BI__builtin_arm_mve_vmvnq_n_u16:
0423 case ARM::BI__builtin_arm_mve_vmvnq_x_n_s16:
0424 case ARM::BI__builtin_arm_mve_vmvnq_x_n_u16:
0425   return SemaRef.BuiltinConstantArgShiftedByteOrXXFF(TheCall, 0, 16);
0426 case ARM::BI__builtin_arm_mve_vmvnq_n_s32:
0427 case ARM::BI__builtin_arm_mve_vmvnq_n_u32:
0428 case ARM::BI__builtin_arm_mve_vmvnq_x_n_s32:
0429 case ARM::BI__builtin_arm_mve_vmvnq_x_n_u32:
0430   return SemaRef.BuiltinConstantArgShiftedByteOrXXFF(TheCall, 0, 32);
0431 case ARM::BI__builtin_arm_mve_vmvnq_m_n_s16:
0432 case ARM::BI__builtin_arm_mve_vmvnq_m_n_u16:
0433   return SemaRef.BuiltinConstantArgShiftedByteOrXXFF(TheCall, 1, 16);
0434 case ARM::BI__builtin_arm_mve_vmvnq_m_n_s32:
0435 case ARM::BI__builtin_arm_mve_vmvnq_m_n_u32:
0436   return SemaRef.BuiltinConstantArgShiftedByteOrXXFF(TheCall, 1, 32);
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