Warning, /include/clang/Basic/arm_cde_builtin_aliases.inc is written in an unsupported language. File is not indexed.
0001 static const IntrinToName MapData[] = {
0002 { ARM::BI__builtin_arm_cde_cx1, 1, -1},
0003 { ARM::BI__builtin_arm_cde_cx1a, 5, -1},
0004 { ARM::BI__builtin_arm_cde_cx1d, 10, -1},
0005 { ARM::BI__builtin_arm_cde_cx1da, 15, -1},
0006 { ARM::BI__builtin_arm_cde_cx2, 21, -1},
0007 { ARM::BI__builtin_arm_cde_cx2a, 25, -1},
0008 { ARM::BI__builtin_arm_cde_cx2d, 30, -1},
0009 { ARM::BI__builtin_arm_cde_cx2da, 35, -1},
0010 { ARM::BI__builtin_arm_cde_cx3, 41, -1},
0011 { ARM::BI__builtin_arm_cde_cx3a, 45, -1},
0012 { ARM::BI__builtin_arm_cde_cx3d, 50, -1},
0013 { ARM::BI__builtin_arm_cde_cx3da, 55, -1},
0014 { ARM::BI__builtin_arm_cde_vcx1_u32, 61, -1},
0015 { ARM::BI__builtin_arm_cde_vcx1a_u32, 70, -1},
0016 { ARM::BI__builtin_arm_cde_vcx1d_u64, 80, -1},
0017 { ARM::BI__builtin_arm_cde_vcx1da_u64, 90, -1},
0018 { ARM::BI__builtin_arm_cde_vcx1q_m_f16, 109, 101},
0019 { ARM::BI__builtin_arm_cde_vcx1q_m_f32, 121, 101},
0020 { ARM::BI__builtin_arm_cde_vcx1q_m_s16, 133, 101},
0021 { ARM::BI__builtin_arm_cde_vcx1q_m_s32, 145, 101},
0022 { ARM::BI__builtin_arm_cde_vcx1q_m_s64, 157, 101},
0023 { ARM::BI__builtin_arm_cde_vcx1q_m_s8, 169, 101},
0024 { ARM::BI__builtin_arm_cde_vcx1q_m_u16, 180, 101},
0025 { ARM::BI__builtin_arm_cde_vcx1q_m_u32, 192, 101},
0026 { ARM::BI__builtin_arm_cde_vcx1q_m_u64, 204, 101},
0027 { ARM::BI__builtin_arm_cde_vcx1q_m_u8, 216, 101},
0028 { ARM::BI__builtin_arm_cde_vcx1q_u8, 227, -1},
0029 { ARM::BI__builtin_arm_cde_vcx1qa_f16, 243, 236},
0030 { ARM::BI__builtin_arm_cde_vcx1qa_f32, 254, 236},
0031 { ARM::BI__builtin_arm_cde_vcx1qa_m_f16, 274, 265},
0032 { ARM::BI__builtin_arm_cde_vcx1qa_m_f32, 287, 265},
0033 { ARM::BI__builtin_arm_cde_vcx1qa_m_s16, 300, 265},
0034 { ARM::BI__builtin_arm_cde_vcx1qa_m_s32, 313, 265},
0035 { ARM::BI__builtin_arm_cde_vcx1qa_m_s64, 326, 265},
0036 { ARM::BI__builtin_arm_cde_vcx1qa_m_s8, 339, 265},
0037 { ARM::BI__builtin_arm_cde_vcx1qa_m_u16, 351, 265},
0038 { ARM::BI__builtin_arm_cde_vcx1qa_m_u32, 364, 265},
0039 { ARM::BI__builtin_arm_cde_vcx1qa_m_u64, 377, 265},
0040 { ARM::BI__builtin_arm_cde_vcx1qa_m_u8, 390, 265},
0041 { ARM::BI__builtin_arm_cde_vcx1qa_s16, 402, 236},
0042 { ARM::BI__builtin_arm_cde_vcx1qa_s32, 413, 236},
0043 { ARM::BI__builtin_arm_cde_vcx1qa_s64, 424, 236},
0044 { ARM::BI__builtin_arm_cde_vcx1qa_s8, 435, 236},
0045 { ARM::BI__builtin_arm_cde_vcx1qa_u16, 445, 236},
0046 { ARM::BI__builtin_arm_cde_vcx1qa_u32, 456, 236},
0047 { ARM::BI__builtin_arm_cde_vcx1qa_u64, 467, 236},
0048 { ARM::BI__builtin_arm_cde_vcx1qa_u8, 478, 236},
0049 { ARM::BI__builtin_arm_cde_vcx2_u32, 488, -1},
0050 { ARM::BI__builtin_arm_cde_vcx2a_u32, 497, -1},
0051 { ARM::BI__builtin_arm_cde_vcx2d_u64, 507, -1},
0052 { ARM::BI__builtin_arm_cde_vcx2da_u64, 517, -1},
0053 { ARM::BI__builtin_arm_cde_vcx2q_f16, 534, 528},
0054 { ARM::BI__builtin_arm_cde_vcx2q_f32, 544, 528},
0055 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_f16, 567, 554},
0056 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_f32, 584, 554},
0057 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_s16, 601, 554},
0058 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_s32, 618, 554},
0059 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_s64, 635, 554},
0060 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_s8, 652, 554},
0061 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_u16, 668, 554},
0062 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_u32, 685, 554},
0063 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_u64, 702, 554},
0064 { ARM::BI__builtin_arm_cde_vcx2q_m_impl_u8, 719, 554},
0065 { ARM::BI__builtin_arm_cde_vcx2q_s16, 735, 528},
0066 { ARM::BI__builtin_arm_cde_vcx2q_s32, 745, 528},
0067 { ARM::BI__builtin_arm_cde_vcx2q_s64, 755, 528},
0068 { ARM::BI__builtin_arm_cde_vcx2q_s8, 765, 528},
0069 { ARM::BI__builtin_arm_cde_vcx2q_u16, 774, 528},
0070 { ARM::BI__builtin_arm_cde_vcx2q_u32, 784, 528},
0071 { ARM::BI__builtin_arm_cde_vcx2q_u64, 794, 528},
0072 { ARM::BI__builtin_arm_cde_vcx2q_u8, 804, 528},
0073 { ARM::BI__builtin_arm_cde_vcx2q_u8_f16, 813, 804},
0074 { ARM::BI__builtin_arm_cde_vcx2q_u8_f32, 826, 804},
0075 { ARM::BI__builtin_arm_cde_vcx2q_u8_s16, 839, 804},
0076 { ARM::BI__builtin_arm_cde_vcx2q_u8_s32, 852, 804},
0077 { ARM::BI__builtin_arm_cde_vcx2q_u8_s64, 865, 804},
0078 { ARM::BI__builtin_arm_cde_vcx2q_u8_s8, 878, 804},
0079 { ARM::BI__builtin_arm_cde_vcx2q_u8_u16, 890, 804},
0080 { ARM::BI__builtin_arm_cde_vcx2q_u8_u32, 903, 804},
0081 { ARM::BI__builtin_arm_cde_vcx2q_u8_u64, 916, 804},
0082 { ARM::BI__builtin_arm_cde_vcx2q_u8_u8, 929, 804},
0083 { ARM::BI__builtin_arm_cde_vcx2qa_impl_f16, 953, 941},
0084 { ARM::BI__builtin_arm_cde_vcx2qa_impl_f32, 969, 941},
0085 { ARM::BI__builtin_arm_cde_vcx2qa_impl_s16, 985, 941},
0086 { ARM::BI__builtin_arm_cde_vcx2qa_impl_s32, 1001, 941},
0087 { ARM::BI__builtin_arm_cde_vcx2qa_impl_s64, 1017, 941},
0088 { ARM::BI__builtin_arm_cde_vcx2qa_impl_s8, 1033, 941},
0089 { ARM::BI__builtin_arm_cde_vcx2qa_impl_u16, 1048, 941},
0090 { ARM::BI__builtin_arm_cde_vcx2qa_impl_u32, 1064, 941},
0091 { ARM::BI__builtin_arm_cde_vcx2qa_impl_u64, 1080, 941},
0092 { ARM::BI__builtin_arm_cde_vcx2qa_impl_u8, 1096, 941},
0093 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_f16, 1125, 1111},
0094 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_f32, 1143, 1111},
0095 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s16, 1161, 1111},
0096 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s32, 1179, 1111},
0097 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s64, 1197, 1111},
0098 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s8, 1215, 1111},
0099 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u16, 1232, 1111},
0100 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u32, 1250, 1111},
0101 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u64, 1268, 1111},
0102 { ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u8, 1286, 1111},
0103 { ARM::BI__builtin_arm_cde_vcx3_u32, 1303, -1},
0104 { ARM::BI__builtin_arm_cde_vcx3a_u32, 1312, -1},
0105 { ARM::BI__builtin_arm_cde_vcx3d_u64, 1322, -1},
0106 { ARM::BI__builtin_arm_cde_vcx3da_u64, 1332, -1},
0107 { ARM::BI__builtin_arm_cde_vcx3q_impl_f16, 1354, 1343},
0108 { ARM::BI__builtin_arm_cde_vcx3q_impl_f32, 1369, 1343},
0109 { ARM::BI__builtin_arm_cde_vcx3q_impl_s16, 1384, 1343},
0110 { ARM::BI__builtin_arm_cde_vcx3q_impl_s32, 1399, 1343},
0111 { ARM::BI__builtin_arm_cde_vcx3q_impl_s64, 1414, 1343},
0112 { ARM::BI__builtin_arm_cde_vcx3q_impl_s8, 1429, 1343},
0113 { ARM::BI__builtin_arm_cde_vcx3q_impl_u16, 1443, 1343},
0114 { ARM::BI__builtin_arm_cde_vcx3q_impl_u32, 1458, 1343},
0115 { ARM::BI__builtin_arm_cde_vcx3q_impl_u64, 1473, 1343},
0116 { ARM::BI__builtin_arm_cde_vcx3q_impl_u8, 1488, 1343},
0117 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_f16, 1515, 1502},
0118 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_f32, 1532, 1502},
0119 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_s16, 1549, 1502},
0120 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_s32, 1566, 1502},
0121 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_s64, 1583, 1502},
0122 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_s8, 1600, 1502},
0123 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_u16, 1616, 1502},
0124 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_u32, 1633, 1502},
0125 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_u64, 1650, 1502},
0126 { ARM::BI__builtin_arm_cde_vcx3q_m_impl_u8, 1667, 1502},
0127 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_f16, 1697, 1683},
0128 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_f32, 1715, 1683},
0129 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s16, 1733, 1683},
0130 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s32, 1751, 1683},
0131 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s64, 1769, 1683},
0132 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s8, 1787, 1683},
0133 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u16, 1804, 1683},
0134 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u32, 1822, 1683},
0135 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u64, 1840, 1683},
0136 { ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u8, 1858, 1683},
0137 { ARM::BI__builtin_arm_cde_vcx3qa_impl_f16, 1887, 1875},
0138 { ARM::BI__builtin_arm_cde_vcx3qa_impl_f32, 1903, 1875},
0139 { ARM::BI__builtin_arm_cde_vcx3qa_impl_s16, 1919, 1875},
0140 { ARM::BI__builtin_arm_cde_vcx3qa_impl_s32, 1935, 1875},
0141 { ARM::BI__builtin_arm_cde_vcx3qa_impl_s64, 1951, 1875},
0142 { ARM::BI__builtin_arm_cde_vcx3qa_impl_s8, 1967, 1875},
0143 { ARM::BI__builtin_arm_cde_vcx3qa_impl_u16, 1982, 1875},
0144 { ARM::BI__builtin_arm_cde_vcx3qa_impl_u32, 1998, 1875},
0145 { ARM::BI__builtin_arm_cde_vcx3qa_impl_u64, 2014, 1875},
0146 { ARM::BI__builtin_arm_cde_vcx3qa_impl_u8, 2030, 1875},
0147 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_f16, 2059, 2045},
0148 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_f32, 2077, 2045},
0149 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s16, 2095, 2045},
0150 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s32, 2113, 2045},
0151 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s64, 2131, 2045},
0152 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s8, 2149, 2045},
0153 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u16, 2166, 2045},
0154 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u32, 2184, 2045},
0155 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u64, 2202, 2045},
0156 { ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u8, 2220, 2045},
0157 { ARM::BI__builtin_arm_cde_vreinterpretq_u8_u8, 2254, 2237},
0158 };
0159
0160 ArrayRef<IntrinToName> Map(MapData);
0161
0162 static const char IntrinNames[] = {
0163 "\000cx1\000cx1a\000cx1d\000cx1da\000cx2\000cx2a\000cx2d\000cx2da\000cx3"
0164 "\000cx3a\000cx3d\000cx3da\000vcx1_u32\000vcx1a_u32\000vcx1d_u64\000vcx1"
0165 "da_u64\000vcx1q_m\000vcx1q_m_f16\000vcx1q_m_f32\000vcx1q_m_s16\000vcx1q"
0166 "_m_s32\000vcx1q_m_s64\000vcx1q_m_s8\000vcx1q_m_u16\000vcx1q_m_u32\000vc"
0167 "x1q_m_u64\000vcx1q_m_u8\000vcx1q_u8\000vcx1qa\000vcx1qa_f16\000vcx1qa_f"
0168 "32\000vcx1qa_m\000vcx1qa_m_f16\000vcx1qa_m_f32\000vcx1qa_m_s16\000vcx1q"
0169 "a_m_s32\000vcx1qa_m_s64\000vcx1qa_m_s8\000vcx1qa_m_u16\000vcx1qa_m_u32\000"
0170 "vcx1qa_m_u64\000vcx1qa_m_u8\000vcx1qa_s16\000vcx1qa_s32\000vcx1qa_s64\000"
0171 "vcx1qa_s8\000vcx1qa_u16\000vcx1qa_u32\000vcx1qa_u64\000vcx1qa_u8\000vcx"
0172 "2_u32\000vcx2a_u32\000vcx2d_u64\000vcx2da_u64\000vcx2q\000vcx2q_f16\000"
0173 "vcx2q_f32\000vcx2q_m_impl\000vcx2q_m_impl_f16\000vcx2q_m_impl_f32\000vc"
0174 "x2q_m_impl_s16\000vcx2q_m_impl_s32\000vcx2q_m_impl_s64\000vcx2q_m_impl_"
0175 "s8\000vcx2q_m_impl_u16\000vcx2q_m_impl_u32\000vcx2q_m_impl_u64\000vcx2q"
0176 "_m_impl_u8\000vcx2q_s16\000vcx2q_s32\000vcx2q_s64\000vcx2q_s8\000vcx2q_"
0177 "u16\000vcx2q_u32\000vcx2q_u64\000vcx2q_u8\000vcx2q_u8_f16\000vcx2q_u8_f"
0178 "32\000vcx2q_u8_s16\000vcx2q_u8_s32\000vcx2q_u8_s64\000vcx2q_u8_s8\000vc"
0179 "x2q_u8_u16\000vcx2q_u8_u32\000vcx2q_u8_u64\000vcx2q_u8_u8\000vcx2qa_imp"
0180 "l\000vcx2qa_impl_f16\000vcx2qa_impl_f32\000vcx2qa_impl_s16\000vcx2qa_im"
0181 "pl_s32\000vcx2qa_impl_s64\000vcx2qa_impl_s8\000vcx2qa_impl_u16\000vcx2q"
0182 "a_impl_u32\000vcx2qa_impl_u64\000vcx2qa_impl_u8\000vcx2qa_m_impl\000vcx"
0183 "2qa_m_impl_f16\000vcx2qa_m_impl_f32\000vcx2qa_m_impl_s16\000vcx2qa_m_im"
0184 "pl_s32\000vcx2qa_m_impl_s64\000vcx2qa_m_impl_s8\000vcx2qa_m_impl_u16\000"
0185 "vcx2qa_m_impl_u32\000vcx2qa_m_impl_u64\000vcx2qa_m_impl_u8\000vcx3_u32\000"
0186 "vcx3a_u32\000vcx3d_u64\000vcx3da_u64\000vcx3q_impl\000vcx3q_impl_f16\000"
0187 "vcx3q_impl_f32\000vcx3q_impl_s16\000vcx3q_impl_s32\000vcx3q_impl_s64\000"
0188 "vcx3q_impl_s8\000vcx3q_impl_u16\000vcx3q_impl_u32\000vcx3q_impl_u64\000"
0189 "vcx3q_impl_u8\000vcx3q_m_impl\000vcx3q_m_impl_f16\000vcx3q_m_impl_f32\000"
0190 "vcx3q_m_impl_s16\000vcx3q_m_impl_s32\000vcx3q_m_impl_s64\000vcx3q_m_imp"
0191 "l_s8\000vcx3q_m_impl_u16\000vcx3q_m_impl_u32\000vcx3q_m_impl_u64\000vcx"
0192 "3q_m_impl_u8\000vcx3q_u8_impl\000vcx3q_u8_impl_f16\000vcx3q_u8_impl_f32"
0193 "\000vcx3q_u8_impl_s16\000vcx3q_u8_impl_s32\000vcx3q_u8_impl_s64\000vcx3"
0194 "q_u8_impl_s8\000vcx3q_u8_impl_u16\000vcx3q_u8_impl_u32\000vcx3q_u8_impl"
0195 "_u64\000vcx3q_u8_impl_u8\000vcx3qa_impl\000vcx3qa_impl_f16\000vcx3qa_im"
0196 "pl_f32\000vcx3qa_impl_s16\000vcx3qa_impl_s32\000vcx3qa_impl_s64\000vcx3"
0197 "qa_impl_s8\000vcx3qa_impl_u16\000vcx3qa_impl_u32\000vcx3qa_impl_u64\000"
0198 "vcx3qa_impl_u8\000vcx3qa_m_impl\000vcx3qa_m_impl_f16\000vcx3qa_m_impl_f"
0199 "32\000vcx3qa_m_impl_s16\000vcx3qa_m_impl_s32\000vcx3qa_m_impl_s64\000vc"
0200 "x3qa_m_impl_s8\000vcx3qa_m_impl_u16\000vcx3qa_m_impl_u32\000vcx3qa_m_im"
0201 "pl_u64\000vcx3qa_m_impl_u8\000vreinterpretq_u8\000vreinterpretq_u8_u8\000"};
0202
