Warning, /include/clang/Basic/BuiltinsPPC.def is written in an unsupported language. File is not indexed.
0001 //===--- BuiltinsPPC.def - PowerPC Builtin function database ----*- C++ -*-===//
0002 //
0003 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
0004 // See https://llvm.org/LICENSE.txt for license information.
0005 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
0006 //
0007 //===----------------------------------------------------------------------===//
0008 //
0009 // This file defines the PowerPC-specific builtin function database. Users of
0010 // this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to
0011 // make use of this information. The latter is used for builtins requiring
0012 // custom code generation and checking.
0013 //
0014 //===----------------------------------------------------------------------===//
0015
0016 // FIXME: this needs to be the full list supported by GCC. Right now, I'm just
0017 // adding stuff on demand.
0018
0019 // The format of this database matches clang/Basic/Builtins.def except for the
0020 // MMA builtins that are using their own format documented below.
0021
0022 #ifndef BUILTIN
0023 #define BUILTIN(ID, TYPE, ATTRS)
0024 #endif
0025
0026 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
0027 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
0028 #endif
0029
0030 #ifndef CUSTOM_BUILTIN
0031 #define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \
0032 TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE)
0033 #endif
0034
0035 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \
0036 CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE)
0037
0038 // GCC predefined macros to rename builtins, undef them to keep original names.
0039 #if defined(__GNUC__) && !defined(__clang__)
0040 #undef __builtin_vsx_xvnmaddadp
0041 #undef __builtin_vsx_xvnmaddasp
0042 #undef __builtin_vsx_xvmsubasp
0043 #undef __builtin_vsx_xvmsubadp
0044 #undef __builtin_vsx_xvmaddadp
0045 #undef __builtin_vsx_xvnmsubasp
0046 #undef __builtin_vsx_xvnmsubadp
0047 #undef __builtin_vsx_xvmaddasp
0048 #endif
0049
0050 // XL Compatibility built-ins
0051 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
0052 BUILTIN(__builtin_ppc_poppar4, "iUi", "")
0053 BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
0054 BUILTIN(__builtin_ppc_eieio, "v", "")
0055 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
0056 BUILTIN(__builtin_ppc_isync, "v", "")
0057 BUILTIN(__builtin_ppc_lwsync, "v", "")
0058 BUILTIN(__builtin_ppc_iospace_lwsync, "v", "")
0059 BUILTIN(__builtin_ppc_sync, "v", "")
0060 BUILTIN(__builtin_ppc_iospace_sync, "v", "")
0061 BUILTIN(__builtin_ppc_dcbfl, "vvC*", "")
0062 BUILTIN(__builtin_ppc_dcbflp, "vvC*", "")
0063 BUILTIN(__builtin_ppc_dcbst, "vvC*", "")
0064 BUILTIN(__builtin_ppc_dcbt, "vv*", "")
0065 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
0066 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
0067 TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions")
0068 BUILTIN(__builtin_ppc_fric, "dd", "")
0069 BUILTIN(__builtin_ppc_frim, "dd", "")
0070 BUILTIN(__builtin_ppc_frims, "ff", "")
0071 BUILTIN(__builtin_ppc_frin, "dd", "")
0072 BUILTIN(__builtin_ppc_frins, "ff", "")
0073 BUILTIN(__builtin_ppc_frip, "dd", "")
0074 BUILTIN(__builtin_ppc_frips, "ff", "")
0075 BUILTIN(__builtin_ppc_friz, "dd", "")
0076 BUILTIN(__builtin_ppc_frizs, "ff", "")
0077 BUILTIN(__builtin_ppc_fsel, "dddd", "")
0078 BUILTIN(__builtin_ppc_fsels, "ffff", "")
0079 BUILTIN(__builtin_ppc_frsqrte, "dd", "")
0080 BUILTIN(__builtin_ppc_frsqrtes, "ff", "")
0081 BUILTIN(__builtin_ppc_fsqrt, "dd", "")
0082 BUILTIN(__builtin_ppc_fsqrts, "ff", "")
0083 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
0084 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
0085 BUILTIN(__builtin_ppc_fetch_and_add, "iiD*i", "")
0086 BUILTIN(__builtin_ppc_fetch_and_addlp, "LiLiD*Li", "")
0087 BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui", "")
0088 BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi", "")
0089 BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "")
0090 BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "")
0091 BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
0092 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
0093 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
0094 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
0095 TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions")
0096 TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*", "", "isa-v207-instructions")
0097 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
0098 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
0099 TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s", "", "isa-v207-instructions")
0100 TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i", "", "isa-v207-instructions")
0101 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
0102 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
0103 BUILTIN(__builtin_ppc_trap, "vi", "")
0104 BUILTIN(__builtin_ppc_trapd, "vLi", "")
0105 BUILTIN(__builtin_ppc_fcfid, "dd", "")
0106 BUILTIN(__builtin_ppc_fcfud, "dd", "")
0107 BUILTIN(__builtin_ppc_fctid, "dd", "")
0108 BUILTIN(__builtin_ppc_fctidz, "dd", "")
0109 BUILTIN(__builtin_ppc_fctiw, "dd", "")
0110 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
0111 BUILTIN(__builtin_ppc_fctudz, "dd", "")
0112 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
0113
0114 // fence builtin prevents all instructions moved across it
0115 BUILTIN(__builtin_ppc_fence, "v", "")
0116
0117 BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "")
0118 BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
0119 BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc")
0120 BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
0121 TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", "isa-v30-instructions,vsx")
0122 TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "", "isa-v30-instructions,vsx")
0123 TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "", "isa-v30-instructions,vsx")
0124 TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "", "isa-v30-instructions,vsx")
0125 TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi", "t", "isa-v30-instructions,vsx")
0126 BUILTIN(__builtin_ppc_swdiv, "ddd", "")
0127 BUILTIN(__builtin_ppc_swdivs, "fff", "")
0128 // Compare
0129 TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "", "isa-v30-instructions")
0130 TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii", "", "isa-v30-instructions")
0131 TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "", "isa-v30-instructions")
0132 BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "")
0133 // Multiply
0134 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
0135 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
0136 BUILTIN(__builtin_ppc_mulhw, "iii", "")
0137 BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
0138 TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "", "isa-v30-instructions")
0139 TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "",
0140 "isa-v30-instructions")
0141 TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "", "isa-v30-instructions")
0142 // Rotate
0143 BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
0144 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
0145 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
0146 // load
0147 BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
0148 BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
0149 TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "", "isa-v206-instructions")
0150 // store
0151 BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
0152 BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
0153 TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions")
0154 TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector")
0155 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
0156 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
0157 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
0158 BUILTIN(__builtin_ppc_mffs, "d", "")
0159 TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
0160 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
0161 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
0162 BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "")
0163 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")
0164 BUILTIN(__builtin_ppc_fmsub, "dddd", "")
0165 BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
0166 BUILTIN(__builtin_ppc_fnmadd, "dddd", "")
0167 BUILTIN(__builtin_ppc_fnmadds, "ffff", "")
0168 BUILTIN(__builtin_ppc_fnmsub, "dddd", "")
0169 BUILTIN(__builtin_ppc_fnmsubs, "ffff", "")
0170 BUILTIN(__builtin_ppc_fre, "dd", "")
0171 BUILTIN(__builtin_ppc_fres, "ff", "")
0172 BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
0173 BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
0174 BUILTIN(__builtin_ppc_mftbu, "Ui", "")
0175 BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
0176 BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
0177 BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
0178 BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
0179 BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
0180 TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "", "isa-v30-instructions")
0181 // select
0182 BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t")
0183 BUILTIN(__builtin_ppc_maxfl, "dddd.", "t")
0184 BUILTIN(__builtin_ppc_maxfs, "ffff.", "t")
0185 BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t")
0186 BUILTIN(__builtin_ppc_minfl, "dddd.", "t")
0187 BUILTIN(__builtin_ppc_minfs, "ffff.", "t")
0188 // Floating Negative Absolute Value
0189 BUILTIN(__builtin_ppc_fnabs, "dd", "")
0190 BUILTIN(__builtin_ppc_fnabss, "ff", "")
0191
0192 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
0193
0194 // This is just a placeholder, the types and attributes are wrong.
0195 TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "", "altivec")
0196
0197 TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "", "altivec")
0198 TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "", "altivec")
0199 TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "", "altivec")
0200 TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "", "altivec")
0201 TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "", "altivec")
0202 TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "", "altivec")
0203 TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
0204 "power8-vector")
0205 TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi", "",
0206 "power8-vector")
0207 TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
0208 "power8-vector")
0209 TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc", "",
0210 "power8-vector")
0211 TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc", "",
0212 "power8-vector")
0213 TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc", "",
0214 "power8-vector")
0215 TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc", "",
0216 "power8-vector")
0217
0218 TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "", "altivec")
0219 TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "", "altivec")
0220 TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "", "altivec")
0221 TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "", "altivec")
0222 TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "", "altivec")
0223 TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "", "altivec")
0224 TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
0225 "power8-vector")
0226 TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi", "",
0227 "power8-vector")
0228 TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
0229 "power8-vector")
0230 TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc", "",
0231 "power8-vector")
0232 TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc", "",
0233 "power8-vector")
0234 TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc", "",
0235 "power8-vector")
0236 TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc", "",
0237 "power8-vector")
0238
0239 TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "", "altivec")
0240 TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "", "altivec")
0241 TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "", "altivec")
0242 TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "", "altivec")
0243 TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "", "altivec")
0244 TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "", "altivec")
0245
0246 TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "", "altivec")
0247
0248 TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "", "altivec")
0249 TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "", "altivec")
0250 TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "", "altivec")
0251 TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "", "altivec")
0252
0253 TARGET_BUILTIN(__builtin_altivec_dss, "vUIi", "", "altivec")
0254 TARGET_BUILTIN(__builtin_altivec_dssall, "v", "", "altivec")
0255 TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "", "altivec")
0256 TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "", "altivec")
0257 TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "", "altivec")
0258 TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "", "altivec")
0259
0260 TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "", "altivec")
0261
0262 TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "", "altivec")
0263
0264 TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "", "altivec")
0265 TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "", "altivec")
0266 TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "", "altivec")
0267 TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "", "altivec")
0268 TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "", "altivec")
0269
0270 TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "", "altivec")
0271
0272 TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "", "altivec")
0273 TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "", "altivec")
0274
0275 TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "", "altivec")
0276 TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "", "altivec")
0277 TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "", "altivec")
0278
0279 TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "", "altivec")
0280 TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "", "altivec")
0281 TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "", "altivec")
0282 TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "", "altivec")
0283 TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "", "altivec")
0284 TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "", "altivec")
0285
0286 TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "", "altivec")
0287 TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "", "altivec")
0288 TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "", "altivec")
0289 TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "", "altivec")
0290 TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "", "power8-vector")
0291 TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "", "power8-vector")
0292 TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "", "altivec")
0293 TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "", "altivec")
0294 TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "", "altivec")
0295 TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "", "altivec")
0296 TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "", "power8-vector")
0297 TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "", "power8-vector")
0298 TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "",
0299 "power10-vector")
0300 TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "",
0301 "power10-vector")
0302 TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "",
0303 "power10-vector")
0304 TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "",
0305 "power10-vector")
0306 TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "",
0307 "power10-vector")
0308
0309 TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "", "altivec")
0310
0311 TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "", "altivec")
0312 TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "", "altivec")
0313 TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "", "altivec")
0314 TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "", "altivec")
0315 TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "", "altivec")
0316 TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "", "altivec")
0317 TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "", "altivec")
0318 TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "",
0319 "power8-vector")
0320 TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "",
0321 "power8-vector")
0322 TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "",
0323 "power8-vector")
0324 TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "",
0325 "power8-vector")
0326
0327 TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "", "altivec")
0328
0329 TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "", "altivec")
0330 TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "", "altivec")
0331 TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "", "altivec")
0332 TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "", "altivec")
0333 TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "", "altivec")
0334
0335 TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "", "altivec")
0336
0337 TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "", "altivec")
0338
0339 TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "", "altivec")
0340 TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "", "altivec")
0341 TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "", "altivec")
0342 TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "",
0343 "power8-vector")
0344 TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "", "altivec")
0345
0346 TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "", "power9-vector")
0347 TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "", "power9-vector")
0348 TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "", "power9-vector")
0349
0350 TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "", "power9-vector")
0351 TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "", "power9-vector")
0352 TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "", "power9-vector")
0353
0354 TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "", "altivec")
0355 TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "", "altivec")
0356 TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "", "altivec")
0357 TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "", "altivec")
0358 TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "", "altivec")
0359 TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "", "altivec")
0360 TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "",
0361 "power8-vector")
0362 TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "",
0363 "power8-vector")
0364 TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "", "altivec")
0365
0366 // P10 Vector compare builtins.
0367 TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "",
0368 "power10-vector")
0369 TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "",
0370 "power10-vector")
0371 TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "",
0372 "power10-vector")
0373 TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "", "altivec")
0374 TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "",
0375 "power10-vector")
0376 TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "",
0377 "power10-vector")
0378
0379 TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "", "altivec")
0380 TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "", "altivec")
0381 TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "", "altivec")
0382 TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "", "altivec")
0383 TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "", "altivec")
0384 TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "", "altivec")
0385 TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "", "power8-vector")
0386 TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "",
0387 "power8-vector")
0388 TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "", "altivec")
0389
0390 TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us", "", "altivec")
0391
0392 TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "", "altivec")
0393 TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "", "altivec")
0394 TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "", "altivec")
0395 TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "", "altivec")
0396 TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "", "altivec")
0397 TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "", "altivec")
0398 TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "", "power8-vector")
0399 TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "",
0400 "power8-vector")
0401 TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "", "altivec")
0402
0403 TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i", "", "altivec")
0404
0405 TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "", "altivec")
0406
0407 TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "", "altivec")
0408 TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "", "altivec")
0409 TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "", "altivec")
0410 TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "", "power8-vector")
0411
0412 TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "", "altivec")
0413
0414 TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "", "altivec")
0415 TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "", "altivec")
0416
0417 TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "", "altivec")
0418 TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "", "altivec")
0419 TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "", "altivec")
0420
0421 TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "", "altivec")
0422 TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "", "altivec")
0423
0424 TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "", "altivec")
0425
0426 TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "", "altivec")
0427
0428 TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "", "altivec")
0429
0430 TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "", "altivec")
0431 TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "", "altivec")
0432 TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "", "altivec")
0433
0434 TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "", "altivec")
0435
0436 TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "", "altivec")
0437
0438 TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "", "altivec")
0439
0440 TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "", "altivec")
0441 TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "", "altivec")
0442 TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "", "altivec")
0443 TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "", "power8-vector")
0444
0445 TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "", "altivec")
0446 TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "", "altivec")
0447 TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "", "altivec")
0448 TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "", "power8-vector")
0449
0450 TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "", "altivec")
0451
0452 TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "", "altivec")
0453
0454 TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "", "altivec")
0455 TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "", "altivec")
0456 TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "", "altivec")
0457 TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "", "vsx")
0458 TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "", "altivec")
0459
0460 TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "", "power9-vector")
0461 TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "", "power9-vector")
0462 TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector")
0463 TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "vsx")
0464
0465 TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "", "altivec")
0466 TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "", "altivec")
0467 TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "", "altivec")
0468 TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "", "altivec")
0469 TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "", "altivec")
0470 TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "", "altivec")
0471 TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "", "vsx")
0472 TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "", "vsx")
0473 TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "", "altivec")
0474
0475 TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "", "power8-vector")
0476 TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "",
0477 "power8-vector")
0478 TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "",
0479 "power9-vector")
0480
0481 // P8 Crypto built-ins.
0482 TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "",
0483 "power8-vector")
0484 TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "",
0485 "power8-vector")
0486 TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "",
0487 "power8-vector")
0488 TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "",
0489 "power8-vector")
0490 TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "",
0491 "power8-vector")
0492 TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "",
0493 "power8-vector")
0494 TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "",
0495 "power8-vector")
0496 TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "",
0497 "power8-vector")
0498 TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "",
0499 "power8-vector")
0500 TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "",
0501 "power8-vector")
0502 TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "",
0503 "power8-vector")
0504 TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "",
0505 "power8-vector")
0506 TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "",
0507 "power8-vector")
0508
0509 TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "", "power8-vector")
0510 TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "", "power8-vector")
0511 TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "", "power8-vector")
0512 TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "", "power8-vector")
0513 TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "", "power9-vector")
0514 TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector")
0515 TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
0516 TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
0517
0518 // P7 BCD builtins.
0519 TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
0520 TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
0521 TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions")
0522
0523 // P7 XL Compat BCD builtins.
0524 TARGET_BUILTIN(__builtin_ppc_cdtbcd, "LLiLLi", "", "isa-v206-instructions")
0525 TARGET_BUILTIN(__builtin_ppc_cbcdtd, "LLiLLi", "", "isa-v206-instructions")
0526 TARGET_BUILTIN(__builtin_ppc_addg6s, "LLiLLiLLi", "", "isa-v206-instructions")
0527
0528 // P8 BCD builtins.
0529 TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "",
0530 "isa-v207-instructions")
0531 TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "",
0532 "isa-v207-instructions")
0533 TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "",
0534 "isa-v207-instructions")
0535 TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "",
0536 "isa-v207-instructions")
0537
0538 TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector")
0539 TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector")
0540 TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector")
0541 TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "", "power9-vector")
0542 TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "", "power9-vector")
0543
0544 // Absolute difference built-ins
0545 TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "",
0546 "power9-vector")
0547 TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "power9-vector")
0548 TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "power9-vector")
0549
0550 // P9 Shift built-ins.
0551 TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "", "power9-vector")
0552 TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "", "power9-vector")
0553
0554 // P9 Vector rotate built-ins
0555 TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "",
0556 "power9-vector")
0557 TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "",
0558 "power9-vector")
0559 TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "", "power9-vector")
0560 TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "",
0561 "power9-vector")
0562
0563 // P9 Vector extend sign builtins.
0564 TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "", "power9-vector")
0565 TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "", "power9-vector")
0566 TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "", "power9-vector")
0567 TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "", "power9-vector")
0568 TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "", "power9-vector")
0569
0570 // P10 Vector extend sign builtins.
0571 TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "",
0572 "power10-vector")
0573
0574 // P10 Vector Extract with Mask built-ins.
0575 TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "", "power10-vector")
0576 TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "", "power10-vector")
0577 TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "", "power10-vector")
0578 TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "", "power10-vector")
0579 TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "", "power10-vector")
0580
0581 // P10 Vector Divide Extended built-ins.
0582 TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "", "power10-vector")
0583 TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "", "power10-vector")
0584 TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "",
0585 "power10-vector")
0586 TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "",
0587 "power10-vector")
0588 TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "",
0589 "power10-vector")
0590 TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "",
0591 "power10-vector")
0592
0593 // P10 Vector Multiply High built-ins.
0594 TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "", "power10-vector")
0595 TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "", "power10-vector")
0596 TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "",
0597 "power10-vector")
0598 TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "",
0599 "power10-vector")
0600
0601 // P10 Vector Expand with Mask built-ins.
0602 TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector")
0603 TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "", "power10-vector")
0604 TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "", "power10-vector")
0605 TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "",
0606 "power10-vector")
0607 TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "",
0608 "power10-vector")
0609
0610 // P10 Vector Count with Mask built-ins.
0611 TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "", "power10-vector")
0612 TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "", "power10-vector")
0613 TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "", "power10-vector")
0614 TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "", "power10-vector")
0615
0616 // P10 Move to VSR with Mask built-ins.
0617 TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "", "power10-vector")
0618 TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "", "power10-vector")
0619 TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "", "power10-vector")
0620 TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "", "power10-vector")
0621 TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "", "power10-vector")
0622
0623 // P10 Vector Parallel Bits built-ins.
0624 TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "",
0625 "power10-vector")
0626 TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "",
0627 "power10-vector")
0628
0629 // P10 Vector String Isolate Built-ins.
0630 TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "", "power10-vector")
0631 TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "", "power10-vector")
0632 TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "", "power10-vector")
0633 TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "", "power10-vector")
0634 TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "", "power10-vector")
0635 TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "", "power10-vector")
0636 TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "", "power10-vector")
0637 TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "", "power10-vector")
0638
0639 // P10 Vector Centrifuge built-in.
0640 TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "",
0641 "power10-vector")
0642
0643 // P10 Vector Gather Every N-th Bit built-in.
0644 TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "", "power10-vector")
0645
0646 // P10 Vector Clear Bytes built-ins.
0647 TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "", "power10-vector")
0648 TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "", "power10-vector")
0649
0650 // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins.
0651 TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "",
0652 "power10-vector")
0653 TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "",
0654 "power10-vector")
0655
0656 // P10 Vector Shift built-ins.
0657 TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "",
0658 "power10-vector")
0659 TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "",
0660 "power10-vector")
0661
0662 // P10 Vector Insert built-ins.
0663 TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "",
0664 "power10-vector")
0665 TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "",
0666 "power10-vector")
0667 TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "", "power10-vector")
0668 TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "", "power10-vector")
0669 TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "", "power10-vector")
0670 TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "", "power10-vector")
0671 TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "",
0672 "power10-vector")
0673 TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "",
0674 "power10-vector")
0675 TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "",
0676 "power10-vector")
0677 TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "",
0678 "power10-vector")
0679 TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "",
0680 "power10-vector")
0681 TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "",
0682 "power10-vector")
0683 TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "",
0684 "power10-vector")
0685 TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "",
0686 "power10-vector")
0687 TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "", "power10-vector")
0688 TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "",
0689 "power10-vector")
0690 TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "",
0691 "power10-vector")
0692 TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "",
0693 "power10-vector")
0694
0695 // P10 Vector Extract built-ins.
0696 TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "",
0697 "power10-vector")
0698 TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "",
0699 "power10-vector")
0700 TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "",
0701 "power10-vector")
0702 TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "",
0703 "power10-vector")
0704 TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "",
0705 "power10-vector")
0706 TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "",
0707 "power10-vector")
0708 TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "",
0709 "power10-vector")
0710 TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "",
0711 "power10-vector")
0712
0713 // P10 Vector rotate built-ins.
0714 TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
0715 "power10-vector")
0716 TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "",
0717 "power10-vector")
0718
0719 // VSX built-ins.
0720
0721 TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "", "vsx")
0722 TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "", "vsx")
0723 TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "", "vsx")
0724 TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "", "vsx")
0725
0726 TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "", "vsx")
0727 TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "", "vsx")
0728 TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "", "vsx")
0729 TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "", "vsx")
0730
0731 TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "", "power9-vector")
0732 TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "", "power9-vector")
0733 TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "", "power9-vector")
0734 TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "", "power9-vector")
0735 TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "", "isa-v207-instructions")
0736 TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "", "isa-v207-instructions")
0737
0738 TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "", "vsx")
0739 TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "", "vsx")
0740 TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "", "vsx")
0741
0742 TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "", "vsx")
0743 TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "", "vsx")
0744 TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd", "", "vsx")
0745
0746 TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "", "vsx")
0747 TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "", "vsx")
0748
0749 TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "", "vsx")
0750 TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "", "vsx")
0751
0752 TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "", "vsx")
0753 TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "", "vsx")
0754
0755 TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "", "vsx")
0756 TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "", "vsx")
0757
0758 TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "", "vsx")
0759 TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "", "vsx")
0760
0761 TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "", "vsx")
0762 TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "", "vsx")
0763
0764 TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "", "vsx")
0765 TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "", "vsx")
0766
0767 TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "", "vsx")
0768 TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "", "vsx")
0769
0770 TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "", "vsx")
0771 TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "", "vsx")
0772
0773 TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "", "vsx")
0774 TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "", "vsx")
0775
0776 TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "", "vsx")
0777 TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "", "vsx")
0778
0779 TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "", "vsx")
0780 TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "", "vsx")
0781
0782 TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "", "vsx")
0783 TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "", "vsx")
0784
0785 TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "", "vsx")
0786 TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "", "vsx")
0787
0788 TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "", "vsx")
0789 TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "", "vsx")
0790
0791 TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "", "vsx")
0792 TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "", "vsx")
0793
0794 TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "", "vsx")
0795 TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "", "vsx")
0796
0797 TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "", "vsx")
0798 TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "", "vsx")
0799
0800 TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "", "vsx")
0801 TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "", "vsx")
0802
0803 TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "", "vsx")
0804 TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "", "vsx")
0805
0806 TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "", "power8-vector")
0807
0808 TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "", "vsx")
0809 TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "", "vsx")
0810
0811 TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "", "vsx")
0812 TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "", "vsx")
0813
0814 TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "", "power10-vector")
0815 TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "", "power10-vector")
0816 TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "", "power10-vector")
0817 TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "", "power10-vector")
0818
0819 // vector Insert/Extract exponent/significand builtins
0820 TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "", "power9-vector")
0821 TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "", "power9-vector")
0822 TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "", "power9-vector")
0823 TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "", "power9-vector")
0824 TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "", "power9-vector")
0825 TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "", "power9-vector")
0826
0827 // Conversion builtins
0828 TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "", "vsx")
0829 TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "", "vsx")
0830 TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "", "vsx")
0831 TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "", "vsx")
0832 TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "", "vsx")
0833 TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "", "vsx")
0834 TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "", "vsx")
0835 TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "", "vsx")
0836 TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "", "vsx")
0837 TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "", "vsx")
0838
0839 TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "", "power9-vector")
0840 TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "", "power9-vector")
0841
0842 TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector")
0843 TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "power10-vector")
0844
0845 // Vector Test Data Class builtins
0846 TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "", "power9-vector")
0847 TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "", "power9-vector")
0848
0849 TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "", "vsx")
0850 TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "", "vsx")
0851
0852 TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v.", "t", "vsx")
0853 TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v.", "t", "vsx")
0854
0855 TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "",
0856 "power10-vector")
0857
0858 TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "", "power10-vector")
0859
0860 TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "", "vsx")
0861 TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "", "vsx")
0862 TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "", "vsx")
0863 TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "", "vsx")
0864
0865 // P10 Vector Permute Extended built-in.
0866 TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "",
0867 "power10-vector")
0868
0869 // P10 Vector Blend built-ins.
0870 TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "",
0871 "power10-vector")
0872 TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "",
0873 "power10-vector")
0874 TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "",
0875 "power10-vector")
0876 TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "",
0877 "power10-vector")
0878
0879 // Float 128 built-ins
0880 TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "", "float128")
0881 TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "", "float128")
0882 TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "", "float128")
0883 TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "", "float128")
0884 TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "", "float128")
0885 TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "", "float128")
0886 TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "", "float128")
0887 TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "", "float128")
0888 TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "", "float128")
0889
0890 // Fastmath by default builtins
0891 BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f", "")
0892 BUILTIN(__builtin_ppc_rsqrtd, "V2dV2d", "")
0893 BUILTIN(__builtin_ppc_recipdivf, "V4fV4fV4f", "")
0894 BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d", "")
0895
0896 // HTM builtins
0897 TARGET_BUILTIN(__builtin_tbegin, "UiUIi", "", "htm")
0898 TARGET_BUILTIN(__builtin_tend, "UiUIi", "", "htm")
0899
0900 TARGET_BUILTIN(__builtin_tabort, "UiUi", "", "htm")
0901 TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi", "", "htm")
0902 TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii", "", "htm")
0903 TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi", "", "htm")
0904 TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii", "", "htm")
0905
0906 TARGET_BUILTIN(__builtin_tcheck, "Ui", "", "htm")
0907 TARGET_BUILTIN(__builtin_treclaim, "UiUi", "", "htm")
0908 TARGET_BUILTIN(__builtin_trechkpt, "Ui", "", "htm")
0909 TARGET_BUILTIN(__builtin_tsr, "UiUi", "", "htm")
0910
0911 TARGET_BUILTIN(__builtin_tendall, "Ui", "", "htm")
0912 TARGET_BUILTIN(__builtin_tresume, "Ui", "", "htm")
0913 TARGET_BUILTIN(__builtin_tsuspend, "Ui", "", "htm")
0914
0915 TARGET_BUILTIN(__builtin_get_texasr, "LUi", "c", "htm")
0916 TARGET_BUILTIN(__builtin_get_texasru, "LUi", "c", "htm")
0917 TARGET_BUILTIN(__builtin_get_tfhar, "LUi", "c", "htm")
0918 TARGET_BUILTIN(__builtin_get_tfiar, "LUi", "c", "htm")
0919
0920 TARGET_BUILTIN(__builtin_set_texasr, "vLUi", "c", "htm")
0921 TARGET_BUILTIN(__builtin_set_texasru, "vLUi", "c", "htm")
0922 TARGET_BUILTIN(__builtin_set_tfhar, "vLUi", "c", "htm")
0923 TARGET_BUILTIN(__builtin_set_tfiar, "vLUi", "c", "htm")
0924
0925 TARGET_BUILTIN(__builtin_ttest, "LUi", "", "htm")
0926
0927 // Scalar built-ins
0928 TARGET_BUILTIN(__builtin_divwe, "SiSiSi", "", "extdiv")
0929 TARGET_BUILTIN(__builtin_divweu, "UiUiUi", "", "extdiv")
0930 TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "", "extdiv")
0931 TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "", "extdiv")
0932 TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "", "bpermd")
0933 TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "", "isa-v31-instructions")
0934 TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi", "", "isa-v31-instructions")
0935 TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "", "isa-v31-instructions")
0936 TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "", "isa-v31-instructions")
0937 TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "", "isa-v31-instructions")
0938
0939 // Double-double (un)pack
0940 BUILTIN(__builtin_unpack_longdouble, "dLdIi", "")
0941 BUILTIN(__builtin_pack_longdouble, "Lddd", "")
0942
0943 // Generate random number
0944 TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions")
0945 TARGET_BUILTIN(__builtin_darn_raw, "LLi", "", "isa-v30-instructions")
0946 TARGET_BUILTIN(__builtin_darn_32, "i", "", "isa-v30-instructions")
0947
0948 // Vector int128 (un)pack
0949 TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "", "vsx")
0950 TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx")
0951
0952 // Set the floating point rounding mode
0953 BUILTIN(__builtin_setrnd, "di", "")
0954
0955 // Get content from current FPSCR
0956 BUILTIN(__builtin_readflm, "d", "")
0957
0958 // Set content of FPSCR, and return its content before update
0959 BUILTIN(__builtin_setflm, "dd", "")
0960
0961 // Cache built-ins
0962 BUILTIN(__builtin_dcbf, "vvC*", "")
0963
0964 // Built-ins requiring custom code generation.
0965 // Because these built-ins rely on target-dependent types and to avoid pervasive
0966 // change, they are type checked manually in Sema using custom type descriptors.
0967 // The first argument of the CUSTOM_BUILTIN macro is the name of the built-in
0968 // with its prefix, the second argument is the name of the intrinsic this
0969 // built-in generates, the third argument specifies the type of the function
0970 // (result value, then each argument) as follows:
0971 // i -> Unsigned integer followed by the greatest possible value for that
0972 // argument or 0 if no constraint on the value.
0973 // (e.g. i15 for a 4-bits value)
0974 // V -> Vector type used with MMA built-ins (vector unsigned char)
0975 // W -> PPC Vector type followed by the size of the vector type.
0976 // (e.g. W512 for __vector_quad)
0977 // any other descriptor -> Fall back to generic type descriptor decoding.
0978 // The 'C' suffix can be used as a suffix to specify the const type.
0979 // The '*' suffix can be used as a suffix to specify a pointer to a type.
0980 // The fourth argument is set to true if the built-in accumulates its result into
0981 // its given accumulator.
0982
0983 // Provided builtins with _mma_ prefix for compatibility.
0984 CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false,
0985 "paired-vector-memops")
0986 CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false,
0987 "paired-vector-memops")
0988 CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false,
0989 "paired-vector-memops")
0990 CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false,
0991 "paired-vector-memops")
0992 CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false,
0993 "paired-vector-memops")
0994 CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false, "mma")
0995
0996 // UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have
0997 // the same name as that of the intrinsic they generate, i.e. the
0998 // ID and INTR are the same.
0999 // This avoids repeating the ID and INTR in the macro expression.
1000
1001 UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false,
1002 "paired-vector-memops")
1003 UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false,
1004 "paired-vector-memops")
1005 UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false,
1006 "paired-vector-memops")
1007 UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false,
1008 "paired-vector-memops")
1009
1010 // TODO: Require only mma after backend supports these without paired memops
1011 UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false,
1012 "mma,paired-vector-memops")
1013 UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false,
1014 "mma,paired-vector-memops")
1015 UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true,
1016 "mma,paired-vector-memops")
1017 UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true,
1018 "mma,paired-vector-memops")
1019 UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false,
1020 "mma,paired-vector-memops")
1021 UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false,
1022 "mma,paired-vector-memops")
1023 UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false,
1024 "mma,paired-vector-memops")
1025 UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false,
1026 "mma,paired-vector-memops")
1027 UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false,
1028 "mma,paired-vector-memops")
1029 UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV", false,
1030 "mma,paired-vector-memops")
1031 UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV", false,
1032 "mma,paired-vector-memops")
1033 UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V", false,
1034 "mma,paired-vector-memops")
1035 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false,
1036 "mma,paired-vector-memops")
1037 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false,
1038 "mma,paired-vector-memops")
1039 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false,
1040 "mma,paired-vector-memops")
1041 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false,
1042 "mma,paired-vector-memops")
1043 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3", false,
1044 "mma,paired-vector-memops")
1045 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15", false,
1046 "mma,paired-vector-memops")
1047 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3", false,
1048 "mma,paired-vector-memops")
1049 UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true,
1050 "mma,paired-vector-memops")
1051 UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true,
1052 "mma,paired-vector-memops")
1053 UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true,
1054 "mma,paired-vector-memops")
1055 UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true,
1056 "mma,paired-vector-memops")
1057 UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true,
1058 "mma,paired-vector-memops")
1059 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true,
1060 "mma,paired-vector-memops")
1061 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true,
1062 "mma,paired-vector-memops")
1063 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true,
1064 "mma,paired-vector-memops")
1065 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true,
1066 "mma,paired-vector-memops")
1067 UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true,
1068 "mma,paired-vector-memops")
1069 UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV", true,
1070 "mma,paired-vector-memops")
1071 UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV", true,
1072 "mma,paired-vector-memops")
1073 UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV", true,
1074 "mma,paired-vector-memops")
1075 UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV", true,
1076 "mma,paired-vector-memops")
1077 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3", true,
1078 "mma,paired-vector-memops")
1079 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3", true,
1080 "mma,paired-vector-memops")
1081 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3", true,
1082 "mma,paired-vector-memops")
1083 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3", true,
1084 "mma,paired-vector-memops")
1085 UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV", true,
1086 "mma,paired-vector-memops")
1087 UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV", true,
1088 "mma,paired-vector-memops")
1089 UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV", true,
1090 "mma,paired-vector-memops")
1091 UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV", true,
1092 "mma,paired-vector-memops")
1093 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15", true,
1094 "mma,paired-vector-memops")
1095 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15", true,
1096 "mma,paired-vector-memops")
1097 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15", true,
1098 "mma,paired-vector-memops")
1099 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15", true,
1100 "mma,paired-vector-memops")
1101 UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V", true,
1102 "mma,paired-vector-memops")
1103 UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V", true,
1104 "mma,paired-vector-memops")
1105 UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V", true,
1106 "mma,paired-vector-memops")
1107 UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V", true,
1108 "mma,paired-vector-memops")
1109 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3", true,
1110 "mma,paired-vector-memops")
1111 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3", true,
1112 "mma,paired-vector-memops")
1113 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3", true,
1114 "mma,paired-vector-memops")
1115 UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3", true,
1116 "mma,paired-vector-memops")
1117 UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV", false,
1118 "mma,paired-vector-memops")
1119 UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3", false,
1120 "mma,paired-vector-memops")
1121 UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV", true,
1122 "mma,paired-vector-memops")
1123 UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV", true,
1124 "mma,paired-vector-memops")
1125 UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV", true,
1126 "mma,paired-vector-memops")
1127 UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV", true,
1128 "mma,paired-vector-memops")
1129 UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3", true,
1130 "mma,paired-vector-memops")
1131 UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3", true,
1132 "mma,paired-vector-memops")
1133 UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true,
1134 "mma,paired-vector-memops")
1135 UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true,
1136 "mma,paired-vector-memops")
1137
1138 // FIXME: Obviously incomplete.
1139
1140 #undef BUILTIN
1141 #undef CUSTOM_BUILTIN
1142 #undef UNALIASED_CUSTOM_BUILTIN
