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Warning, file /include/QtCore/qprocessordetection.h was not indexed or was modified since last indexation (in which case cross-reference links may be missing, inaccurate or erroneous).

0001 // Copyright (C) 2016 The Qt Company Ltd.
0002 // Copyright (C) 2016 Intel Corporation.
0003 // SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
0004 
0005 
0006 #if 0
0007 #pragma qt_class(QtProcessorDetection)
0008 #pragma qt_sync_skip_header_check
0009 #pragma qt_sync_stop_processing
0010 #endif
0011 
0012 #ifndef QPROCESSORDETECTION_H
0013 #define QPROCESSORDETECTION_H
0014 
0015 /*
0016     This file uses preprocessor #defines to set various Q_PROCESSOR_* #defines
0017     based on the following patterns:
0018 
0019     Q_PROCESSOR_{FAMILY}
0020     Q_PROCESSOR_{FAMILY}_{VARIANT}
0021     Q_PROCESSOR_{FAMILY}_{REVISION}
0022 
0023     The first is always defined. Defines for the various revisions/variants are
0024     optional and usually dependent on how the compiler was invoked. Variants
0025     that are a superset of another should have a define for the superset.
0026 
0027     In addition to the processor family, variants, and revisions, we also set
0028     Q_BYTE_ORDER appropriately for the target processor. For bi-endian
0029     processors, we try to auto-detect the byte order using the __BIG_ENDIAN__,
0030     __LITTLE_ENDIAN__, or __BYTE_ORDER__ preprocessor macros.
0031 
0032     Note: when adding support for new processors, be sure to update
0033     config.tests/arch/arch.cpp to ensure that configure can detect the target
0034     and host architectures.
0035 */
0036 
0037 /* Machine byte-order, reuse preprocessor provided macros when available */
0038 #if defined(__ORDER_BIG_ENDIAN__)
0039 #  define Q_BIG_ENDIAN __ORDER_BIG_ENDIAN__
0040 #else
0041 #  define Q_BIG_ENDIAN 4321
0042 #endif
0043 #if defined(__ORDER_LITTLE_ENDIAN__)
0044 #  define Q_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
0045 #else
0046 #  define Q_LITTLE_ENDIAN 1234
0047 #endif
0048 
0049 /*
0050     Alpha family, no revisions or variants
0051 
0052     Alpha is bi-endian, use endianness auto-detection implemented below.
0053 */
0054 #if defined(__alpha__) || defined(_M_ALPHA)
0055 #  define Q_PROCESSOR_ALPHA
0056 // Q_BYTE_ORDER not defined, use endianness auto-detection
0057 
0058 /*
0059     ARM family, known revisions: V5, V6, V7, V8
0060 
0061     ARM is bi-endian, detect using __ARMEL__ or __ARMEB__, falling back to
0062     auto-detection implemented below.
0063 */
0064 #elif defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(_M_ARM64) || defined(__aarch64__) || defined(__ARM64__)
0065 #  if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
0066 #    define Q_PROCESSOR_ARM_64
0067 #    define Q_PROCESSOR_WORDSIZE 8
0068 #  else
0069 #    define Q_PROCESSOR_ARM_32
0070 #  endif
0071 #  if defined(__ARM_ARCH) && __ARM_ARCH > 1
0072 #    define Q_PROCESSOR_ARM __ARM_ARCH
0073 #  elif defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM > 1
0074 #    define Q_PROCESSOR_ARM __TARGET_ARCH_ARM
0075 #  elif defined(_M_ARM) && _M_ARM > 1
0076 #    define Q_PROCESSOR_ARM _M_ARM
0077 #  elif defined(__ARM64_ARCH_8__) \
0078       || defined(__aarch64__) \
0079       || defined(__ARMv8__) \
0080       || defined(__ARMv8_A__) \
0081       || defined(_M_ARM64)
0082 #    define Q_PROCESSOR_ARM 8
0083 #  elif defined(__ARM_ARCH_7__) \
0084       || defined(__ARM_ARCH_7A__) \
0085       || defined(__ARM_ARCH_7R__) \
0086       || defined(__ARM_ARCH_7M__) \
0087       || defined(__ARM_ARCH_7S__) \
0088       || defined(_ARM_ARCH_7) \
0089       || defined(__CORE_CORTEXA__)
0090 #    define Q_PROCESSOR_ARM 7
0091 #  elif defined(__ARM_ARCH_6__) \
0092       || defined(__ARM_ARCH_6J__) \
0093       || defined(__ARM_ARCH_6T2__) \
0094       || defined(__ARM_ARCH_6Z__) \
0095       || defined(__ARM_ARCH_6K__) \
0096       || defined(__ARM_ARCH_6ZK__) \
0097       || defined(__ARM_ARCH_6M__)
0098 #    define Q_PROCESSOR_ARM 6
0099 #  elif defined(__ARM_ARCH_5TEJ__) \
0100         || defined(__ARM_ARCH_5TE__)
0101 #    define Q_PROCESSOR_ARM 5
0102 #  else
0103 #    define Q_PROCESSOR_ARM 0
0104 #  endif
0105 #  if Q_PROCESSOR_ARM >= 8
0106 #    define Q_PROCESSOR_ARM_V8
0107 #  endif
0108 #  if Q_PROCESSOR_ARM >= 7
0109 #    define Q_PROCESSOR_ARM_V7
0110 #  endif
0111 #  if Q_PROCESSOR_ARM >= 6
0112 #    define Q_PROCESSOR_ARM_V6
0113 #  endif
0114 #  if Q_PROCESSOR_ARM >= 5
0115 #    define Q_PROCESSOR_ARM_V5
0116 #  else
0117 #    error "ARM architecture too old"
0118 #  endif
0119 #  if defined(__ARMEL__) || defined(_M_ARM64)
0120 #    define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0121 #  elif defined(__ARMEB__)
0122 #    define Q_BYTE_ORDER Q_BIG_ENDIAN
0123 #  else
0124 // Q_BYTE_ORDER not defined, use endianness auto-detection
0125 #endif
0126 
0127 /*
0128     AVR32 family, no revisions or variants
0129 
0130     AVR32 is big-endian.
0131 */
0132 // #elif defined(__avr32__)
0133 // #  define Q_PROCESSOR_AVR32
0134 // #  define Q_BYTE_ORDER Q_BIG_ENDIAN
0135 
0136 /*
0137     Blackfin family, no revisions or variants
0138 
0139     Blackfin is little-endian.
0140 */
0141 // #elif defined(__bfin__)
0142 // #  define Q_PROCESSOR_BLACKFIN
0143 // #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0144 
0145 /*
0146     PA-RISC family, no revisions or variants
0147 
0148     PA-RISC is big-endian.
0149 */
0150 #elif defined(__hppa__)
0151 #  define Q_PROCESSOR_HPPA
0152 #  define Q_BYTE_ORDER Q_BIG_ENDIAN
0153 
0154 /*
0155     X86 family, known variants: 32- and 64-bit
0156 
0157     X86 is little-endian.
0158 */
0159 #elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
0160 #  define Q_PROCESSOR_X86_32
0161 #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0162 #  define Q_PROCESSOR_WORDSIZE   4
0163 
0164 /*
0165  * We define Q_PROCESSOR_X86 == 6 for anything above a equivalent or better
0166  * than a Pentium Pro (the processor whose architecture was called P6) or an
0167  * Athlon.
0168  *
0169  * All processors since the Pentium III and the Athlon 4 have SSE support, so
0170  * we use that to detect. That leaves the original Athlon, Pentium Pro and
0171  * Pentium II.
0172  */
0173 
0174 #  if defined(_M_IX86)
0175 #    define Q_PROCESSOR_X86     (_M_IX86/100)
0176 #  elif defined(__i686__) || defined(__athlon__) || defined(__SSE__) || defined(__pentiumpro__)
0177 #    define Q_PROCESSOR_X86     6
0178 #  elif defined(__i586__) || defined(__k6__) || defined(__pentium__)
0179 #    define Q_PROCESSOR_X86     5
0180 #  elif defined(__i486__) || defined(__80486__)
0181 #    define Q_PROCESSOR_X86     4
0182 #  else
0183 #    define Q_PROCESSOR_X86     3
0184 #  endif
0185 
0186 #elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
0187 #  define Q_PROCESSOR_X86       6
0188 #  define Q_PROCESSOR_X86_64
0189 #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0190 #  define Q_PROCESSOR_WORDSIZE   8
0191 
0192 /*
0193     Itanium (IA-64) family, no revisions or variants
0194 
0195     Itanium is bi-endian, use endianness auto-detection implemented below.
0196 */
0197 #elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
0198 #  define Q_PROCESSOR_IA64
0199 #  define Q_PROCESSOR_WORDSIZE   8
0200 // Q_BYTE_ORDER not defined, use endianness auto-detection
0201 
0202 /*
0203     LoongArch family, known variants: 32- and 64-bit
0204 
0205     LoongArch is little-endian.
0206 */
0207 #elif defined(__loongarch__)
0208 #  define Q_PROCESSOR_LOONGARCH
0209 #  if __loongarch_grlen == 64
0210 #    define Q_PROCESSOR_LOONGARCH_64
0211 #  else
0212 #    define Q_PROCESSOR_LOONGARCH_32
0213 #  endif
0214 #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0215 
0216 /*
0217     Motorola 68000 family, no revisions or variants
0218 
0219     M68K is big-endian.
0220 */
0221 #elif defined(__m68k__)
0222 #  define Q_PROCESSOR_M68K
0223 #  define Q_BYTE_ORDER Q_BIG_ENDIAN
0224 
0225 /*
0226     MIPS family, known revisions: I, II, III, IV, 32, 64
0227 
0228     MIPS is bi-endian, use endianness auto-detection implemented below.
0229 */
0230 #elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
0231 #  define Q_PROCESSOR_MIPS
0232 #  if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
0233 #    define Q_PROCESSOR_MIPS_I
0234 #  endif
0235 #  if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
0236 #    define Q_PROCESSOR_MIPS_II
0237 #  endif
0238 #  if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
0239 #    define Q_PROCESSOR_MIPS_III
0240 #  endif
0241 #  if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
0242 #    define Q_PROCESSOR_MIPS_IV
0243 #  endif
0244 #  if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
0245 #    define Q_PROCESSOR_MIPS_V
0246 #  endif
0247 #  if defined(_MIPS_ARCH_MIPS32) || defined(__mips32) || (defined(__mips) && __mips - 0 >= 32)
0248 #    define Q_PROCESSOR_MIPS_32
0249 #  endif
0250 #  if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
0251 #    define Q_PROCESSOR_MIPS_64
0252 #    define Q_PROCESSOR_WORDSIZE 8
0253 #  endif
0254 #  if defined(__MIPSEL__)
0255 #    define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0256 #  elif defined(__MIPSEB__)
0257 #    define Q_BYTE_ORDER Q_BIG_ENDIAN
0258 #  else
0259 // Q_BYTE_ORDER not defined, use endianness auto-detection
0260 #  endif
0261 
0262 /*
0263     Power family, known variants: 32- and 64-bit
0264 
0265     There are many more known variants/revisions that we do not handle/detect.
0266     See http://en.wikipedia.org/wiki/Power_Architecture
0267     and http://en.wikipedia.org/wiki/File:PowerISA-evolution.svg
0268 
0269     Power is bi-endian, use endianness auto-detection implemented below.
0270 */
0271 #elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
0272       || defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC)  \
0273       || defined(_M_MPPC) || defined(_M_PPC)
0274 #  define Q_PROCESSOR_POWER
0275 #  if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
0276 #    define Q_PROCESSOR_POWER_64
0277 #    define Q_PROCESSOR_WORDSIZE 8
0278 #  else
0279 #    define Q_PROCESSOR_POWER_32
0280 #  endif
0281 // Q_BYTE_ORDER not defined, use endianness auto-detection
0282 
0283 /*
0284     RISC-V family, known variants: 32- and 64-bit
0285 
0286     RISC-V is little-endian.
0287 */
0288 #elif defined(__riscv)
0289 #  define Q_PROCESSOR_RISCV
0290 #  if __riscv_xlen == 64
0291 #    define Q_PROCESSOR_RISCV_64
0292 #  else
0293 #    define Q_PROCESSOR_RISCV_32
0294 #  endif
0295 #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0296 
0297 /*
0298     S390 family, known variant: S390X (64-bit)
0299 
0300     S390 is big-endian.
0301 */
0302 #elif defined(__s390__)
0303 #  define Q_PROCESSOR_S390
0304 #  if defined(__s390x__)
0305 #    define Q_PROCESSOR_S390_X
0306 #  endif
0307 #  define Q_BYTE_ORDER Q_BIG_ENDIAN
0308 
0309 /*
0310     SuperH family, optional revision: SH-4A
0311 
0312     SuperH is bi-endian, use endianness auto-detection implemented below.
0313 */
0314 // #elif defined(__sh__)
0315 // #  define Q_PROCESSOR_SH
0316 // #  if defined(__sh4a__)
0317 // #    define Q_PROCESSOR_SH_4A
0318 // #  endif
0319 // Q_BYTE_ORDER not defined, use endianness auto-detection
0320 
0321 /*
0322     SPARC family, optional revision: V9
0323 
0324     SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
0325     as the default byte order. Assume all SPARC systems are big-endian.
0326 */
0327 #elif defined(__sparc__)
0328 #  define Q_PROCESSOR_SPARC
0329 #  if defined(__sparc_v9__) || defined(__sparcv9)
0330 #    define Q_PROCESSOR_SPARC_V9
0331 #  endif
0332 #  if defined(__sparc64__)
0333 #    define Q_PROCESSOR_SPARC_64
0334 #  endif
0335 #  define Q_BYTE_ORDER Q_BIG_ENDIAN
0336 
0337 // -- Web Assembly --
0338 #elif defined(__EMSCRIPTEN__)
0339 #  define Q_PROCESSOR_WASM
0340 #  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0341 #  define Q_PROCESSOR_WORDSIZE 8
0342 #ifdef QT_COMPILER_SUPPORTS_SSE2
0343 #  define Q_PROCESSOR_X86 6   // enables SIMD support
0344 # define Q_PROCESSOR_X86_64 // wasm64
0345 #  define Q_PROCESSOR_WASM_64
0346 #endif
0347 
0348 #endif
0349 
0350 /*
0351   NOTE:
0352   GCC 4.6 added __BYTE_ORDER__, __ORDER_BIG_ENDIAN__, __ORDER_LITTLE_ENDIAN__
0353   and __ORDER_PDP_ENDIAN__ in SVN r165881. If you are using GCC 4.6 or newer,
0354   this code will properly detect your target byte order; if you are not, and
0355   the __LITTLE_ENDIAN__ or __BIG_ENDIAN__ macros are not defined, then this
0356   code will fail to detect the target byte order.
0357 */
0358 // Some processors support either endian format, try to detect which we are using.
0359 #if !defined(Q_BYTE_ORDER)
0360 #  if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
0361 // Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
0362 #    define Q_BYTE_ORDER __BYTE_ORDER__
0363 #  elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
0364 #    define Q_BYTE_ORDER Q_BIG_ENDIAN
0365 #  elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN)
0366 #    define Q_BYTE_ORDER Q_LITTLE_ENDIAN
0367 #  else
0368 #    error "Unable to determine byte order!"
0369 #  endif
0370 #endif
0371 
0372 /*
0373    Size of a pointer and the machine register size. We detect a 64-bit system by:
0374    * GCC and compatible compilers (Clang, ICC on OS X and Windows) always define
0375      __SIZEOF_POINTER__. This catches all known cases of ILP32 builds on 64-bit
0376      processors.
0377    * Most other Unix compilers define __LP64__ or _LP64 on 64-bit mode
0378      (Long and Pointer 64-bit)
0379    * If Q_PROCESSOR_WORDSIZE was defined above, it's assumed to match the pointer
0380      size.
0381    Otherwise, we assume to be 32-bit and then check in qglobal.cpp that it is right.
0382 */
0383 
0384 #if defined __SIZEOF_POINTER__
0385 #  define QT_POINTER_SIZE           __SIZEOF_POINTER__
0386 #elif defined(__LP64__) || defined(_LP64)
0387 #  define QT_POINTER_SIZE           8
0388 #elif defined(Q_PROCESSOR_WORDSIZE)
0389 #  define QT_POINTER_SIZE           Q_PROCESSOR_WORDSIZE
0390 #else
0391 #  define QT_POINTER_SIZE           4
0392 #endif
0393 
0394 /*
0395    Define Q_PROCESSOR_WORDSIZE to be the size of the machine's word (usually,
0396    the size of the register). On some architectures where a pointer could be
0397    smaller than the register, the macro is defined above.
0398 
0399    Falls back to QT_POINTER_SIZE if not set explicitly for the platform.
0400 */
0401 #ifndef Q_PROCESSOR_WORDSIZE
0402 #  define Q_PROCESSOR_WORDSIZE        QT_POINTER_SIZE
0403 #endif
0404 
0405 
0406 #endif // QPROCESSORDETECTION_H
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