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File indexing completed on 2025-01-18 10:13:29

0001 #define OFFSET_x86_EAX 8
0002 #define OFFSET_x86_EBX 20
0003 #define OFFSET_x86_ECX 12
0004 #define OFFSET_x86_EDX 16
0005 #define OFFSET_x86_ESI 32
0006 #define OFFSET_x86_EDI 36
0007 #define OFFSET_x86_EBP 28
0008 #define OFFSET_x86_ESP 24
0009 #define OFFSET_x86_EIP 68
0010 #define OFFSET_x86_CS 288
0011 #define OFFSET_x86_DS 290
0012 #define OFFSET_x86_ES 292
0013 #define OFFSET_x86_FS 294
0014 #define OFFSET_x86_GS 296
0015 #define OFFSET_x86_SS 298
0016 #define OFFSET_amd64_RAX 16
0017 #define OFFSET_amd64_RBX 40
0018 #define OFFSET_amd64_RCX 24
0019 #define OFFSET_amd64_RDX 32
0020 #define OFFSET_amd64_RSI 64
0021 #define OFFSET_amd64_RDI 72
0022 #define OFFSET_amd64_RSP 48
0023 #define OFFSET_amd64_RBP 56
0024 #define OFFSET_amd64_R8 80
0025 #define OFFSET_amd64_R9 88
0026 #define OFFSET_amd64_R10 96
0027 #define OFFSET_amd64_R11 104
0028 #define OFFSET_amd64_R12 112
0029 #define OFFSET_amd64_R13 120
0030 #define OFFSET_amd64_R14 128
0031 #define OFFSET_amd64_R15 136
0032 #define OFFSET_amd64_RIP 184
0033 #define OFFSET_ppc32_GPR0 16
0034 #define OFFSET_ppc32_GPR1 20
0035 #define OFFSET_ppc32_GPR2 24
0036 #define OFFSET_ppc32_GPR3 28
0037 #define OFFSET_ppc32_GPR4 32
0038 #define OFFSET_ppc32_GPR5 36
0039 #define OFFSET_ppc32_GPR6 40
0040 #define OFFSET_ppc32_GPR7 44
0041 #define OFFSET_ppc32_GPR8 48
0042 #define OFFSET_ppc32_GPR9 52
0043 #define OFFSET_ppc32_GPR10 56
0044 #define OFFSET_ppc32_CIA 1168
0045 #define OFFSET_ppc32_CR0_0 1187
0046 #define OFFSET_ppc64_GPR0 16
0047 #define OFFSET_ppc64_GPR1 24
0048 #define OFFSET_ppc64_GPR2 32
0049 #define OFFSET_ppc64_GPR3 40
0050 #define OFFSET_ppc64_GPR4 48
0051 #define OFFSET_ppc64_GPR5 56
0052 #define OFFSET_ppc64_GPR6 64
0053 #define OFFSET_ppc64_GPR7 72
0054 #define OFFSET_ppc64_GPR8 80
0055 #define OFFSET_ppc64_GPR9 88
0056 #define OFFSET_ppc64_GPR10 96
0057 #define OFFSET_ppc64_CIA 1296
0058 #define OFFSET_ppc64_CR0_0 1327
0059 #define OFFSET_arm_R0 8
0060 #define OFFSET_arm_R1 12
0061 #define OFFSET_arm_R2 16
0062 #define OFFSET_arm_R3 20
0063 #define OFFSET_arm_R4 24
0064 #define OFFSET_arm_R5 28
0065 #define OFFSET_arm_R7 36
0066 #define OFFSET_arm_R13 60
0067 #define OFFSET_arm_R14 64
0068 #define OFFSET_arm_R15T 68
0069 #define OFFSET_arm64_X0 16
0070 #define OFFSET_arm64_X1 24
0071 #define OFFSET_arm64_X2 32
0072 #define OFFSET_arm64_X3 40
0073 #define OFFSET_arm64_X4 48
0074 #define OFFSET_arm64_X5 56
0075 #define OFFSET_arm64_X6 64
0076 #define OFFSET_arm64_X7 72
0077 #define OFFSET_arm64_X8 80
0078 #define OFFSET_arm64_XSP 264
0079 #define OFFSET_arm64_PC 272
0080 #define OFFSET_s390x_r2 592
0081 #define OFFSET_s390x_r3 600
0082 #define OFFSET_s390x_r4 608
0083 #define OFFSET_s390x_r5 616
0084 #define OFFSET_s390x_r6 624
0085 #define OFFSET_s390x_r7 632
0086 #define OFFSET_s390x_r15 696
0087 #define OFFSET_s390x_IA 720
0088 #define OFFSET_s390x_SYSNO 728
0089 #define OFFSET_s390x_IP_AT_SYSCALL 792
0090 #define OFFSET_s390x_fpc 712
0091 #define OFFSET_s390x_CC_OP 736
0092 #define OFFSET_s390x_CC_DEP1 744
0093 #define OFFSET_s390x_CC_DEP2 752
0094 #define OFFSET_s390x_CC_NDEP 760
0095 #define OFFSET_mips32_r0 8
0096 #define OFFSET_mips32_r1 12
0097 #define OFFSET_mips32_r2 16
0098 #define OFFSET_mips32_r3 20
0099 #define OFFSET_mips32_r4 24
0100 #define OFFSET_mips32_r5 28
0101 #define OFFSET_mips32_r6 32
0102 #define OFFSET_mips32_r7 36
0103 #define OFFSET_mips32_r8 40
0104 #define OFFSET_mips32_r9 44
0105 #define OFFSET_mips32_r10 48
0106 #define OFFSET_mips32_r11 52
0107 #define OFFSET_mips32_r12 56
0108 #define OFFSET_mips32_r13 60
0109 #define OFFSET_mips32_r14 64
0110 #define OFFSET_mips32_r15 68
0111 #define OFFSET_mips32_r15 68
0112 #define OFFSET_mips32_r17 76
0113 #define OFFSET_mips32_r18 80
0114 #define OFFSET_mips32_r19 84
0115 #define OFFSET_mips32_r20 88
0116 #define OFFSET_mips32_r21 92
0117 #define OFFSET_mips32_r22 96
0118 #define OFFSET_mips32_r23 100
0119 #define OFFSET_mips32_r24 104
0120 #define OFFSET_mips32_r25 108
0121 #define OFFSET_mips32_r26 112
0122 #define OFFSET_mips32_r27 116
0123 #define OFFSET_mips32_r28 120
0124 #define OFFSET_mips32_r29 124
0125 #define OFFSET_mips32_r30 128
0126 #define OFFSET_mips32_r31 132
0127 #define OFFSET_mips32_PC 136
0128 #define OFFSET_mips32_HI 140
0129 #define OFFSET_mips32_LO 144
0130 #define OFFSET_mips64_r0 16
0131 #define OFFSET_mips64_r1 24
0132 #define OFFSET_mips64_r2 32
0133 #define OFFSET_mips64_r3 40
0134 #define OFFSET_mips64_r4 48
0135 #define OFFSET_mips64_r5 56
0136 #define OFFSET_mips64_r6 64
0137 #define OFFSET_mips64_r7 72
0138 #define OFFSET_mips64_r8 80
0139 #define OFFSET_mips64_r9 88
0140 #define OFFSET_mips64_r10 96
0141 #define OFFSET_mips64_r11 104
0142 #define OFFSET_mips64_r12 112
0143 #define OFFSET_mips64_r13 120
0144 #define OFFSET_mips64_r14 128
0145 #define OFFSET_mips64_r15 136
0146 #define OFFSET_mips64_r15 136
0147 #define OFFSET_mips64_r17 152
0148 #define OFFSET_mips64_r18 160
0149 #define OFFSET_mips64_r19 168
0150 #define OFFSET_mips64_r20 176
0151 #define OFFSET_mips64_r21 184
0152 #define OFFSET_mips64_r22 192
0153 #define OFFSET_mips64_r23 200
0154 #define OFFSET_mips64_r24 208
0155 #define OFFSET_mips64_r25 216
0156 #define OFFSET_mips64_r26 224
0157 #define OFFSET_mips64_r27 232
0158 #define OFFSET_mips64_r28 240
0159 #define OFFSET_mips64_r29 248
0160 #define OFFSET_mips64_r30 256
0161 #define OFFSET_mips64_r31 264
0162 #define OFFSET_mips64_PC 272
0163 #define OFFSET_mips64_HI 280
0164 #define OFFSET_mips64_LO 288