tbb/machine/windows_ia32.h

0001 /*
0002     Copyright (c) 2005-2020 Intel Corporation
0003
0004     Licensed under the Apache License, Version 2.0 (the "License");
0005     you may not use this file except in compliance with the License.
0006     You may obtain a copy of the License at
0007
0008         http://www.apache.org/licenses/LICENSE-2.0
0009
0010     Unless required by applicable law or agreed to in writing, software
0011     distributed under the License is distributed on an "AS IS" BASIS,
0012     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
0013     See the License for the specific language governing permissions and
0014     limitations under the License.
0015 */
0016
0017 #if !defined(__TBB_machine_H) || defined(__TBB_machine_windows_ia32_H)
0018 #error Do not #include this internal file directly; use public TBB headers instead.
0019 #endif
0020
0021 #define __TBB_machine_windows_ia32_H
0022
0023 #if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
0024     // Workaround for overzealous compiler warnings in /Wp64 mode
0025     #pragma warning (push)
0026     #pragma warning (disable: 4244 4267)
0027 #endif
0028
0029 #include "msvc_ia32_common.h"
0030
0031 #define __TBB_WORDSIZE 4
0032 #define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
0033
0034 extern "C" {
0035     __int64 __TBB_EXPORTED_FUNC __TBB_machine_cmpswp8 (volatile void *ptr, __int64 value, __int64 comparand );
0036     __int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchadd8 (volatile void *ptr, __int64 addend );
0037     __int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchstore8 (volatile void *ptr, __int64 value );
0038     void __TBB_EXPORTED_FUNC __TBB_machine_store8 (volatile void *ptr, __int64 value );
0039     __int64 __TBB_EXPORTED_FUNC __TBB_machine_load8 (const volatile void *ptr);
0040 }
0041
0042 #if !__TBB_MSVC_PART_WORD_INTERLOCKED_INTRINSICS_PRESENT
0043
0044 #define __TBB_MACHINE_DEFINE_ATOMICS(S,T,U,A,C) \
0045 static inline T __TBB_machine_cmpswp##S ( volatile void * ptr, U value, U comparand ) { \
0046     T result; \
0047     volatile T *p = (T *)ptr; \
0048     __asm \
0049     { \
0050        __asm mov edx, p \
0051        __asm mov C , value \
0052        __asm mov A , comparand \
0053        __asm lock cmpxchg [edx], C \
0054        __asm mov result, A \
0055     } \
0056     return result; \
0057 } \
0058 \
0059 static inline T __TBB_machine_fetchadd##S ( volatile void * ptr, U addend ) { \
0060     T result; \
0061     volatile T *p = (T *)ptr; \
0062     __asm \
0063     { \
0064         __asm mov edx, p \
0065         __asm mov A, addend \
0066         __asm lock xadd [edx], A \
0067         __asm mov result, A \
0068     } \
0069     return result; \
0070 }\
0071 \
0072 static inline T __TBB_machine_fetchstore##S ( volatile void * ptr, U value ) { \
0073     T result; \
0074     volatile T *p = (T *)ptr; \
0075     __asm \
0076     { \
0077         __asm mov edx, p \
0078         __asm mov A, value \
0079         __asm lock xchg [edx], A \
0080         __asm mov result, A \
0081     } \
0082     return result; \
0083 }
0084
0085
0086 __TBB_MACHINE_DEFINE_ATOMICS(1, __int8, __int8, al, cl)
0087 __TBB_MACHINE_DEFINE_ATOMICS(2, __int16, __int16, ax, cx)
0088 __TBB_MACHINE_DEFINE_ATOMICS(4, ptrdiff_t, ptrdiff_t, eax, ecx)
0089
0090 #undef __TBB_MACHINE_DEFINE_ATOMICS
0091
0092 #endif /* __TBB_MSVC_PART_WORD_INTERLOCKED_INTRINSICS_PRESENT */
0093
0094 //TODO: Check if it possible and profitable for IA-32 architecture on (Linux and Windows)
0095 //to use of 64-bit load/store via floating point registers together with full fence
0096 //for sequentially consistent load/store, instead of CAS.
0097 #define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE           1
0098 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE            1
0099 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE                1
0100 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
0101
0102
0103 #if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
0104     #pragma warning (pop)
0105 #endif // warnings 4244, 4267 are back