include/libdrm/virtgpu_drm.h

0001 /*
0002  * Copyright 2013 Red Hat
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice (including the next
0013  * paragraph) shall be included in all copies or substantial portions of the
0014  * Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  */
0024 #ifndef VIRTGPU_DRM_H
0025 #define VIRTGPU_DRM_H
0026
0027 #include "drm.h"
0028
0029 #if defined(__cplusplus)
0030 extern "C" {
0031 #endif
0032
0033 /* Please note that modifications to all structs defined here are
0034  * subject to backwards-compatibility constraints.
0035  *
0036  * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
0037  * compatibility Keep fields aligned to their size
0038  */
0039
0040 #define DRM_VIRTGPU_MAP         0x01
0041 #define DRM_VIRTGPU_EXECBUFFER  0x02
0042 #define DRM_VIRTGPU_GETPARAM    0x03
0043 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
0044 #define DRM_VIRTGPU_RESOURCE_INFO     0x05
0045 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
0046 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
0047 #define DRM_VIRTGPU_WAIT     0x08
0048 #define DRM_VIRTGPU_GET_CAPS  0x09
0049
0050 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
0051 #define VIRTGPU_EXECBUF_FENCE_FD_OUT    0x02
0052 #define VIRTGPU_EXECBUF_FLAGS  (\
0053         VIRTGPU_EXECBUF_FENCE_FD_IN |\
0054         VIRTGPU_EXECBUF_FENCE_FD_OUT |\
0055         0)
0056
0057 struct drm_virtgpu_map {
0058     __u64 offset; /* use for mmap system call */
0059     __u32 handle;
0060     __u32 pad;
0061 };
0062
0063 struct drm_virtgpu_execbuffer {
0064     __u32 flags;
0065     __u32 size;
0066     __u64 command; /* void* */
0067     __u64 bo_handles;
0068     __u32 num_bo_handles;
0069     __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
0070 };
0071
0072 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
0073 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
0074
0075 struct drm_virtgpu_getparam {
0076     __u64 param;
0077     __u64 value;
0078 };
0079
0080 /* NO_BO flags? NO resource flag? */
0081 /* resource flag for y_0_top */
0082 struct drm_virtgpu_resource_create {
0083     __u32 target;
0084     __u32 format;
0085     __u32 bind;
0086     __u32 width;
0087     __u32 height;
0088     __u32 depth;
0089     __u32 array_size;
0090     __u32 last_level;
0091     __u32 nr_samples;
0092     __u32 flags;
0093     __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
0094     __u32 res_handle;  /* returned by kernel */
0095     __u32 size;        /* validate transfer in the host */
0096     __u32 stride;      /* validate transfer in the host */
0097 };
0098
0099 struct drm_virtgpu_resource_info {
0100     __u32 bo_handle;
0101     __u32 res_handle;
0102     __u32 size;
0103     __u32 stride;
0104 };
0105
0106 struct drm_virtgpu_3d_box {
0107     __u32 x;
0108     __u32 y;
0109     __u32 z;
0110     __u32 w;
0111     __u32 h;
0112     __u32 d;
0113 };
0114
0115 struct drm_virtgpu_3d_transfer_to_host {
0116     __u32 bo_handle;
0117     struct drm_virtgpu_3d_box box;
0118     __u32 level;
0119     __u32 offset;
0120 };
0121
0122 struct drm_virtgpu_3d_transfer_from_host {
0123     __u32 bo_handle;
0124     struct drm_virtgpu_3d_box box;
0125     __u32 level;
0126     __u32 offset;
0127 };
0128
0129 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
0130 struct drm_virtgpu_3d_wait {
0131     __u32 handle; /* 0 is an invalid handle */
0132     __u32 flags;
0133 };
0134
0135 struct drm_virtgpu_get_caps {
0136     __u32 cap_set_id;
0137     __u32 cap_set_ver;
0138     __u64 addr;
0139     __u32 size;
0140     __u32 pad;
0141 };
0142
0143 #define DRM_IOCTL_VIRTGPU_MAP \
0144     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
0145
0146 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
0147     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
0148         struct drm_virtgpu_execbuffer)
0149
0150 #define DRM_IOCTL_VIRTGPU_GETPARAM \
0151     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
0152         struct drm_virtgpu_getparam)
0153
0154 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE           \
0155     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,    \
0156         struct drm_virtgpu_resource_create)
0157
0158 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
0159     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
0160          struct drm_virtgpu_resource_info)
0161
0162 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
0163     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
0164         struct drm_virtgpu_3d_transfer_from_host)
0165
0166 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
0167     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,   \
0168         struct drm_virtgpu_3d_transfer_to_host)
0169
0170 #define DRM_IOCTL_VIRTGPU_WAIT              \
0171     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,   \
0172         struct drm_virtgpu_3d_wait)
0173
0174 #define DRM_IOCTL_VIRTGPU_GET_CAPS \
0175     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
0176     struct drm_virtgpu_get_caps)
0177
0178 #if defined(__cplusplus)
0179 }
0180 #endif
0181
0182 #endif