include/libdrm/virtgpu_drm.h

0001 /*
0002  * Copyright 2013 Red Hat
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice (including the next
0013  * paragraph) shall be included in all copies or substantial portions of the
0014  * Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  */
0024 #ifndef VIRTGPU_DRM_H
0025 #define VIRTGPU_DRM_H
0026
0027 #include "drm.h"
0028
0029 #if defined(__cplusplus)
0030 extern "C" {
0031 #endif
0032
0033 /* Please note that modifications to all structs defined here are
0034  * subject to backwards-compatibility constraints.
0035  *
0036  * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
0037  * compatibility Keep fields aligned to their size
0038  */
0039
0040 #define DRM_VIRTGPU_MAP         0x01
0041 #define DRM_VIRTGPU_EXECBUFFER  0x02
0042 #define DRM_VIRTGPU_GETPARAM    0x03
0043 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
0044 #define DRM_VIRTGPU_RESOURCE_INFO     0x05
0045 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
0046 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
0047 #define DRM_VIRTGPU_WAIT     0x08
0048 #define DRM_VIRTGPU_GET_CAPS  0x09
0049 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
0050 #define DRM_VIRTGPU_CONTEXT_INIT 0x0b
0051
0052 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
0053 #define VIRTGPU_EXECBUF_FENCE_FD_OUT    0x02
0054 #define VIRTGPU_EXECBUF_RING_IDX    0x04
0055 #define VIRTGPU_EXECBUF_FLAGS  (\
0056         VIRTGPU_EXECBUF_FENCE_FD_IN |\
0057         VIRTGPU_EXECBUF_FENCE_FD_OUT |\
0058         VIRTGPU_EXECBUF_RING_IDX |\
0059         0)
0060
0061 struct drm_virtgpu_map {
0062     __u64 offset; /* use for mmap system call */
0063     __u32 handle;
0064     __u32 pad;
0065 };
0066
0067 #define VIRTGPU_EXECBUF_SYNCOBJ_RESET       0x01
0068 #define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
0069         VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
0070         0)
0071 struct drm_virtgpu_execbuffer_syncobj {
0072     __u32 handle;
0073     __u32 flags;
0074     __u64 point;
0075 };
0076
0077 /* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
0078 struct drm_virtgpu_execbuffer {
0079     __u32 flags;
0080     __u32 size;
0081     __u64 command; /* void* */
0082     __u64 bo_handles;
0083     __u32 num_bo_handles;
0084     __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
0085     __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
0086     __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
0087     __u32 num_in_syncobjs;
0088     __u32 num_out_syncobjs;
0089     __u64 in_syncobjs;
0090     __u64 out_syncobjs;
0091 };
0092
0093 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
0094 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
0095 #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
0096 #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
0097 #define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing  */
0098 #define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
0099 #define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
0100 #define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
0101
0102 struct drm_virtgpu_getparam {
0103     __u64 param;
0104     __u64 value;
0105 };
0106
0107 /* NO_BO flags? NO resource flag? */
0108 /* resource flag for y_0_top */
0109 struct drm_virtgpu_resource_create {
0110     __u32 target;
0111     __u32 format;
0112     __u32 bind;
0113     __u32 width;
0114     __u32 height;
0115     __u32 depth;
0116     __u32 array_size;
0117     __u32 last_level;
0118     __u32 nr_samples;
0119     __u32 flags;
0120     __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
0121     __u32 res_handle;  /* returned by kernel */
0122     __u32 size;        /* validate transfer in the host */
0123     __u32 stride;      /* validate transfer in the host */
0124 };
0125
0126 struct drm_virtgpu_resource_info {
0127     __u32 bo_handle;
0128     __u32 res_handle;
0129     __u32 size;
0130     __u32 blob_mem;
0131 };
0132
0133 struct drm_virtgpu_3d_box {
0134     __u32 x;
0135     __u32 y;
0136     __u32 z;
0137     __u32 w;
0138     __u32 h;
0139     __u32 d;
0140 };
0141
0142 struct drm_virtgpu_3d_transfer_to_host {
0143     __u32 bo_handle;
0144     struct drm_virtgpu_3d_box box;
0145     __u32 level;
0146     __u32 offset;
0147     __u32 stride;
0148     __u32 layer_stride;
0149 };
0150
0151 struct drm_virtgpu_3d_transfer_from_host {
0152     __u32 bo_handle;
0153     struct drm_virtgpu_3d_box box;
0154     __u32 level;
0155     __u32 offset;
0156     __u32 stride;
0157     __u32 layer_stride;
0158 };
0159
0160 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
0161 struct drm_virtgpu_3d_wait {
0162     __u32 handle; /* 0 is an invalid handle */
0163     __u32 flags;
0164 };
0165
0166 #define VIRTGPU_DRM_CAPSET_VIRGL 1
0167 #define VIRTGPU_DRM_CAPSET_VIRGL2 2
0168 #define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
0169 #define VIRTGPU_DRM_CAPSET_VENUS 4
0170 #define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
0171 #define VIRTGPU_DRM_CAPSET_DRM 6
0172 struct drm_virtgpu_get_caps {
0173     __u32 cap_set_id;
0174     __u32 cap_set_ver;
0175     __u64 addr;
0176     __u32 size;
0177     __u32 pad;
0178 };
0179
0180 struct drm_virtgpu_resource_create_blob {
0181 #define VIRTGPU_BLOB_MEM_GUEST             0x0001
0182 #define VIRTGPU_BLOB_MEM_HOST3D            0x0002
0183 #define VIRTGPU_BLOB_MEM_HOST3D_GUEST      0x0003
0184
0185 #define VIRTGPU_BLOB_FLAG_USE_MAPPABLE     0x0001
0186 #define VIRTGPU_BLOB_FLAG_USE_SHAREABLE    0x0002
0187 #define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
0188     /* zero is invalid blob_mem */
0189     __u32 blob_mem;
0190     __u32 blob_flags;
0191     __u32 bo_handle;
0192     __u32 res_handle;
0193     __u64 size;
0194
0195     /*
0196      * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
0197      * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
0198      */
0199     __u32 pad;
0200     __u32 cmd_size;
0201     __u64 cmd;
0202     __u64 blob_id;
0203 };
0204
0205 #define VIRTGPU_CONTEXT_PARAM_CAPSET_ID       0x0001
0206 #define VIRTGPU_CONTEXT_PARAM_NUM_RINGS       0x0002
0207 #define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
0208 #define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME      0x0004
0209 struct drm_virtgpu_context_set_param {
0210     __u64 param;
0211     __u64 value;
0212 };
0213
0214 struct drm_virtgpu_context_init {
0215     __u32 num_params;
0216     __u32 pad;
0217
0218     /* pointer to drm_virtgpu_context_set_param array */
0219     __u64 ctx_set_params;
0220 };
0221
0222 /*
0223  * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
0224  * effect.  The event size is sizeof(drm_event), since there is no additional
0225  * payload.
0226  */
0227 #define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
0228
0229 #define DRM_IOCTL_VIRTGPU_MAP \
0230     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
0231
0232 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
0233     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
0234         struct drm_virtgpu_execbuffer)
0235
0236 #define DRM_IOCTL_VIRTGPU_GETPARAM \
0237     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
0238         struct drm_virtgpu_getparam)
0239
0240 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE           \
0241     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,    \
0242         struct drm_virtgpu_resource_create)
0243
0244 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
0245     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
0246          struct drm_virtgpu_resource_info)
0247
0248 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
0249     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
0250         struct drm_virtgpu_3d_transfer_from_host)
0251
0252 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
0253     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,   \
0254         struct drm_virtgpu_3d_transfer_to_host)
0255
0256 #define DRM_IOCTL_VIRTGPU_WAIT              \
0257     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,   \
0258         struct drm_virtgpu_3d_wait)
0259
0260 #define DRM_IOCTL_VIRTGPU_GET_CAPS \
0261     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
0262     struct drm_virtgpu_get_caps)
0263
0264 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB              \
0265     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB,   \
0266         struct drm_virtgpu_resource_create_blob)
0267
0268 #define DRM_IOCTL_VIRTGPU_CONTEXT_INIT                  \
0269     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT,       \
0270         struct drm_virtgpu_context_init)
0271
0272 #if defined(__cplusplus)
0273 }
0274 #endif
0275
0276 #endif