include/libdrm/vc4_drm.h

0001 /*
0002  * Copyright © 2014-2015 Broadcom
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  */
0023
0024 #ifndef _VC4_DRM_H_
0025 #define _VC4_DRM_H_
0026
0027 #include "drm.h"
0028
0029 #if defined(__cplusplus)
0030 extern "C" {
0031 #endif
0032
0033 #define DRM_VC4_SUBMIT_CL                         0x00
0034 #define DRM_VC4_WAIT_SEQNO                        0x01
0035 #define DRM_VC4_WAIT_BO                           0x02
0036 #define DRM_VC4_CREATE_BO                         0x03
0037 #define DRM_VC4_MMAP_BO                           0x04
0038 #define DRM_VC4_CREATE_SHADER_BO                  0x05
0039 #define DRM_VC4_GET_HANG_STATE                    0x06
0040 #define DRM_VC4_GET_PARAM                         0x07
0041 #define DRM_VC4_SET_TILING                        0x08
0042 #define DRM_VC4_GET_TILING                        0x09
0043 #define DRM_VC4_LABEL_BO                          0x0a
0044 #define DRM_VC4_GEM_MADVISE                       0x0b
0045 #define DRM_VC4_PERFMON_CREATE                    0x0c
0046 #define DRM_VC4_PERFMON_DESTROY                   0x0d
0047 #define DRM_VC4_PERFMON_GET_VALUES                0x0e
0048
0049 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
0050 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
0051 #define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
0052 #define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
0053 #define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
0054 #define DRM_IOCTL_VC4_CREATE_SHADER_BO    DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
0055 #define DRM_IOCTL_VC4_GET_HANG_STATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
0056 #define DRM_IOCTL_VC4_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
0057 #define DRM_IOCTL_VC4_SET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
0058 #define DRM_IOCTL_VC4_GET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
0059 #define DRM_IOCTL_VC4_LABEL_BO            DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
0060 #define DRM_IOCTL_VC4_GEM_MADVISE         DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
0061 #define DRM_IOCTL_VC4_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
0062 #define DRM_IOCTL_VC4_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
0063 #define DRM_IOCTL_VC4_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
0064
0065 struct drm_vc4_submit_rcl_surface {
0066     __u32 hindex; /* Handle index, or ~0 if not present. */
0067     __u32 offset; /* Offset to start of buffer. */
0068     /*
0069      * Bits for either render config (color_write) or load/store packet.
0070      * Bits should all be 0 for MSAA load/stores.
0071      */
0072     __u16 bits;
0073
0074 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES     (1 << 0)
0075     __u16 flags;
0076 };
0077
0078 /**
0079  * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
0080  * engine.
0081  *
0082  * Drivers typically use GPU BOs to store batchbuffers / command lists and
0083  * their associated state.  However, because the VC4 lacks an MMU, we have to
0084  * do validation of memory accesses by the GPU commands.  If we were to store
0085  * our commands in BOs, we'd need to do uncached readback from them to do the
0086  * validation process, which is too expensive.  Instead, userspace accumulates
0087  * commands and associated state in plain memory, then the kernel copies the
0088  * data to its own address space, and then validates and stores it in a GPU
0089  * BO.
0090  */
0091 struct drm_vc4_submit_cl {
0092     /* Pointer to the binner command list.
0093      *
0094      * This is the first set of commands executed, which runs the
0095      * coordinate shader to determine where primitives land on the screen,
0096      * then writes out the state updates and draw calls necessary per tile
0097      * to the tile allocation BO.
0098      */
0099     __u64 bin_cl;
0100
0101     /* Pointer to the shader records.
0102      *
0103      * Shader records are the structures read by the hardware that contain
0104      * pointers to uniforms, shaders, and vertex attributes.  The
0105      * reference to the shader record has enough information to determine
0106      * how many pointers are necessary (fixed number for shaders/uniforms,
0107      * and an attribute count), so those BO indices into bo_handles are
0108      * just stored as __u32s before each shader record passed in.
0109      */
0110     __u64 shader_rec;
0111
0112     /* Pointer to uniform data and texture handles for the textures
0113      * referenced by the shader.
0114      *
0115      * For each shader state record, there is a set of uniform data in the
0116      * order referenced by the record (FS, VS, then CS).  Each set of
0117      * uniform data has a __u32 index into bo_handles per texture
0118      * sample operation, in the order the QPU_W_TMUn_S writes appear in
0119      * the program.  Following the texture BO handle indices is the actual
0120      * uniform data.
0121      *
0122      * The individual uniform state blocks don't have sizes passed in,
0123      * because the kernel has to determine the sizes anyway during shader
0124      * code validation.
0125      */
0126     __u64 uniforms;
0127     __u64 bo_handles;
0128
0129     /* Size in bytes of the binner command list. */
0130     __u32 bin_cl_size;
0131     /* Size in bytes of the set of shader records. */
0132     __u32 shader_rec_size;
0133     /* Number of shader records.
0134      *
0135      * This could just be computed from the contents of shader_records and
0136      * the address bits of references to them from the bin CL, but it
0137      * keeps the kernel from having to resize some allocations it makes.
0138      */
0139     __u32 shader_rec_count;
0140     /* Size in bytes of the uniform state. */
0141     __u32 uniforms_size;
0142
0143     /* Number of BO handles passed in (size is that times 4). */
0144     __u32 bo_handle_count;
0145
0146     /* RCL setup: */
0147     __u16 width;
0148     __u16 height;
0149     __u8 min_x_tile;
0150     __u8 min_y_tile;
0151     __u8 max_x_tile;
0152     __u8 max_y_tile;
0153     struct drm_vc4_submit_rcl_surface color_read;
0154     struct drm_vc4_submit_rcl_surface color_write;
0155     struct drm_vc4_submit_rcl_surface zs_read;
0156     struct drm_vc4_submit_rcl_surface zs_write;
0157     struct drm_vc4_submit_rcl_surface msaa_color_write;
0158     struct drm_vc4_submit_rcl_surface msaa_zs_write;
0159     __u32 clear_color[2];
0160     __u32 clear_z;
0161     __u8 clear_s;
0162
0163     __u32 pad:24;
0164
0165 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR           (1 << 0)
0166 /* By default, the kernel gets to choose the order that the tiles are
0167  * rendered in.  If this is set, then the tiles will be rendered in a
0168  * raster order, with the right-to-left vs left-to-right and
0169  * top-to-bottom vs bottom-to-top dictated by
0170  * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*.  This allows overlapping
0171  * blits to be implemented using the 3D engine.
0172  */
0173 #define VC4_SUBMIT_CL_FIXED_RCL_ORDER           (1 << 1)
0174 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X        (1 << 2)
0175 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y        (1 << 3)
0176     __u32 flags;
0177
0178     /* Returned value of the seqno of this render job (for the
0179      * wait ioctl).
0180      */
0181     __u64 seqno;
0182
0183     /* ID of the perfmon to attach to this job. 0 means no perfmon. */
0184     __u32 perfmonid;
0185
0186     /* Syncobj handle to wait on. If set, processing of this render job
0187      * will not start until the syncobj is signaled. 0 means ignore.
0188      */
0189     __u32 in_sync;
0190
0191     /* Syncobj handle to export fence to. If set, the fence in the syncobj
0192      * will be replaced with a fence that signals upon completion of this
0193      * render job. 0 means ignore.
0194      */
0195     __u32 out_sync;
0196
0197     __u32 pad2;
0198 };
0199
0200 /**
0201  * struct drm_vc4_wait_seqno - ioctl argument for waiting for
0202  * DRM_VC4_SUBMIT_CL completion using its returned seqno.
0203  *
0204  * timeout_ns is the timeout in nanoseconds, where "0" means "don't
0205  * block, just return the status."
0206  */
0207 struct drm_vc4_wait_seqno {
0208     __u64 seqno;
0209     __u64 timeout_ns;
0210 };
0211
0212 /**
0213  * struct drm_vc4_wait_bo - ioctl argument for waiting for
0214  * completion of the last DRM_VC4_SUBMIT_CL on a BO.
0215  *
0216  * This is useful for cases where multiple processes might be
0217  * rendering to a BO and you want to wait for all rendering to be
0218  * completed.
0219  */
0220 struct drm_vc4_wait_bo {
0221     __u32 handle;
0222     __u32 pad;
0223     __u64 timeout_ns;
0224 };
0225
0226 /**
0227  * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
0228  *
0229  * There are currently no values for the flags argument, but it may be
0230  * used in a future extension.
0231  */
0232 struct drm_vc4_create_bo {
0233     __u32 size;
0234     __u32 flags;
0235     /** Returned GEM handle for the BO. */
0236     __u32 handle;
0237     __u32 pad;
0238 };
0239
0240 /**
0241  * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
0242  *
0243  * This doesn't actually perform an mmap.  Instead, it returns the
0244  * offset you need to use in an mmap on the DRM device node.  This
0245  * means that tools like valgrind end up knowing about the mapped
0246  * memory.
0247  *
0248  * There are currently no values for the flags argument, but it may be
0249  * used in a future extension.
0250  */
0251 struct drm_vc4_mmap_bo {
0252     /** Handle for the object being mapped. */
0253     __u32 handle;
0254     __u32 flags;
0255     /** offset into the drm node to use for subsequent mmap call. */
0256     __u64 offset;
0257 };
0258
0259 /**
0260  * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
0261  * shader BOs.
0262  *
0263  * Since allowing a shader to be overwritten while it's also being
0264  * executed from would allow privlege escalation, shaders must be
0265  * created using this ioctl, and they can't be mmapped later.
0266  */
0267 struct drm_vc4_create_shader_bo {
0268     /* Size of the data argument. */
0269     __u32 size;
0270     /* Flags, currently must be 0. */
0271     __u32 flags;
0272
0273     /* Pointer to the data. */
0274     __u64 data;
0275
0276     /** Returned GEM handle for the BO. */
0277     __u32 handle;
0278     /* Pad, must be 0. */
0279     __u32 pad;
0280 };
0281
0282 struct drm_vc4_get_hang_state_bo {
0283     __u32 handle;
0284     __u32 paddr;
0285     __u32 size;
0286     __u32 pad;
0287 };
0288
0289 /**
0290  * struct drm_vc4_hang_state - ioctl argument for collecting state
0291  * from a GPU hang for analysis.
0292 */
0293 struct drm_vc4_get_hang_state {
0294     /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
0295     __u64 bo;
0296     /**
0297      * On input, the size of the bo array.  Output is the number
0298      * of bos to be returned.
0299      */
0300     __u32 bo_count;
0301
0302     __u32 start_bin, start_render;
0303
0304     __u32 ct0ca, ct0ea;
0305     __u32 ct1ca, ct1ea;
0306     __u32 ct0cs, ct1cs;
0307     __u32 ct0ra0, ct1ra0;
0308
0309     __u32 bpca, bpcs;
0310     __u32 bpoa, bpos;
0311
0312     __u32 vpmbase;
0313
0314     __u32 dbge;
0315     __u32 fdbgo;
0316     __u32 fdbgb;
0317     __u32 fdbgr;
0318     __u32 fdbgs;
0319     __u32 errstat;
0320
0321     /* Pad that we may save more registers into in the future. */
0322     __u32 pad[16];
0323 };
0324
0325 #define DRM_VC4_PARAM_V3D_IDENT0        0
0326 #define DRM_VC4_PARAM_V3D_IDENT1        1
0327 #define DRM_VC4_PARAM_V3D_IDENT2        2
0328 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES     3
0329 #define DRM_VC4_PARAM_SUPPORTS_ETC1     4
0330 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS  5
0331 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER  6
0332 #define DRM_VC4_PARAM_SUPPORTS_MADVISE      7
0333 #define DRM_VC4_PARAM_SUPPORTS_PERFMON      8
0334
0335 struct drm_vc4_get_param {
0336     __u32 param;
0337     __u32 pad;
0338     __u64 value;
0339 };
0340
0341 struct drm_vc4_get_tiling {
0342     __u32 handle;
0343     __u32 flags;
0344     __u64 modifier;
0345 };
0346
0347 struct drm_vc4_set_tiling {
0348     __u32 handle;
0349     __u32 flags;
0350     __u64 modifier;
0351 };
0352
0353 /**
0354  * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
0355  */
0356 struct drm_vc4_label_bo {
0357     __u32 handle;
0358     __u32 len;
0359     __u64 name;
0360 };
0361
0362 /*
0363  * States prefixed with '__' are internal states and cannot be passed to the
0364  * DRM_IOCTL_VC4_GEM_MADVISE ioctl.
0365  */
0366 #define VC4_MADV_WILLNEED           0
0367 #define VC4_MADV_DONTNEED           1
0368 #define __VC4_MADV_PURGED           2
0369 #define __VC4_MADV_NOTSUPP          3
0370
0371 struct drm_vc4_gem_madvise {
0372     __u32 handle;
0373     __u32 madv;
0374     __u32 retained;
0375     __u32 pad;
0376 };
0377
0378 enum {
0379     VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
0380     VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
0381     VC4_PERFCNT_FEP_CLIPPED_QUADS,
0382     VC4_PERFCNT_FEP_VALID_QUADS,
0383     VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
0384     VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
0385     VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
0386     VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
0387     VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
0388     VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
0389     VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
0390     VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
0391     VC4_PERFCNT_PSE_PRIMS_REVERSED,
0392     VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
0393     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
0394     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
0395     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
0396     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
0397     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
0398     VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
0399     VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
0400     VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
0401     VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
0402     VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
0403     VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
0404     VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
0405     VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
0406     VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
0407     VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
0408     VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
0409     VC4_PERFCNT_NUM_EVENTS,
0410 };
0411
0412 #define DRM_VC4_MAX_PERF_COUNTERS   16
0413
0414 struct drm_vc4_perfmon_create {
0415     __u32 id;
0416     __u32 ncounters;
0417     __u8 events[DRM_VC4_MAX_PERF_COUNTERS];
0418 };
0419
0420 struct drm_vc4_perfmon_destroy {
0421     __u32 id;
0422 };
0423
0424 /*
0425  * Returns the values of the performance counters tracked by this
0426  * perfmon (as an array of ncounters u64 values).
0427  *
0428  * No implicit synchronization is performed, so the user has to
0429  * guarantee that any jobs using this perfmon have already been
0430  * completed  (probably by blocking on the seqno returned by the
0431  * last exec that used the perfmon).
0432  */
0433 struct drm_vc4_perfmon_get_values {
0434     __u32 id;
0435     __u64 values_ptr;
0436 };
0437
0438 #if defined(__cplusplus)
0439 }
0440 #endif
0441
0442 #endif /* _VC4_DRM_H_ */