include/libdrm/radeon_surface.h

0001 /*
0002  * Copyright © 2011 Red Hat All Rights Reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining
0005  * a copy of this software and associated documentation files (the
0006  * "Software"), to deal in the Software without restriction, including
0007  * without limitation the rights to use, copy, modify, merge, publish,
0008  * distribute, sub license, and/or sell copies of the Software, and to
0009  * permit persons to whom the Software is furnished to do so, subject to
0010  * the following conditions:
0011  *
0012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0013  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0014  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0015  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
0016  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0017  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0019  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * The above copyright notice and this permission notice (including the
0022  * next paragraph) shall be included in all copies or substantial portions
0023  * of the Software.
0024  */
0025 /*
0026  * Authors:
0027  *      Jérôme Glisse <jglisse@redhat.com>
0028  */
0029 #ifndef RADEON_SURFACE_H
0030 #define RADEON_SURFACE_H
0031
0032 /* Note :
0033  *
0034  * For texture array, the n layer are stored one after the other within each
0035  * mipmap level. 0 value for field than can be hint is always valid.
0036  */
0037
0038 #define RADEON_SURF_MAX_LEVEL                   32
0039
0040 #define RADEON_SURF_TYPE_MASK                   0xFF
0041 #define RADEON_SURF_TYPE_SHIFT                  0
0042 #define     RADEON_SURF_TYPE_1D                     0
0043 #define     RADEON_SURF_TYPE_2D                     1
0044 #define     RADEON_SURF_TYPE_3D                     2
0045 #define     RADEON_SURF_TYPE_CUBEMAP                3
0046 #define     RADEON_SURF_TYPE_1D_ARRAY               4
0047 #define     RADEON_SURF_TYPE_2D_ARRAY               5
0048 #define RADEON_SURF_MODE_MASK                   0xFF
0049 #define RADEON_SURF_MODE_SHIFT                  8
0050 #define     RADEON_SURF_MODE_LINEAR                 0
0051 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
0052 #define     RADEON_SURF_MODE_1D                     2
0053 #define     RADEON_SURF_MODE_2D                     3
0054 #define RADEON_SURF_SCANOUT                     (1 << 16)
0055 #define RADEON_SURF_ZBUFFER                     (1 << 17)
0056 #define RADEON_SURF_SBUFFER                     (1 << 18)
0057 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
0058 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
0059 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
0060 #define RADEON_SURF_FMASK                       (1 << 21)
0061
0062 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
0063 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
0064 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
0065
0066 /* first field up to mode need to match r6 struct so that we can reuse
0067  * same function for linear & linear aligned
0068  */
0069 struct radeon_surface_level {
0070     uint64_t                    offset;
0071     uint64_t                    slice_size;
0072     uint32_t                    npix_x;
0073     uint32_t                    npix_y;
0074     uint32_t                    npix_z;
0075     uint32_t                    nblk_x;
0076     uint32_t                    nblk_y;
0077     uint32_t                    nblk_z;
0078     uint32_t                    pitch_bytes;
0079     uint32_t                    mode;
0080 };
0081
0082 enum si_tiling_mode {
0083     SI_TILING_AUTO = 0,
0084
0085     SI_TILING_COLOR_1D,
0086     SI_TILING_COLOR_1D_SCANOUT,
0087     SI_TILING_COLOR_2D_8BPP,
0088     SI_TILING_COLOR_2D_16BPP,
0089     SI_TILING_COLOR_2D_32BPP,
0090     SI_TILING_COLOR_2D_64BPP,
0091     SI_TILING_COLOR_2D_SCANOUT_16BPP,
0092     SI_TILING_COLOR_2D_SCANOUT_32BPP,
0093     SI_TILING_COLOR_LINEAR,
0094
0095     SI_TILING_STENCIL_1D,
0096     SI_TILING_STENCIL_2D,
0097     SI_TILING_STENCIL_2D_2AA,
0098     SI_TILING_STENCIL_2D_4AA,
0099     SI_TILING_STENCIL_2D_8AA,
0100
0101     SI_TILING_DEPTH_1D,
0102     SI_TILING_DEPTH_2D,
0103     SI_TILING_DEPTH_2D_2AA,
0104     SI_TILING_DEPTH_2D_4AA,
0105     SI_TILING_DEPTH_2D_8AA,
0106
0107     SI_TILING_LAST_MODE,
0108 };
0109
0110 struct radeon_surface {
0111     uint32_t                    npix_x;
0112     uint32_t                    npix_y;
0113     uint32_t                    npix_z;
0114     uint32_t                    blk_w;
0115     uint32_t                    blk_h;
0116     uint32_t                    blk_d;
0117     uint32_t                    array_size;
0118     uint32_t                    last_level;
0119     uint32_t                    bpe;
0120     uint32_t                    nsamples;
0121     uint32_t                    flags;
0122     /* Following is updated/fill by the allocator. It's allowed to
0123      * set some of the value but they are use as hint and can be
0124      * overridden (things lile bankw/bankh on evergreen for
0125      * instance).
0126      */
0127     uint64_t                    bo_size;
0128     uint64_t                    bo_alignment;
0129     /* apply to eg */
0130     uint32_t                    bankw;
0131     uint32_t                    bankh;
0132     uint32_t                    mtilea;
0133     uint32_t                    tile_split;
0134     uint32_t                    stencil_tile_split;
0135     uint64_t                    stencil_offset;
0136     struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
0137     struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
0138     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
0139     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
0140 };
0141
0142 struct radeon_surface_manager *radeon_surface_manager_new(int fd);
0143 void radeon_surface_manager_free(struct radeon_surface_manager *surf_man);
0144 int radeon_surface_init(struct radeon_surface_manager *surf_man,
0145                         struct radeon_surface *surf);
0146 int radeon_surface_best(struct radeon_surface_manager *surf_man,
0147                         struct radeon_surface *surf);
0148
0149 #endif