File indexing completed on 2025-01-18 10:01:51
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033 #ifndef __RADEON_DRM_H__
0034 #define __RADEON_DRM_H__
0035
0036 #include "drm.h"
0037
0038 #if defined(__cplusplus)
0039 extern "C" {
0040 #endif
0041
0042
0043
0044
0045 #ifndef __RADEON_SAREA_DEFINES__
0046 #define __RADEON_SAREA_DEFINES__
0047
0048
0049
0050
0051 #define RADEON_UPLOAD_CONTEXT 0x00000001
0052 #define RADEON_UPLOAD_VERTFMT 0x00000002
0053 #define RADEON_UPLOAD_LINE 0x00000004
0054 #define RADEON_UPLOAD_BUMPMAP 0x00000008
0055 #define RADEON_UPLOAD_MASKS 0x00000010
0056 #define RADEON_UPLOAD_VIEWPORT 0x00000020
0057 #define RADEON_UPLOAD_SETUP 0x00000040
0058 #define RADEON_UPLOAD_TCL 0x00000080
0059 #define RADEON_UPLOAD_MISC 0x00000100
0060 #define RADEON_UPLOAD_TEX0 0x00000200
0061 #define RADEON_UPLOAD_TEX1 0x00000400
0062 #define RADEON_UPLOAD_TEX2 0x00000800
0063 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000
0064 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000
0065 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000
0066 #define RADEON_UPLOAD_CLIPRECTS 0x00008000
0067 #define RADEON_REQUIRE_QUIESCENCE 0x00010000
0068 #define RADEON_UPLOAD_ZBIAS 0x00020000
0069 #define RADEON_UPLOAD_ALL 0x003effff
0070 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
0071
0072
0073
0074
0075
0076 #define RADEON_EMIT_PP_MISC 0
0077 #define RADEON_EMIT_PP_CNTL 1
0078 #define RADEON_EMIT_RB3D_COLORPITCH 2
0079 #define RADEON_EMIT_RE_LINE_PATTERN 3
0080 #define RADEON_EMIT_SE_LINE_WIDTH 4
0081 #define RADEON_EMIT_PP_LUM_MATRIX 5
0082 #define RADEON_EMIT_PP_ROT_MATRIX_0 6
0083 #define RADEON_EMIT_RB3D_STENCILREFMASK 7
0084 #define RADEON_EMIT_SE_VPORT_XSCALE 8
0085 #define RADEON_EMIT_SE_CNTL 9
0086 #define RADEON_EMIT_SE_CNTL_STATUS 10
0087 #define RADEON_EMIT_RE_MISC 11
0088 #define RADEON_EMIT_PP_TXFILTER_0 12
0089 #define RADEON_EMIT_PP_BORDER_COLOR_0 13
0090 #define RADEON_EMIT_PP_TXFILTER_1 14
0091 #define RADEON_EMIT_PP_BORDER_COLOR_1 15
0092 #define RADEON_EMIT_PP_TXFILTER_2 16
0093 #define RADEON_EMIT_PP_BORDER_COLOR_2 17
0094 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18
0095 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19
0096 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20
0097 #define R200_EMIT_PP_TXCBLEND_0 21
0098 #define R200_EMIT_PP_TXCBLEND_1 22
0099 #define R200_EMIT_PP_TXCBLEND_2 23
0100 #define R200_EMIT_PP_TXCBLEND_3 24
0101 #define R200_EMIT_PP_TXCBLEND_4 25
0102 #define R200_EMIT_PP_TXCBLEND_5 26
0103 #define R200_EMIT_PP_TXCBLEND_6 27
0104 #define R200_EMIT_PP_TXCBLEND_7 28
0105 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29
0106 #define R200_EMIT_TFACTOR_0 30
0107 #define R200_EMIT_VTX_FMT_0 31
0108 #define R200_EMIT_VAP_CTL 32
0109 #define R200_EMIT_MATRIX_SELECT_0 33
0110 #define R200_EMIT_TEX_PROC_CTL_2 34
0111 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35
0112 #define R200_EMIT_PP_TXFILTER_0 36
0113 #define R200_EMIT_PP_TXFILTER_1 37
0114 #define R200_EMIT_PP_TXFILTER_2 38
0115 #define R200_EMIT_PP_TXFILTER_3 39
0116 #define R200_EMIT_PP_TXFILTER_4 40
0117 #define R200_EMIT_PP_TXFILTER_5 41
0118 #define R200_EMIT_PP_TXOFFSET_0 42
0119 #define R200_EMIT_PP_TXOFFSET_1 43
0120 #define R200_EMIT_PP_TXOFFSET_2 44
0121 #define R200_EMIT_PP_TXOFFSET_3 45
0122 #define R200_EMIT_PP_TXOFFSET_4 46
0123 #define R200_EMIT_PP_TXOFFSET_5 47
0124 #define R200_EMIT_VTE_CNTL 48
0125 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49
0126 #define R200_EMIT_PP_TAM_DEBUG3 50
0127 #define R200_EMIT_PP_CNTL_X 51
0128 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52
0129 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53
0130 #define R200_EMIT_RE_SCISSOR_TL_0 54
0131 #define R200_EMIT_RE_SCISSOR_TL_1 55
0132 #define R200_EMIT_RE_SCISSOR_TL_2 56
0133 #define R200_EMIT_SE_VAP_CNTL_STATUS 57
0134 #define R200_EMIT_SE_VTX_STATE_CNTL 58
0135 #define R200_EMIT_RE_POINTSIZE 59
0136 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60
0137 #define R200_EMIT_PP_CUBIC_FACES_0 61
0138 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62
0139 #define R200_EMIT_PP_CUBIC_FACES_1 63
0140 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64
0141 #define R200_EMIT_PP_CUBIC_FACES_2 65
0142 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66
0143 #define R200_EMIT_PP_CUBIC_FACES_3 67
0144 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68
0145 #define R200_EMIT_PP_CUBIC_FACES_4 69
0146 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70
0147 #define R200_EMIT_PP_CUBIC_FACES_5 71
0148 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72
0149 #define RADEON_EMIT_PP_TEX_SIZE_0 73
0150 #define RADEON_EMIT_PP_TEX_SIZE_1 74
0151 #define RADEON_EMIT_PP_TEX_SIZE_2 75
0152 #define R200_EMIT_RB3D_BLENDCOLOR 76
0153 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
0154 #define RADEON_EMIT_PP_CUBIC_FACES_0 78
0155 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
0156 #define RADEON_EMIT_PP_CUBIC_FACES_1 80
0157 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
0158 #define RADEON_EMIT_PP_CUBIC_FACES_2 82
0159 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
0160 #define R200_EMIT_PP_TRI_PERF_CNTL 84
0161 #define R200_EMIT_PP_AFS_0 85
0162 #define R200_EMIT_PP_AFS_1 86
0163 #define R200_EMIT_ATF_TFACTOR 87
0164 #define R200_EMIT_PP_TXCTLALL_0 88
0165 #define R200_EMIT_PP_TXCTLALL_1 89
0166 #define R200_EMIT_PP_TXCTLALL_2 90
0167 #define R200_EMIT_PP_TXCTLALL_3 91
0168 #define R200_EMIT_PP_TXCTLALL_4 92
0169 #define R200_EMIT_PP_TXCTLALL_5 93
0170 #define R200_EMIT_VAP_PVS_CNTL 94
0171 #define RADEON_MAX_STATE_PACKETS 95
0172
0173
0174
0175
0176 #define RADEON_CMD_PACKET 1
0177 #define RADEON_CMD_SCALARS 2
0178 #define RADEON_CMD_VECTORS 3
0179 #define RADEON_CMD_DMA_DISCARD 4
0180 #define RADEON_CMD_PACKET3 5
0181 #define RADEON_CMD_PACKET3_CLIP 6
0182 #define RADEON_CMD_SCALARS2 7
0183 #define RADEON_CMD_WAIT 8
0184
0185
0186 #define RADEON_CMD_VECLINEAR 9
0187
0188 typedef union {
0189 int i;
0190 struct {
0191 unsigned char cmd_type, pad0, pad1, pad2;
0192 } header;
0193 struct {
0194 unsigned char cmd_type, packet_id, pad0, pad1;
0195 } packet;
0196 struct {
0197 unsigned char cmd_type, offset, stride, count;
0198 } scalars;
0199 struct {
0200 unsigned char cmd_type, offset, stride, count;
0201 } vectors;
0202 struct {
0203 unsigned char cmd_type, addr_lo, addr_hi, count;
0204 } veclinear;
0205 struct {
0206 unsigned char cmd_type, buf_idx, pad0, pad1;
0207 } dma;
0208 struct {
0209 unsigned char cmd_type, flags, pad0, pad1;
0210 } wait;
0211 } drm_radeon_cmd_header_t;
0212
0213 #define RADEON_WAIT_2D 0x1
0214 #define RADEON_WAIT_3D 0x2
0215
0216
0217
0218 #define R300_CMD_PACKET3_CLEAR 0
0219 #define R300_CMD_PACKET3_RAW 1
0220
0221
0222
0223
0224
0225 #define R300_CMD_PACKET0 1
0226 #define R300_CMD_VPU 2
0227 #define R300_CMD_PACKET3 3
0228 #define R300_CMD_END3D 4
0229 #define R300_CMD_CP_DELAY 5
0230 #define R300_CMD_DMA_DISCARD 6
0231 #define R300_CMD_WAIT 7
0232 # define R300_WAIT_2D 0x1
0233 # define R300_WAIT_3D 0x2
0234
0235
0236
0237
0238
0239
0240 # define R300_WAIT_2D_CLEAN 0x3
0241 # define R300_WAIT_3D_CLEAN 0x4
0242
0243 # define R300_NEW_WAIT_2D_3D 0x3
0244 # define R300_NEW_WAIT_2D_2D_CLEAN 0x4
0245 # define R300_NEW_WAIT_3D_3D_CLEAN 0x6
0246 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
0247
0248 #define R300_CMD_SCRATCH 8
0249 #define R300_CMD_R500FP 9
0250
0251 typedef union {
0252 unsigned int u;
0253 struct {
0254 unsigned char cmd_type, pad0, pad1, pad2;
0255 } header;
0256 struct {
0257 unsigned char cmd_type, count, reglo, reghi;
0258 } packet0;
0259 struct {
0260 unsigned char cmd_type, count, adrlo, adrhi;
0261 } vpu;
0262 struct {
0263 unsigned char cmd_type, packet, pad0, pad1;
0264 } packet3;
0265 struct {
0266 unsigned char cmd_type, packet;
0267 unsigned short count;
0268 } delay;
0269 struct {
0270 unsigned char cmd_type, buf_idx, pad0, pad1;
0271 } dma;
0272 struct {
0273 unsigned char cmd_type, flags, pad0, pad1;
0274 } wait;
0275 struct {
0276 unsigned char cmd_type, reg, n_bufs, flags;
0277 } scratch;
0278 struct {
0279 unsigned char cmd_type, count, adrlo, adrhi_flags;
0280 } r500fp;
0281 } drm_r300_cmd_header_t;
0282
0283 #define RADEON_FRONT 0x1
0284 #define RADEON_BACK 0x2
0285 #define RADEON_DEPTH 0x4
0286 #define RADEON_STENCIL 0x8
0287 #define RADEON_CLEAR_FASTZ 0x80000000
0288 #define RADEON_USE_HIERZ 0x40000000
0289 #define RADEON_USE_COMP_ZBUF 0x20000000
0290
0291 #define R500FP_CONSTANT_TYPE (1 << 1)
0292 #define R500FP_CONSTANT_CLAMP (1 << 2)
0293
0294
0295
0296 #define RADEON_POINTS 0x1
0297 #define RADEON_LINES 0x2
0298 #define RADEON_LINE_STRIP 0x3
0299 #define RADEON_TRIANGLES 0x4
0300 #define RADEON_TRIANGLE_FAN 0x5
0301 #define RADEON_TRIANGLE_STRIP 0x6
0302
0303
0304
0305 #define RADEON_BUFFER_SIZE 65536
0306
0307
0308
0309 #define RADEON_INDEX_PRIM_OFFSET 20
0310
0311 #define RADEON_SCRATCH_REG_OFFSET 32
0312
0313 #define R600_SCRATCH_REG_OFFSET 256
0314
0315 #define RADEON_NR_SAREA_CLIPRECTS 12
0316
0317
0318
0319
0320 #define RADEON_LOCAL_TEX_HEAP 0
0321 #define RADEON_GART_TEX_HEAP 1
0322 #define RADEON_NR_TEX_HEAPS 2
0323 #define RADEON_NR_TEX_REGIONS 64
0324 #define RADEON_LOG_TEX_GRANULARITY 16
0325
0326 #define RADEON_MAX_TEXTURE_LEVELS 12
0327 #define RADEON_MAX_TEXTURE_UNITS 3
0328
0329 #define RADEON_MAX_SURFACES 8
0330
0331
0332
0333
0334 #define RADEON_OFFSET_SHIFT 10
0335 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
0336 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
0337
0338 #endif
0339
0340 typedef struct {
0341 unsigned int red;
0342 unsigned int green;
0343 unsigned int blue;
0344 unsigned int alpha;
0345 } radeon_color_regs_t;
0346
0347 typedef struct {
0348
0349 unsigned int pp_misc;
0350 unsigned int pp_fog_color;
0351 unsigned int re_solid_color;
0352 unsigned int rb3d_blendcntl;
0353 unsigned int rb3d_depthoffset;
0354 unsigned int rb3d_depthpitch;
0355 unsigned int rb3d_zstencilcntl;
0356
0357 unsigned int pp_cntl;
0358 unsigned int rb3d_cntl;
0359 unsigned int rb3d_coloroffset;
0360 unsigned int re_width_height;
0361 unsigned int rb3d_colorpitch;
0362 unsigned int se_cntl;
0363
0364
0365 unsigned int se_coord_fmt;
0366
0367
0368 unsigned int re_line_pattern;
0369 unsigned int re_line_state;
0370
0371 unsigned int se_line_width;
0372
0373
0374 unsigned int pp_lum_matrix;
0375
0376 unsigned int pp_rot_matrix_0;
0377 unsigned int pp_rot_matrix_1;
0378
0379
0380 unsigned int rb3d_stencilrefmask;
0381 unsigned int rb3d_ropcntl;
0382 unsigned int rb3d_planemask;
0383
0384
0385 unsigned int se_vport_xscale;
0386 unsigned int se_vport_xoffset;
0387 unsigned int se_vport_yscale;
0388 unsigned int se_vport_yoffset;
0389 unsigned int se_vport_zscale;
0390 unsigned int se_vport_zoffset;
0391
0392
0393 unsigned int se_cntl_status;
0394
0395
0396 unsigned int re_top_left;
0397 unsigned int re_misc;
0398 } drm_radeon_context_regs_t;
0399
0400 typedef struct {
0401
0402 unsigned int se_zbias_factor;
0403 unsigned int se_zbias_constant;
0404 } drm_radeon_context2_regs_t;
0405
0406
0407
0408 typedef struct {
0409 unsigned int pp_txfilter;
0410 unsigned int pp_txformat;
0411 unsigned int pp_txoffset;
0412 unsigned int pp_txcblend;
0413 unsigned int pp_txablend;
0414 unsigned int pp_tfactor;
0415 unsigned int pp_border_color;
0416 } drm_radeon_texture_regs_t;
0417
0418 typedef struct {
0419 unsigned int start;
0420 unsigned int finish;
0421 unsigned int prim:8;
0422 unsigned int stateidx:8;
0423 unsigned int numverts:16;
0424 unsigned int vc_format;
0425 } drm_radeon_prim_t;
0426
0427 typedef struct {
0428 drm_radeon_context_regs_t context;
0429 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
0430 drm_radeon_context2_regs_t context2;
0431 unsigned int dirty;
0432 } drm_radeon_state_t;
0433
0434 typedef struct {
0435
0436
0437
0438
0439 drm_radeon_context_regs_t context_state;
0440 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
0441 unsigned int dirty;
0442 unsigned int vertsize;
0443 unsigned int vc_format;
0444
0445
0446
0447 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
0448 unsigned int nbox;
0449
0450
0451
0452 unsigned int last_frame;
0453 unsigned int last_dispatch;
0454 unsigned int last_clear;
0455
0456 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
0457 1];
0458 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
0459 int ctx_owner;
0460 int pfState;
0461 int pfCurrentPage;
0462 int crtc2_base;
0463 int tiling_enabled;
0464 } drm_radeon_sarea_t;
0465
0466
0467
0468
0469
0470
0471
0472
0473
0474
0475 #define DRM_RADEON_CP_INIT 0x00
0476 #define DRM_RADEON_CP_START 0x01
0477 #define DRM_RADEON_CP_STOP 0x02
0478 #define DRM_RADEON_CP_RESET 0x03
0479 #define DRM_RADEON_CP_IDLE 0x04
0480 #define DRM_RADEON_RESET 0x05
0481 #define DRM_RADEON_FULLSCREEN 0x06
0482 #define DRM_RADEON_SWAP 0x07
0483 #define DRM_RADEON_CLEAR 0x08
0484 #define DRM_RADEON_VERTEX 0x09
0485 #define DRM_RADEON_INDICES 0x0A
0486 #define DRM_RADEON_NOT_USED
0487 #define DRM_RADEON_STIPPLE 0x0C
0488 #define DRM_RADEON_INDIRECT 0x0D
0489 #define DRM_RADEON_TEXTURE 0x0E
0490 #define DRM_RADEON_VERTEX2 0x0F
0491 #define DRM_RADEON_CMDBUF 0x10
0492 #define DRM_RADEON_GETPARAM 0x11
0493 #define DRM_RADEON_FLIP 0x12
0494 #define DRM_RADEON_ALLOC 0x13
0495 #define DRM_RADEON_FREE 0x14
0496 #define DRM_RADEON_INIT_HEAP 0x15
0497 #define DRM_RADEON_IRQ_EMIT 0x16
0498 #define DRM_RADEON_IRQ_WAIT 0x17
0499 #define DRM_RADEON_CP_RESUME 0x18
0500 #define DRM_RADEON_SETPARAM 0x19
0501 #define DRM_RADEON_SURF_ALLOC 0x1a
0502 #define DRM_RADEON_SURF_FREE 0x1b
0503
0504 #define DRM_RADEON_GEM_INFO 0x1c
0505 #define DRM_RADEON_GEM_CREATE 0x1d
0506 #define DRM_RADEON_GEM_MMAP 0x1e
0507 #define DRM_RADEON_GEM_PREAD 0x21
0508 #define DRM_RADEON_GEM_PWRITE 0x22
0509 #define DRM_RADEON_GEM_SET_DOMAIN 0x23
0510 #define DRM_RADEON_GEM_WAIT_IDLE 0x24
0511 #define DRM_RADEON_CS 0x26
0512 #define DRM_RADEON_INFO 0x27
0513 #define DRM_RADEON_GEM_SET_TILING 0x28
0514 #define DRM_RADEON_GEM_GET_TILING 0x29
0515 #define DRM_RADEON_GEM_BUSY 0x2a
0516 #define DRM_RADEON_GEM_VA 0x2b
0517 #define DRM_RADEON_GEM_OP 0x2c
0518 #define DRM_RADEON_GEM_USERPTR 0x2d
0519
0520 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
0521 #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
0522 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
0523 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
0524 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
0525 #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
0526 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
0527 #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
0528 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
0529 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
0530 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
0531 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
0532 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
0533 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
0534 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
0535 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
0536 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
0537 #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
0538 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
0539 #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
0540 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
0541 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
0542 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
0543 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
0544 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
0545 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
0546 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
0547
0548 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
0549 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
0550 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
0551 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
0552 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
0553 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
0554 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
0555 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
0556 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
0557 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
0558 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
0559 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
0560 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
0561 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
0562 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
0563
0564 typedef struct drm_radeon_init {
0565 enum {
0566 RADEON_INIT_CP = 0x01,
0567 RADEON_CLEANUP_CP = 0x02,
0568 RADEON_INIT_R200_CP = 0x03,
0569 RADEON_INIT_R300_CP = 0x04,
0570 RADEON_INIT_R600_CP = 0x05
0571 } func;
0572 unsigned long sarea_priv_offset;
0573 int is_pci;
0574 int cp_mode;
0575 int gart_size;
0576 int ring_size;
0577 int usec_timeout;
0578
0579 unsigned int fb_bpp;
0580 unsigned int front_offset, front_pitch;
0581 unsigned int back_offset, back_pitch;
0582 unsigned int depth_bpp;
0583 unsigned int depth_offset, depth_pitch;
0584
0585 unsigned long fb_offset;
0586 unsigned long mmio_offset;
0587 unsigned long ring_offset;
0588 unsigned long ring_rptr_offset;
0589 unsigned long buffers_offset;
0590 unsigned long gart_textures_offset;
0591 } drm_radeon_init_t;
0592
0593 typedef struct drm_radeon_cp_stop {
0594 int flush;
0595 int idle;
0596 } drm_radeon_cp_stop_t;
0597
0598 typedef struct drm_radeon_fullscreen {
0599 enum {
0600 RADEON_INIT_FULLSCREEN = 0x01,
0601 RADEON_CLEANUP_FULLSCREEN = 0x02
0602 } func;
0603 } drm_radeon_fullscreen_t;
0604
0605 #define CLEAR_X1 0
0606 #define CLEAR_Y1 1
0607 #define CLEAR_X2 2
0608 #define CLEAR_Y2 3
0609 #define CLEAR_DEPTH 4
0610
0611 typedef union drm_radeon_clear_rect {
0612 float f[5];
0613 unsigned int ui[5];
0614 } drm_radeon_clear_rect_t;
0615
0616 typedef struct drm_radeon_clear {
0617 unsigned int flags;
0618 unsigned int clear_color;
0619 unsigned int clear_depth;
0620 unsigned int color_mask;
0621 unsigned int depth_mask;
0622 drm_radeon_clear_rect_t *depth_boxes;
0623 } drm_radeon_clear_t;
0624
0625 typedef struct drm_radeon_vertex {
0626 int prim;
0627 int idx;
0628 int count;
0629 int discard;
0630 } drm_radeon_vertex_t;
0631
0632 typedef struct drm_radeon_indices {
0633 int prim;
0634 int idx;
0635 int start;
0636 int end;
0637 int discard;
0638 } drm_radeon_indices_t;
0639
0640
0641
0642
0643
0644 typedef struct drm_radeon_vertex2 {
0645 int idx;
0646 int discard;
0647 int nr_states;
0648 drm_radeon_state_t *state;
0649 int nr_prims;
0650 drm_radeon_prim_t *prim;
0651 } drm_radeon_vertex2_t;
0652
0653
0654
0655
0656
0657
0658
0659
0660
0661
0662
0663 typedef struct drm_radeon_cmd_buffer {
0664 int bufsz;
0665 char *buf;
0666 int nbox;
0667 struct drm_clip_rect *boxes;
0668 } drm_radeon_cmd_buffer_t;
0669
0670 typedef struct drm_radeon_tex_image {
0671 unsigned int x, y;
0672 unsigned int width, height;
0673 const void *data;
0674 } drm_radeon_tex_image_t;
0675
0676 typedef struct drm_radeon_texture {
0677 unsigned int offset;
0678 int pitch;
0679 int format;
0680 int width;
0681 int height;
0682 drm_radeon_tex_image_t *image;
0683 } drm_radeon_texture_t;
0684
0685 typedef struct drm_radeon_stipple {
0686 unsigned int *mask;
0687 } drm_radeon_stipple_t;
0688
0689 typedef struct drm_radeon_indirect {
0690 int idx;
0691 int start;
0692 int end;
0693 int discard;
0694 } drm_radeon_indirect_t;
0695
0696
0697 #define RADEON_CARD_PCI 0
0698 #define RADEON_CARD_AGP 1
0699 #define RADEON_CARD_PCIE 2
0700
0701
0702
0703
0704 #define RADEON_PARAM_GART_BUFFER_OFFSET 1
0705 #define RADEON_PARAM_LAST_FRAME 2
0706 #define RADEON_PARAM_LAST_DISPATCH 3
0707 #define RADEON_PARAM_LAST_CLEAR 4
0708
0709 #define RADEON_PARAM_IRQ_NR 5
0710 #define RADEON_PARAM_GART_BASE 6
0711
0712 #define RADEON_PARAM_REGISTER_HANDLE 7
0713 #define RADEON_PARAM_STATUS_HANDLE 8
0714 #define RADEON_PARAM_SAREA_HANDLE 9
0715 #define RADEON_PARAM_GART_TEX_HANDLE 10
0716 #define RADEON_PARAM_SCRATCH_OFFSET 11
0717 #define RADEON_PARAM_CARD_TYPE 12
0718 #define RADEON_PARAM_VBLANK_CRTC 13
0719 #define RADEON_PARAM_FB_LOCATION 14
0720 #define RADEON_PARAM_NUM_GB_PIPES 15
0721 #define RADEON_PARAM_DEVICE_ID 16
0722 #define RADEON_PARAM_NUM_Z_PIPES 17
0723
0724 typedef struct drm_radeon_getparam {
0725 int param;
0726 void *value;
0727 } drm_radeon_getparam_t;
0728
0729
0730
0731 #define RADEON_MEM_REGION_GART 1
0732 #define RADEON_MEM_REGION_FB 2
0733
0734 typedef struct drm_radeon_mem_alloc {
0735 int region;
0736 int alignment;
0737 int size;
0738 int *region_offset;
0739 } drm_radeon_mem_alloc_t;
0740
0741 typedef struct drm_radeon_mem_free {
0742 int region;
0743 int region_offset;
0744 } drm_radeon_mem_free_t;
0745
0746 typedef struct drm_radeon_mem_init_heap {
0747 int region;
0748 int size;
0749 int start;
0750 } drm_radeon_mem_init_heap_t;
0751
0752
0753
0754 typedef struct drm_radeon_irq_emit {
0755 int *irq_seq;
0756 } drm_radeon_irq_emit_t;
0757
0758 typedef struct drm_radeon_irq_wait {
0759 int irq_seq;
0760 } drm_radeon_irq_wait_t;
0761
0762
0763
0764
0765
0766 typedef struct drm_radeon_setparam {
0767 unsigned int param;
0768 __s64 value;
0769 } drm_radeon_setparam_t;
0770
0771 #define RADEON_SETPARAM_FB_LOCATION 1
0772 #define RADEON_SETPARAM_SWITCH_TILING 2
0773 #define RADEON_SETPARAM_PCIGART_LOCATION 3
0774 #define RADEON_SETPARAM_NEW_MEMMAP 4
0775 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
0776 #define RADEON_SETPARAM_VBLANK_CRTC 6
0777
0778
0779 typedef struct drm_radeon_surface_alloc {
0780 unsigned int address;
0781 unsigned int size;
0782 unsigned int flags;
0783 } drm_radeon_surface_alloc_t;
0784
0785 typedef struct drm_radeon_surface_free {
0786 unsigned int address;
0787 } drm_radeon_surface_free_t;
0788
0789 #define DRM_RADEON_VBLANK_CRTC1 1
0790 #define DRM_RADEON_VBLANK_CRTC2 2
0791
0792
0793
0794
0795 #define RADEON_GEM_DOMAIN_CPU 0x1
0796 #define RADEON_GEM_DOMAIN_GTT 0x2
0797 #define RADEON_GEM_DOMAIN_VRAM 0x4
0798
0799 struct drm_radeon_gem_info {
0800 __u64 gart_size;
0801 __u64 vram_size;
0802 __u64 vram_visible;
0803 };
0804
0805 #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
0806 #define RADEON_GEM_GTT_UC (1 << 1)
0807 #define RADEON_GEM_GTT_WC (1 << 2)
0808
0809 #define RADEON_GEM_CPU_ACCESS (1 << 3)
0810
0811 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
0812
0813 struct drm_radeon_gem_create {
0814 __u64 size;
0815 __u64 alignment;
0816 __u32 handle;
0817 __u32 initial_domain;
0818 __u32 flags;
0819 };
0820
0821
0822
0823
0824
0825
0826 #define RADEON_GEM_USERPTR_READONLY (1 << 0)
0827 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
0828 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
0829 #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
0830
0831 struct drm_radeon_gem_userptr {
0832 __u64 addr;
0833 __u64 size;
0834 __u32 flags;
0835 __u32 handle;
0836 };
0837
0838 #define RADEON_TILING_MACRO 0x1
0839 #define RADEON_TILING_MICRO 0x2
0840 #define RADEON_TILING_SWAP_16BIT 0x4
0841 #define RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BIT
0842 #define RADEON_TILING_SWAP_32BIT 0x8
0843
0844 #define RADEON_TILING_SURFACE 0x10
0845 #define RADEON_TILING_MICRO_SQUARE 0x20
0846 #define RADEON_TILING_EG_BANKW_SHIFT 8
0847 #define RADEON_TILING_EG_BANKW_MASK 0xf
0848 #define RADEON_TILING_EG_BANKH_SHIFT 12
0849 #define RADEON_TILING_EG_BANKH_MASK 0xf
0850 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
0851 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
0852 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
0853 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
0854 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
0855 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
0856
0857 struct drm_radeon_gem_set_tiling {
0858 __u32 handle;
0859 __u32 tiling_flags;
0860 __u32 pitch;
0861 };
0862
0863 struct drm_radeon_gem_get_tiling {
0864 __u32 handle;
0865 __u32 tiling_flags;
0866 __u32 pitch;
0867 };
0868
0869 struct drm_radeon_gem_mmap {
0870 __u32 handle;
0871 __u32 pad;
0872 __u64 offset;
0873 __u64 size;
0874 __u64 addr_ptr;
0875 };
0876
0877 struct drm_radeon_gem_set_domain {
0878 __u32 handle;
0879 __u32 read_domains;
0880 __u32 write_domain;
0881 };
0882
0883 struct drm_radeon_gem_wait_idle {
0884 __u32 handle;
0885 __u32 pad;
0886 };
0887
0888 struct drm_radeon_gem_busy {
0889 __u32 handle;
0890 __u32 domain;
0891 };
0892
0893 struct drm_radeon_gem_pread {
0894
0895 __u32 handle;
0896 __u32 pad;
0897
0898 __u64 offset;
0899
0900 __u64 size;
0901
0902
0903 __u64 data_ptr;
0904 };
0905
0906 struct drm_radeon_gem_pwrite {
0907
0908 __u32 handle;
0909 __u32 pad;
0910
0911 __u64 offset;
0912
0913 __u64 size;
0914
0915
0916 __u64 data_ptr;
0917 };
0918
0919
0920 struct drm_radeon_gem_op {
0921 __u32 handle;
0922 __u32 op;
0923 __u64 value;
0924 };
0925
0926 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
0927 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
0928
0929 #define RADEON_VA_MAP 1
0930 #define RADEON_VA_UNMAP 2
0931
0932 #define RADEON_VA_RESULT_OK 0
0933 #define RADEON_VA_RESULT_ERROR 1
0934 #define RADEON_VA_RESULT_VA_EXIST 2
0935
0936 #define RADEON_VM_PAGE_VALID (1 << 0)
0937 #define RADEON_VM_PAGE_READABLE (1 << 1)
0938 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
0939 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
0940 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
0941
0942 struct drm_radeon_gem_va {
0943 __u32 handle;
0944 __u32 operation;
0945 __u32 vm_id;
0946 __u32 flags;
0947 __u64 offset;
0948 };
0949
0950 #define RADEON_CHUNK_ID_RELOCS 0x01
0951 #define RADEON_CHUNK_ID_IB 0x02
0952 #define RADEON_CHUNK_ID_FLAGS 0x03
0953 #define RADEON_CHUNK_ID_CONST_IB 0x04
0954
0955
0956 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
0957 #define RADEON_CS_USE_VM 0x02
0958 #define RADEON_CS_END_OF_FRAME 0x04
0959
0960 #define RADEON_CS_RING_GFX 0
0961 #define RADEON_CS_RING_COMPUTE 1
0962 #define RADEON_CS_RING_DMA 2
0963 #define RADEON_CS_RING_UVD 3
0964 #define RADEON_CS_RING_VCE 4
0965
0966
0967
0968 struct drm_radeon_cs_chunk {
0969 __u32 chunk_id;
0970 __u32 length_dw;
0971 __u64 chunk_data;
0972 };
0973
0974
0975 #define RADEON_RELOC_PRIO_MASK (0xf << 0)
0976
0977 struct drm_radeon_cs_reloc {
0978 __u32 handle;
0979 __u32 read_domains;
0980 __u32 write_domain;
0981 __u32 flags;
0982 };
0983
0984 struct drm_radeon_cs {
0985 __u32 num_chunks;
0986 __u32 cs_id;
0987
0988 __u64 chunks;
0989
0990 __u64 gart_limit;
0991 __u64 vram_limit;
0992 };
0993
0994 #define RADEON_INFO_DEVICE_ID 0x00
0995 #define RADEON_INFO_NUM_GB_PIPES 0x01
0996 #define RADEON_INFO_NUM_Z_PIPES 0x02
0997 #define RADEON_INFO_ACCEL_WORKING 0x03
0998 #define RADEON_INFO_CRTC_FROM_ID 0x04
0999 #define RADEON_INFO_ACCEL_WORKING2 0x05
1000 #define RADEON_INFO_TILING_CONFIG 0x06
1001 #define RADEON_INFO_WANT_HYPERZ 0x07
1002 #define RADEON_INFO_WANT_CMASK 0x08
1003 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09
1004 #define RADEON_INFO_NUM_BACKENDS 0x0a
1005 #define RADEON_INFO_NUM_TILE_PIPES 0x0b
1006 #define RADEON_INFO_FUSION_GART_WORKING 0x0c
1007 #define RADEON_INFO_BACKEND_MAP 0x0d
1008
1009 #define RADEON_INFO_VA_START 0x0e
1010
1011 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
1012
1013 #define RADEON_INFO_MAX_PIPES 0x10
1014
1015 #define RADEON_INFO_TIMESTAMP 0x11
1016
1017 #define RADEON_INFO_MAX_SE 0x12
1018
1019 #define RADEON_INFO_MAX_SH_PER_SE 0x13
1020
1021 #define RADEON_INFO_FASTFB_WORKING 0x14
1022
1023 #define RADEON_INFO_RING_WORKING 0x15
1024
1025 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
1026
1027 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
1028
1029 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
1030
1031 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
1032
1033 #define RADEON_INFO_MAX_SCLK 0x1a
1034
1035 #define RADEON_INFO_VCE_FW_VERSION 0x1b
1036
1037 #define RADEON_INFO_VCE_FB_VERSION 0x1c
1038 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d
1039 #define RADEON_INFO_VRAM_USAGE 0x1e
1040 #define RADEON_INFO_GTT_USAGE 0x1f
1041 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
1042 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21
1043 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22
1044 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23
1045 #define RADEON_INFO_READ_REG 0x24
1046 #define RADEON_INFO_VA_UNMAP_WORKING 0x25
1047 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
1048
1049 struct drm_radeon_info {
1050 __u32 request;
1051 __u32 pad;
1052 __u64 value;
1053 };
1054
1055
1056
1057
1058 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
1059 #define SI_TILE_MODE_COLOR_1D 13
1060 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9
1061 #define SI_TILE_MODE_COLOR_2D_8BPP 14
1062 #define SI_TILE_MODE_COLOR_2D_16BPP 15
1063 #define SI_TILE_MODE_COLOR_2D_32BPP 16
1064 #define SI_TILE_MODE_COLOR_2D_64BPP 17
1065 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
1066 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
1067 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4
1068 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0
1069 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
1070 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
1071 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
1072
1073 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
1074
1075 #if defined(__cplusplus)
1076 }
1077 #endif
1078
1079 #endif