include/libdrm/r128_drm.h

0001 /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
0002  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
0003  */
0004 /*
0005  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
0006  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0007  * All rights reserved.
0008  *
0009  * Permission is hereby granted, free of charge, to any person obtaining a
0010  * copy of this software and associated documentation files (the "Software"),
0011  * to deal in the Software without restriction, including without limitation
0012  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0013  * and/or sell copies of the Software, and to permit persons to whom the
0014  * Software is furnished to do so, subject to the following conditions:
0015  *
0016  * The above copyright notice and this permission notice (including the next
0017  * paragraph) shall be included in all copies or substantial portions of the
0018  * Software.
0019  *
0020  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0021  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0022  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0023  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0024  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0025  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0026  * DEALINGS IN THE SOFTWARE.
0027  *
0028  * Authors:
0029  *    Gareth Hughes <gareth@valinux.com>
0030  *    Kevin E. Martin <martin@valinux.com>
0031  */
0032
0033 #ifndef __R128_DRM_H__
0034 #define __R128_DRM_H__
0035
0036 #include "drm.h"
0037
0038 #if defined(__cplusplus)
0039 extern "C" {
0040 #endif
0041
0042 /* WARNING: If you change any of these defines, make sure to change the
0043  * defines in the X server file (r128_sarea.h)
0044  */
0045 #ifndef __R128_SAREA_DEFINES__
0046 #define __R128_SAREA_DEFINES__
0047
0048 /* What needs to be changed for the current vertex buffer?
0049  */
0050 #define R128_UPLOAD_CONTEXT     0x001
0051 #define R128_UPLOAD_SETUP       0x002
0052 #define R128_UPLOAD_TEX0        0x004
0053 #define R128_UPLOAD_TEX1        0x008
0054 #define R128_UPLOAD_TEX0IMAGES      0x010
0055 #define R128_UPLOAD_TEX1IMAGES      0x020
0056 #define R128_UPLOAD_CORE        0x040
0057 #define R128_UPLOAD_MASKS       0x080
0058 #define R128_UPLOAD_WINDOW      0x100
0059 #define R128_UPLOAD_CLIPRECTS       0x200   /* handled client-side */
0060 #define R128_REQUIRE_QUIESCENCE     0x400
0061 #define R128_UPLOAD_ALL         0x7ff
0062
0063 #define R128_FRONT          0x1
0064 #define R128_BACK           0x2
0065 #define R128_DEPTH          0x4
0066
0067 /* Primitive types
0068  */
0069 #define R128_POINTS         0x1
0070 #define R128_LINES          0x2
0071 #define R128_LINE_STRIP         0x3
0072 #define R128_TRIANGLES          0x4
0073 #define R128_TRIANGLE_FAN       0x5
0074 #define R128_TRIANGLE_STRIP     0x6
0075
0076 /* Vertex/indirect buffer size
0077  */
0078 #define R128_BUFFER_SIZE        16384
0079
0080 /* Byte offsets for indirect buffer data
0081  */
0082 #define R128_INDEX_PRIM_OFFSET      20
0083 #define R128_HOSTDATA_BLIT_OFFSET   32
0084
0085 /* Keep these small for testing.
0086  */
0087 #define R128_NR_SAREA_CLIPRECTS     12
0088
0089 /* There are 2 heaps (local/AGP).  Each region within a heap is a
0090  *  minimum of 64k, and there are at most 64 of them per heap.
0091  */
0092 #define R128_LOCAL_TEX_HEAP     0
0093 #define R128_AGP_TEX_HEAP       1
0094 #define R128_NR_TEX_HEAPS       2
0095 #define R128_NR_TEX_REGIONS     64
0096 #define R128_LOG_TEX_GRANULARITY    16
0097
0098 #define R128_NR_CONTEXT_REGS        12
0099
0100 #define R128_MAX_TEXTURE_LEVELS     11
0101 #define R128_MAX_TEXTURE_UNITS      2
0102
0103 #endif              /* __R128_SAREA_DEFINES__ */
0104
0105 typedef struct {
0106     /* Context state - can be written in one large chunk */
0107     unsigned int dst_pitch_offset_c;
0108     unsigned int dp_gui_master_cntl_c;
0109     unsigned int sc_top_left_c;
0110     unsigned int sc_bottom_right_c;
0111     unsigned int z_offset_c;
0112     unsigned int z_pitch_c;
0113     unsigned int z_sten_cntl_c;
0114     unsigned int tex_cntl_c;
0115     unsigned int misc_3d_state_cntl_reg;
0116     unsigned int texture_clr_cmp_clr_c;
0117     unsigned int texture_clr_cmp_msk_c;
0118     unsigned int fog_color_c;
0119
0120     /* Texture state */
0121     unsigned int tex_size_pitch_c;
0122     unsigned int constant_color_c;
0123
0124     /* Setup state */
0125     unsigned int pm4_vc_fpu_setup;
0126     unsigned int setup_cntl;
0127
0128     /* Mask state */
0129     unsigned int dp_write_mask;
0130     unsigned int sten_ref_mask_c;
0131     unsigned int plane_3d_mask_c;
0132
0133     /* Window state */
0134     unsigned int window_xy_offset;
0135
0136     /* Core state */
0137     unsigned int scale_3d_cntl;
0138 } drm_r128_context_regs_t;
0139
0140 /* Setup registers for each texture unit
0141  */
0142 typedef struct {
0143     unsigned int tex_cntl;
0144     unsigned int tex_combine_cntl;
0145     unsigned int tex_size_pitch;
0146     unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
0147     unsigned int tex_border_color;
0148 } drm_r128_texture_regs_t;
0149
0150 typedef struct drm_r128_sarea {
0151     /* The channel for communication of state information to the kernel
0152      * on firing a vertex buffer.
0153      */
0154     drm_r128_context_regs_t context_state;
0155     drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
0156     unsigned int dirty;
0157     unsigned int vertsize;
0158     unsigned int vc_format;
0159
0160     /* The current cliprects, or a subset thereof.
0161      */
0162     struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
0163     unsigned int nbox;
0164
0165     /* Counters for client-side throttling of rendering clients.
0166      */
0167     unsigned int last_frame;
0168     unsigned int last_dispatch;
0169
0170     struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
0171     unsigned int tex_age[R128_NR_TEX_HEAPS];
0172     int ctx_owner;
0173     int pfAllowPageFlip;    /* number of 3d windows (0,1,2 or more) */
0174     int pfCurrentPage;  /* which buffer is being displayed? */
0175 } drm_r128_sarea_t;
0176
0177 /* WARNING: If you change any of these defines, make sure to change the
0178  * defines in the Xserver file (xf86drmR128.h)
0179  */
0180
0181 /* Rage 128 specific ioctls
0182  * The device specific ioctl range is 0x40 to 0x79.
0183  */
0184 #define DRM_R128_INIT       0x00
0185 #define DRM_R128_CCE_START  0x01
0186 #define DRM_R128_CCE_STOP   0x02
0187 #define DRM_R128_CCE_RESET  0x03
0188 #define DRM_R128_CCE_IDLE   0x04
0189 /* 0x05 not used */
0190 #define DRM_R128_RESET      0x06
0191 #define DRM_R128_SWAP       0x07
0192 #define DRM_R128_CLEAR      0x08
0193 #define DRM_R128_VERTEX     0x09
0194 #define DRM_R128_INDICES    0x0a
0195 #define DRM_R128_BLIT       0x0b
0196 #define DRM_R128_DEPTH      0x0c
0197 #define DRM_R128_STIPPLE    0x0d
0198 /* 0x0e not used */
0199 #define DRM_R128_INDIRECT   0x0f
0200 #define DRM_R128_FULLSCREEN 0x10
0201 #define DRM_R128_CLEAR2     0x11
0202 #define DRM_R128_GETPARAM   0x12
0203 #define DRM_R128_FLIP       0x13
0204
0205 #define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
0206 #define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
0207 #define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
0208 #define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
0209 #define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
0210 /* 0x05 not used */
0211 #define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
0212 #define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
0213 #define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
0214 #define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
0215 #define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
0216 #define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
0217 #define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
0218 #define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
0219 /* 0x0e not used */
0220 #define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
0221 #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
0222 #define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
0223 #define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
0224 #define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)
0225
0226 typedef struct drm_r128_init {
0227     enum {
0228         R128_INIT_CCE = 0x01,
0229         R128_CLEANUP_CCE = 0x02
0230     } func;
0231     unsigned long sarea_priv_offset;
0232     int is_pci;
0233     int cce_mode;
0234     int cce_secure;
0235     int ring_size;
0236     int usec_timeout;
0237
0238     unsigned int fb_bpp;
0239     unsigned int front_offset, front_pitch;
0240     unsigned int back_offset, back_pitch;
0241     unsigned int depth_bpp;
0242     unsigned int depth_offset, depth_pitch;
0243     unsigned int span_offset;
0244
0245     unsigned long fb_offset;
0246     unsigned long mmio_offset;
0247     unsigned long ring_offset;
0248     unsigned long ring_rptr_offset;
0249     unsigned long buffers_offset;
0250     unsigned long agp_textures_offset;
0251 } drm_r128_init_t;
0252
0253 typedef struct drm_r128_cce_stop {
0254     int flush;
0255     int idle;
0256 } drm_r128_cce_stop_t;
0257
0258 typedef struct drm_r128_clear {
0259     unsigned int flags;
0260     unsigned int clear_color;
0261     unsigned int clear_depth;
0262     unsigned int color_mask;
0263     unsigned int depth_mask;
0264 } drm_r128_clear_t;
0265
0266 typedef struct drm_r128_vertex {
0267     int prim;
0268     int idx;        /* Index of vertex buffer */
0269     int count;      /* Number of vertices in buffer */
0270     int discard;        /* Client finished with buffer? */
0271 } drm_r128_vertex_t;
0272
0273 typedef struct drm_r128_indices {
0274     int prim;
0275     int idx;
0276     int start;
0277     int end;
0278     int discard;        /* Client finished with buffer? */
0279 } drm_r128_indices_t;
0280
0281 typedef struct drm_r128_blit {
0282     int idx;
0283     int pitch;
0284     int offset;
0285     int format;
0286     unsigned short x, y;
0287     unsigned short width, height;
0288 } drm_r128_blit_t;
0289
0290 typedef struct drm_r128_depth {
0291     enum {
0292         R128_WRITE_SPAN = 0x01,
0293         R128_WRITE_PIXELS = 0x02,
0294         R128_READ_SPAN = 0x03,
0295         R128_READ_PIXELS = 0x04
0296     } func;
0297     int n;
0298     int *x;
0299     int *y;
0300     unsigned int *buffer;
0301     unsigned char *mask;
0302 } drm_r128_depth_t;
0303
0304 typedef struct drm_r128_stipple {
0305     unsigned int *mask;
0306 } drm_r128_stipple_t;
0307
0308 typedef struct drm_r128_indirect {
0309     int idx;
0310     int start;
0311     int end;
0312     int discard;
0313 } drm_r128_indirect_t;
0314
0315 typedef struct drm_r128_fullscreen {
0316     enum {
0317         R128_INIT_FULLSCREEN = 0x01,
0318         R128_CLEANUP_FULLSCREEN = 0x02
0319     } func;
0320 } drm_r128_fullscreen_t;
0321
0322 /* 2.3: An ioctl to get parameters that aren't available to the 3d
0323  * client any other way.
0324  */
0325 #define R128_PARAM_IRQ_NR            1
0326
0327 typedef struct drm_r128_getparam {
0328     int param;
0329     void *value;
0330 } drm_r128_getparam_t;
0331
0332 #if defined(__cplusplus)
0333 }
0334 #endif
0335
0336 #endif