nouveau/nvif/class.h

0001 #ifndef __NVIF_CLASS_H__
0002 #define __NVIF_CLASS_H__
0003
0004 /* these class numbers are made up by us, and not nvidia-assigned */
0005 #define NVIF_CLASS_CONTROL                                    /* if0001.h */ -1
0006 #define NVIF_CLASS_PERFMON                                    /* if0002.h */ -2
0007 #define NVIF_CLASS_PERFDOM                                    /* if0003.h */ -3
0008 #define NVIF_CLASS_SW_NV04                                    /* if0004.h */ -4
0009 #define NVIF_CLASS_SW_NV10                                    /* if0005.h */ -5
0010 #define NVIF_CLASS_SW_NV50                                    /* if0005.h */ -6
0011 #define NVIF_CLASS_SW_GF100                                   /* if0005.h */ -7
0012
0013 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
0014 #define NV_DEVICE                                     /* cl0080.h */ 0x00000080
0015
0016 #define NV_DMA_FROM_MEMORY                            /* cl0002.h */ 0x00000002
0017 #define NV_DMA_TO_MEMORY                              /* cl0002.h */ 0x00000003
0018 #define NV_DMA_IN_MEMORY                              /* cl0002.h */ 0x0000003d
0019
0020 #define FERMI_TWOD_A                                                 0x0000902d
0021
0022 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
0023
0024 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
0025 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
0026
0027 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
0028
0029 #define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
0030 #define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
0031 #define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
0032 #define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
0033 #define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
0034 #define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
0035
0036 #define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
0037 #define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
0038 #define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
0039 #define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
0040 #define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
0041
0042 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
0043 #define G82_DISP                                      /* cl5070.h */ 0x00008270
0044 #define GT200_DISP                                    /* cl5070.h */ 0x00008370
0045 #define GT214_DISP                                    /* cl5070.h */ 0x00008570
0046 #define GT206_DISP                                    /* cl5070.h */ 0x00008870
0047 #define GF110_DISP                                    /* cl5070.h */ 0x00009070
0048 #define GK104_DISP                                    /* cl5070.h */ 0x00009170
0049 #define GK110_DISP                                    /* cl5070.h */ 0x00009270
0050 #define GM107_DISP                                    /* cl5070.h */ 0x00009470
0051 #define GM204_DISP                                    /* cl5070.h */ 0x00009570
0052
0053 #define NV31_MPEG                                                    0x00003174
0054 #define G82_MPEG                                                     0x00008274
0055
0056 #define NV74_VP2                                                     0x00007476
0057
0058 #define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
0059 #define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
0060 #define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
0061 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
0062 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
0063
0064 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
0065 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
0066 #define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
0067 #define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
0068 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
0069
0070 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
0071 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
0072 #define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
0073 #define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
0074 #define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
0075 #define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
0076 #define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c
0077
0078 #define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
0079 #define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
0080 #define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
0081 #define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
0082 #define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
0083 #define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
0084 #define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
0085 #define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
0086 #define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
0087 #define GM204_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
0088
0089 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
0090 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
0091 #define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
0092 #define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
0093 #define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
0094 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
0095
0096 #define FERMI_A                                       /* cl9097.h */ 0x00009097
0097 #define FERMI_B                                       /* cl9097.h */ 0x00009197
0098 #define FERMI_C                                       /* cl9097.h */ 0x00009297
0099
0100 #define KEPLER_A                                      /* cl9097.h */ 0x0000a097
0101 #define KEPLER_B                                      /* cl9097.h */ 0x0000a197
0102 #define KEPLER_C                                      /* cl9097.h */ 0x0000a297
0103
0104 #define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
0105 #define MAXWELL_B                                     /* cl9097.h */ 0x0000b197
0106
0107 #define NV74_BSP                                                     0x000074b0
0108
0109 #define GT212_MSVLD                                                  0x000085b1
0110 #define IGT21A_MSVLD                                                 0x000086b1
0111 #define G98_MSVLD                                                    0x000088b1
0112 #define GF100_MSVLD                                                  0x000090b1
0113 #define GK104_MSVLD                                                  0x000095b1
0114
0115 #define GT212_MSPDEC                                                 0x000085b2
0116 #define G98_MSPDEC                                                   0x000088b2
0117 #define GF100_MSPDEC                                                 0x000090b2
0118 #define GK104_MSPDEC                                                 0x000095b2
0119
0120 #define GT212_MSPPP                                                  0x000085b3
0121 #define G98_MSPPP                                                    0x000088b3
0122 #define GF100_MSPPP                                                  0x000090b3
0123
0124 #define G98_SEC                                                      0x000088b4
0125
0126 #define GT212_DMA                                                    0x000085b5
0127 #define FERMI_DMA                                                    0x000090b5
0128 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
0129 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
0130
0131 #define FERMI_DECOMPRESS                                             0x000090b8
0132
0133 #define FERMI_COMPUTE_A                                              0x000090c0
0134 #define FERMI_COMPUTE_B                                              0x000091c0
0135 #define KEPLER_COMPUTE_A                                             0x0000a0c0
0136 #define KEPLER_COMPUTE_B                                             0x0000a1c0
0137 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
0138 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
0139
0140 #define NV74_CIPHER                                                  0x000074c1
0141 #endif