include/libdrm/intel_bufmgr.h

0001 /*
0002  * Copyright © 2008-2012 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *    Eric Anholt <eric@anholt.net>
0025  *
0026  */
0027
0028 /**
0029  * @file intel_bufmgr.h
0030  *
0031  * Public definitions of Intel-specific bufmgr functions.
0032  */
0033
0034 #ifndef INTEL_BUFMGR_H
0035 #define INTEL_BUFMGR_H
0036
0037 #include <stdio.h>
0038 #include <stdint.h>
0039 #include <stdio.h>
0040
0041 #if defined(__cplusplus)
0042 extern "C" {
0043 #endif
0044
0045 struct drm_clip_rect;
0046
0047 typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
0048 typedef struct _drm_intel_context drm_intel_context;
0049 typedef struct _drm_intel_bo drm_intel_bo;
0050
0051 struct _drm_intel_bo {
0052     /**
0053      * Size in bytes of the buffer object.
0054      *
0055      * The size may be larger than the size originally requested for the
0056      * allocation, such as being aligned to page size.
0057      */
0058     unsigned long size;
0059
0060     /**
0061      * Alignment requirement for object
0062      *
0063      * Used for GTT mapping & pinning the object.
0064      */
0065     unsigned long align;
0066
0067     /**
0068      * Deprecated field containing (possibly the low 32-bits of) the last
0069      * seen virtual card address.  Use offset64 instead.
0070      */
0071     unsigned long offset;
0072
0073     /**
0074      * Virtual address for accessing the buffer data.  Only valid while
0075      * mapped.
0076      */
0077 #ifdef __cplusplus
0078     void *virt;
0079 #else
0080     void *virtual;
0081 #endif
0082
0083     /** Buffer manager context associated with this buffer object */
0084     drm_intel_bufmgr *bufmgr;
0085
0086     /**
0087      * MM-specific handle for accessing object
0088      */
0089     int handle;
0090
0091     /**
0092      * Last seen card virtual address (offset from the beginning of the
0093      * aperture) for the object.  This should be used to fill relocation
0094      * entries when calling drm_intel_bo_emit_reloc()
0095      */
0096     uint64_t offset64;
0097 };
0098
0099 enum aub_dump_bmp_format {
0100     AUB_DUMP_BMP_FORMAT_8BIT = 1,
0101     AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
0102     AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
0103     AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
0104 };
0105
0106 typedef struct _drm_intel_aub_annotation {
0107     uint32_t type;
0108     uint32_t subtype;
0109     uint32_t ending_offset;
0110 } drm_intel_aub_annotation;
0111
0112 #define BO_ALLOC_FOR_RENDER (1<<0)
0113
0114 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
0115                  unsigned long size, unsigned int alignment);
0116 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
0117                         const char *name,
0118                         unsigned long size,
0119                         unsigned int alignment);
0120 drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
0121                     const char *name,
0122                     void *addr, uint32_t tiling_mode,
0123                     uint32_t stride, unsigned long size,
0124                     unsigned long flags);
0125 drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
0126                        const char *name,
0127                        int x, int y, int cpp,
0128                        uint32_t *tiling_mode,
0129                        unsigned long *pitch,
0130                        unsigned long flags);
0131 void drm_intel_bo_reference(drm_intel_bo *bo);
0132 void drm_intel_bo_unreference(drm_intel_bo *bo);
0133 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
0134 int drm_intel_bo_unmap(drm_intel_bo *bo);
0135
0136 int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
0137              unsigned long size, const void *data);
0138 int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
0139                  unsigned long size, void *data);
0140 void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
0141
0142 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
0143 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
0144 int drm_intel_bo_exec(drm_intel_bo *bo, int used,
0145               struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
0146 int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
0147             struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
0148             unsigned int flags);
0149 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
0150
0151 int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
0152                 drm_intel_bo *target_bo, uint32_t target_offset,
0153                 uint32_t read_domains, uint32_t write_domain);
0154 int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
0155                   drm_intel_bo *target_bo,
0156                   uint32_t target_offset,
0157                   uint32_t read_domains, uint32_t write_domain);
0158 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
0159 int drm_intel_bo_unpin(drm_intel_bo *bo);
0160 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
0161                 uint32_t stride);
0162 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
0163                 uint32_t * swizzle_mode);
0164 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
0165 int drm_intel_bo_busy(drm_intel_bo *bo);
0166 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
0167 int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
0168 int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
0169
0170 int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
0171 int drm_intel_bo_is_reusable(drm_intel_bo *bo);
0172 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
0173
0174 /* drm_intel_bufmgr_gem.c */
0175 drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
0176 drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
0177                         const char *name,
0178                         unsigned int handle);
0179 void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
0180 void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
0181 void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
0182                          int limit);
0183 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
0184 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
0185 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
0186
0187 #define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
0188 int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
0189 void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
0190 void drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo);
0191
0192 void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
0193 void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
0194 void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
0195
0196 int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
0197 void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
0198 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
0199
0200 void
0201 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
0202                       const char *filename);
0203 void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
0204 void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
0205                    int x1, int y1, int width, int height,
0206                    enum aub_dump_bmp_format format,
0207                    int pitch, int offset);
0208 void
0209 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
0210                      drm_intel_aub_annotation *annotations,
0211                      unsigned count);
0212
0213 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
0214
0215 int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
0216 int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
0217 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
0218
0219 drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
0220 int drm_intel_gem_context_get_id(drm_intel_context *ctx,
0221                                  uint32_t *ctx_id);
0222 void drm_intel_gem_context_destroy(drm_intel_context *ctx);
0223 int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
0224                   int used, unsigned int flags);
0225 int drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
0226                 drm_intel_context *ctx,
0227                 int used,
0228                 int in_fence,
0229                 int *out_fence,
0230                 unsigned int flags);
0231
0232 int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
0233 drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
0234                         int prime_fd, int size);
0235
0236 /* drm_intel_bufmgr_fake.c */
0237 drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
0238                          unsigned long low_offset,
0239                          void *low_virtual,
0240                          unsigned long size,
0241                          volatile unsigned int
0242                          *last_dispatch);
0243 void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
0244                          volatile unsigned int
0245                          *last_dispatch);
0246 void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
0247                          int (*exec) (drm_intel_bo *bo,
0248                               unsigned int used,
0249                               void *priv),
0250                          void *priv);
0251 void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
0252                           unsigned int (*emit) (void *priv),
0253                           void (*wait) (unsigned int fence,
0254                                 void *priv),
0255                           void *priv);
0256 drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
0257                          const char *name,
0258                          unsigned long offset,
0259                          unsigned long size, void *virt);
0260 void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
0261                          void (*invalidate_cb) (drm_intel_bo
0262                                     * bo,
0263                                     void *ptr),
0264                          void *ptr);
0265
0266 void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
0267 void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
0268
0269 struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
0270 void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
0271 void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
0272                     void *data, uint32_t hw_offset,
0273                     int count);
0274 void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
0275                     int dump_past_end);
0276 void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
0277                     uint32_t head, uint32_t tail);
0278 void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
0279 void drm_intel_decode(struct drm_intel_decode *ctx);
0280
0281 int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
0282                uint32_t offset,
0283                uint64_t *result);
0284
0285 int drm_intel_get_reset_stats(drm_intel_context *ctx,
0286                   uint32_t *reset_count,
0287                   uint32_t *active,
0288                   uint32_t *pending);
0289
0290 int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
0291 int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
0292
0293 int drm_intel_get_pooled_eu(int fd);
0294 int drm_intel_get_min_eu_in_pool(int fd);
0295
0296 /** @{ Compatibility defines to keep old code building despite the symbol rename
0297  * from dri_* to drm_intel_*
0298  */
0299 #define dri_bo drm_intel_bo
0300 #define dri_bufmgr drm_intel_bufmgr
0301 #define dri_bo_alloc drm_intel_bo_alloc
0302 #define dri_bo_reference drm_intel_bo_reference
0303 #define dri_bo_unreference drm_intel_bo_unreference
0304 #define dri_bo_map drm_intel_bo_map
0305 #define dri_bo_unmap drm_intel_bo_unmap
0306 #define dri_bo_subdata drm_intel_bo_subdata
0307 #define dri_bo_get_subdata drm_intel_bo_get_subdata
0308 #define dri_bo_wait_rendering drm_intel_bo_wait_rendering
0309 #define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
0310 #define dri_bufmgr_destroy drm_intel_bufmgr_destroy
0311 #define dri_bo_exec drm_intel_bo_exec
0312 #define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
0313 #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset,     \
0314               reloc_offset, target_bo)          \
0315     drm_intel_bo_emit_reloc(reloc_bo, reloc_offset,         \
0316                 target_bo, target_offset,       \
0317                 read, write);
0318 #define dri_bo_pin drm_intel_bo_pin
0319 #define dri_bo_unpin drm_intel_bo_unpin
0320 #define dri_bo_get_tiling drm_intel_bo_get_tiling
0321 #define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
0322 #define dri_bo_flink drm_intel_bo_flink
0323 #define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
0324 #define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
0325 #define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
0326 #define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
0327 #define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
0328 #define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
0329 #define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
0330 #define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
0331 #define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
0332 #define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
0333 #define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
0334
0335 /** @{ */
0336
0337 #if defined(__cplusplus)
0338 }
0339 #endif
0340
0341 #endif /* INTEL_BUFMGR_H */