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File indexing completed on 2025-01-18 10:01:48
0001 /* 0002 * Copyright 2014 Advanced Micro Devices, Inc. 0003 * 0004 * Permission is hereby granted, free of charge, to any person obtaining a 0005 * copy of this software and associated documentation files (the "Software"), 0006 * to deal in the Software without restriction, including without limitation 0007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 0008 * and/or sell copies of the Software, and to permit persons to whom the 0009 * Software is furnished to do so, subject to the following conditions: 0010 * 0011 * The above copyright notice and this permission notice shall be included in 0012 * all copies or substantial portions of the Software. 0013 * 0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 0017 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 0018 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 0019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 0020 * OTHER DEALINGS IN THE SOFTWARE. 0021 * 0022 */ 0023 0024 /** 0025 * \file amdgpu.h 0026 * 0027 * Declare public libdrm_amdgpu API 0028 * 0029 * This file define API exposed by libdrm_amdgpu library. 0030 * User wanted to use libdrm_amdgpu functionality must include 0031 * this file. 0032 * 0033 */ 0034 #ifndef _AMDGPU_H_ 0035 #define _AMDGPU_H_ 0036 0037 #include <stdint.h> 0038 #include <stdbool.h> 0039 0040 #ifdef __cplusplus 0041 extern "C" { 0042 #endif 0043 0044 struct drm_amdgpu_info_hw_ip; 0045 struct drm_amdgpu_bo_list_entry; 0046 0047 /*--------------------------------------------------------------------------*/ 0048 /* --------------------------- Defines ------------------------------------ */ 0049 /*--------------------------------------------------------------------------*/ 0050 0051 /** 0052 * Define max. number of Command Buffers (IB) which could be sent to the single 0053 * hardware IP to accommodate CE/DE requirements 0054 * 0055 * \sa amdgpu_cs_ib_info 0056 */ 0057 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 0058 0059 /** 0060 * Special timeout value meaning that the timeout is infinite. 0061 */ 0062 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 0063 0064 /** 0065 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 0066 * is absolute. 0067 */ 0068 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 0069 0070 /*--------------------------------------------------------------------------*/ 0071 /* ----------------------------- Enums ------------------------------------ */ 0072 /*--------------------------------------------------------------------------*/ 0073 0074 /** 0075 * Enum describing possible handle types 0076 * 0077 * \sa amdgpu_bo_import, amdgpu_bo_export 0078 * 0079 */ 0080 enum amdgpu_bo_handle_type { 0081 /** GEM flink name (needs DRM authentication, used by DRI2) */ 0082 amdgpu_bo_handle_type_gem_flink_name = 0, 0083 0084 /** KMS handle which is used by all driver ioctls */ 0085 amdgpu_bo_handle_type_kms = 1, 0086 0087 /** DMA-buf fd handle */ 0088 amdgpu_bo_handle_type_dma_buf_fd = 2, 0089 0090 /** Deprecated in favour of and same behaviour as 0091 * amdgpu_bo_handle_type_kms, use that instead of this 0092 */ 0093 amdgpu_bo_handle_type_kms_noimport = 3, 0094 }; 0095 0096 /** Define known types of GPU VM VA ranges */ 0097 enum amdgpu_gpu_va_range 0098 { 0099 /** Allocate from "normal"/general range */ 0100 amdgpu_gpu_va_range_general = 0 0101 }; 0102 0103 enum amdgpu_sw_info { 0104 amdgpu_sw_info_address32_hi = 0, 0105 }; 0106 0107 /*--------------------------------------------------------------------------*/ 0108 /* -------------------------- Datatypes ----------------------------------- */ 0109 /*--------------------------------------------------------------------------*/ 0110 0111 /** 0112 * Define opaque pointer to context associated with fd. 0113 * This context will be returned as the result of 0114 * "initialize" function and should be pass as the first 0115 * parameter to any API call 0116 */ 0117 typedef struct amdgpu_device *amdgpu_device_handle; 0118 0119 /** 0120 * Define GPU Context type as pointer to opaque structure 0121 * Example of GPU Context is the "rendering" context associated 0122 * with OpenGL context (glCreateContext) 0123 */ 0124 typedef struct amdgpu_context *amdgpu_context_handle; 0125 0126 /** 0127 * Define handle for amdgpu resources: buffer, GDS, etc. 0128 */ 0129 typedef struct amdgpu_bo *amdgpu_bo_handle; 0130 0131 /** 0132 * Define handle for list of BOs 0133 */ 0134 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 0135 0136 /** 0137 * Define handle to be used to work with VA allocated ranges 0138 */ 0139 typedef struct amdgpu_va *amdgpu_va_handle; 0140 0141 /** 0142 * Define handle dealing with VA allocation. An amdgpu_device 0143 * owns one of these, but they can also be used without a device. 0144 */ 0145 typedef struct amdgpu_va_manager *amdgpu_va_manager_handle; 0146 0147 /** 0148 * Define handle for semaphore 0149 */ 0150 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 0151 0152 /*--------------------------------------------------------------------------*/ 0153 /* -------------------------- Structures ---------------------------------- */ 0154 /*--------------------------------------------------------------------------*/ 0155 0156 /** 0157 * Structure describing memory allocation request 0158 * 0159 * \sa amdgpu_bo_alloc() 0160 * 0161 */ 0162 struct amdgpu_bo_alloc_request { 0163 /** Allocation request. It must be aligned correctly. */ 0164 uint64_t alloc_size; 0165 0166 /** 0167 * It may be required to have some specific alignment requirements 0168 * for physical back-up storage (e.g. for displayable surface). 0169 * If 0 there is no special alignment requirement 0170 */ 0171 uint64_t phys_alignment; 0172 0173 /** 0174 * UMD should specify where to allocate memory and how it 0175 * will be accessed by the CPU. 0176 */ 0177 uint32_t preferred_heap; 0178 0179 /** Additional flags passed on allocation */ 0180 uint64_t flags; 0181 }; 0182 0183 /** 0184 * Special UMD specific information associated with buffer. 0185 * 0186 * It may be need to pass some buffer charactersitic as part 0187 * of buffer sharing. Such information are defined UMD and 0188 * opaque for libdrm_amdgpu as well for kernel driver. 0189 * 0190 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 0191 * amdgpu_bo_import(), amdgpu_bo_export 0192 * 0193 */ 0194 struct amdgpu_bo_metadata { 0195 /** Special flag associated with surface */ 0196 uint64_t flags; 0197 0198 /** 0199 * ASIC-specific tiling information (also used by DCE). 0200 * The encoding is defined by the AMDGPU_TILING_* definitions. 0201 */ 0202 uint64_t tiling_info; 0203 0204 /** Size of metadata associated with the buffer, in bytes. */ 0205 uint32_t size_metadata; 0206 0207 /** UMD specific metadata. Opaque for kernel */ 0208 uint32_t umd_metadata[64]; 0209 }; 0210 0211 /** 0212 * Structure describing allocated buffer. Client may need 0213 * to query such information as part of 'sharing' buffers mechanism 0214 * 0215 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 0216 * amdgpu_bo_import(), amdgpu_bo_export() 0217 */ 0218 struct amdgpu_bo_info { 0219 /** Allocated memory size */ 0220 uint64_t alloc_size; 0221 0222 /** 0223 * It may be required to have some specific alignment requirements 0224 * for physical back-up storage. 0225 */ 0226 uint64_t phys_alignment; 0227 0228 /** Heap where to allocate memory. */ 0229 uint32_t preferred_heap; 0230 0231 /** Additional allocation flags. */ 0232 uint64_t alloc_flags; 0233 0234 /** Metadata associated with buffer if any. */ 0235 struct amdgpu_bo_metadata metadata; 0236 }; 0237 0238 /** 0239 * Structure with information about "imported" buffer 0240 * 0241 * \sa amdgpu_bo_import() 0242 * 0243 */ 0244 struct amdgpu_bo_import_result { 0245 /** Handle of memory/buffer to use */ 0246 amdgpu_bo_handle buf_handle; 0247 0248 /** Buffer size */ 0249 uint64_t alloc_size; 0250 }; 0251 0252 /** 0253 * 0254 * Structure to describe GDS partitioning information. 0255 * \note OA and GWS resources are asscoiated with GDS partition 0256 * 0257 * \sa amdgpu_gpu_resource_query_gds_info 0258 * 0259 */ 0260 struct amdgpu_gds_resource_info { 0261 uint32_t gds_gfx_partition_size; 0262 uint32_t compute_partition_size; 0263 uint32_t gds_total_size; 0264 uint32_t gws_per_gfx_partition; 0265 uint32_t gws_per_compute_partition; 0266 uint32_t oa_per_gfx_partition; 0267 uint32_t oa_per_compute_partition; 0268 }; 0269 0270 /** 0271 * Structure describing CS fence 0272 * 0273 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 0274 * 0275 */ 0276 struct amdgpu_cs_fence { 0277 0278 /** In which context IB was sent to execution */ 0279 amdgpu_context_handle context; 0280 0281 /** To which HW IP type the fence belongs */ 0282 uint32_t ip_type; 0283 0284 /** IP instance index if there are several IPs of the same type. */ 0285 uint32_t ip_instance; 0286 0287 /** Ring index of the HW IP */ 0288 uint32_t ring; 0289 0290 /** Specify fence for which we need to check submission status.*/ 0291 uint64_t fence; 0292 }; 0293 0294 /** 0295 * Structure describing IB 0296 * 0297 * \sa amdgpu_cs_request, amdgpu_cs_submit() 0298 * 0299 */ 0300 struct amdgpu_cs_ib_info { 0301 /** Special flags */ 0302 uint64_t flags; 0303 0304 /** Virtual MC address of the command buffer */ 0305 uint64_t ib_mc_address; 0306 0307 /** 0308 * Size of Command Buffer to be submitted. 0309 * - The size is in units of dwords (4 bytes). 0310 * - Could be 0 0311 */ 0312 uint32_t size; 0313 }; 0314 0315 /** 0316 * Structure describing fence information 0317 * 0318 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 0319 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 0320 */ 0321 struct amdgpu_cs_fence_info { 0322 /** buffer object for the fence */ 0323 amdgpu_bo_handle handle; 0324 0325 /** fence offset in the unit of sizeof(uint64_t) */ 0326 uint64_t offset; 0327 }; 0328 0329 /** 0330 * Structure describing submission request 0331 * 0332 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 0333 * 0334 * \sa amdgpu_cs_submit() 0335 */ 0336 struct amdgpu_cs_request { 0337 /** Specify flags with additional information */ 0338 uint64_t flags; 0339 0340 /** Specify HW IP block type to which to send the IB. */ 0341 unsigned ip_type; 0342 0343 /** IP instance index if there are several IPs of the same type. */ 0344 unsigned ip_instance; 0345 0346 /** 0347 * Specify ring index of the IP. We could have several rings 0348 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 0349 */ 0350 uint32_t ring; 0351 0352 /** 0353 * List handle with resources used by this request. 0354 */ 0355 amdgpu_bo_list_handle resources; 0356 0357 /** 0358 * Number of dependencies this Command submission needs to 0359 * wait for before starting execution. 0360 */ 0361 uint32_t number_of_dependencies; 0362 0363 /** 0364 * Array of dependencies which need to be met before 0365 * execution can start. 0366 */ 0367 struct amdgpu_cs_fence *dependencies; 0368 0369 /** Number of IBs to submit in the field ibs. */ 0370 uint32_t number_of_ibs; 0371 0372 /** 0373 * IBs to submit. Those IBs will be submit together as single entity 0374 */ 0375 struct amdgpu_cs_ib_info *ibs; 0376 0377 /** 0378 * The returned sequence number for the command submission 0379 */ 0380 uint64_t seq_no; 0381 0382 /** 0383 * The fence information 0384 */ 0385 struct amdgpu_cs_fence_info fence_info; 0386 }; 0387 0388 /** 0389 * Structure which provide information about GPU VM MC Address space 0390 * alignments requirements 0391 * 0392 * \sa amdgpu_query_buffer_size_alignment 0393 */ 0394 struct amdgpu_buffer_size_alignments { 0395 /** Size alignment requirement for allocation in 0396 * local memory */ 0397 uint64_t size_local; 0398 0399 /** 0400 * Size alignment requirement for allocation in remote memory 0401 */ 0402 uint64_t size_remote; 0403 }; 0404 0405 /** 0406 * Structure which provide information about heap 0407 * 0408 * \sa amdgpu_query_heap_info() 0409 * 0410 */ 0411 struct amdgpu_heap_info { 0412 /** Theoretical max. available memory in the given heap */ 0413 uint64_t heap_size; 0414 0415 /** 0416 * Number of bytes allocated in the heap. This includes all processes 0417 * and private allocations in the kernel. It changes when new buffers 0418 * are allocated, freed, and moved. It cannot be larger than 0419 * heap_size. 0420 */ 0421 uint64_t heap_usage; 0422 0423 /** 0424 * Theoretical possible max. size of buffer which 0425 * could be allocated in the given heap 0426 */ 0427 uint64_t max_allocation; 0428 }; 0429 0430 /** 0431 * Describe GPU h/w info needed for UMD correct initialization 0432 * 0433 * \sa amdgpu_query_gpu_info() 0434 */ 0435 struct amdgpu_gpu_info { 0436 /** Asic id */ 0437 uint32_t asic_id; 0438 /** Chip revision */ 0439 uint32_t chip_rev; 0440 /** Chip external revision */ 0441 uint32_t chip_external_rev; 0442 /** Family ID */ 0443 uint32_t family_id; 0444 /** Special flags */ 0445 uint64_t ids_flags; 0446 /** max engine clock*/ 0447 uint64_t max_engine_clk; 0448 /** max memory clock */ 0449 uint64_t max_memory_clk; 0450 /** number of shader engines */ 0451 uint32_t num_shader_engines; 0452 /** number of shader arrays per engine */ 0453 uint32_t num_shader_arrays_per_engine; 0454 /** Number of available good shader pipes */ 0455 uint32_t avail_quad_shader_pipes; 0456 /** Max. number of shader pipes.(including good and bad pipes */ 0457 uint32_t max_quad_shader_pipes; 0458 /** Number of parameter cache entries per shader quad pipe */ 0459 uint32_t cache_entries_per_quad_pipe; 0460 /** Number of available graphics context */ 0461 uint32_t num_hw_gfx_contexts; 0462 /** Number of render backend pipes */ 0463 uint32_t rb_pipes; 0464 /** Enabled render backend pipe mask */ 0465 uint32_t enabled_rb_pipes_mask; 0466 /** Frequency of GPU Counter */ 0467 uint32_t gpu_counter_freq; 0468 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 0469 uint32_t backend_disable[4]; 0470 /** Value of MC_ARB_RAMCFG register*/ 0471 uint32_t mc_arb_ramcfg; 0472 /** Value of GB_ADDR_CONFIG */ 0473 uint32_t gb_addr_cfg; 0474 /** Values of the GB_TILE_MODE0..31 registers */ 0475 uint32_t gb_tile_mode[32]; 0476 /** Values of GB_MACROTILE_MODE0..15 registers */ 0477 uint32_t gb_macro_tile_mode[16]; 0478 /** Value of PA_SC_RASTER_CONFIG register per SE */ 0479 uint32_t pa_sc_raster_cfg[4]; 0480 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 0481 uint32_t pa_sc_raster_cfg1[4]; 0482 /* CU info */ 0483 uint32_t cu_active_number; 0484 uint32_t cu_ao_mask; 0485 uint32_t cu_bitmap[4][4]; 0486 /* video memory type info*/ 0487 uint32_t vram_type; 0488 /* video memory bit width*/ 0489 uint32_t vram_bit_width; 0490 /** constant engine ram size*/ 0491 uint32_t ce_ram_size; 0492 /* vce harvesting instance */ 0493 uint32_t vce_harvest_config; 0494 /* PCI revision ID */ 0495 uint32_t pci_rev_id; 0496 }; 0497 0498 0499 /*--------------------------------------------------------------------------*/ 0500 /*------------------------- Functions --------------------------------------*/ 0501 /*--------------------------------------------------------------------------*/ 0502 0503 /* 0504 * Initialization / Cleanup 0505 * 0506 */ 0507 0508 /** 0509 * 0510 * \param fd - \c [in] File descriptor for AMD GPU device 0511 * received previously as the result of 0512 * e.g. drmOpen() call. 0513 * For legacy fd type, the DRI2/DRI3 0514 * authentication should be done before 0515 * calling this function. 0516 * \param major_version - \c [out] Major version of library. It is assumed 0517 * that adding new functionality will cause 0518 * increase in major version 0519 * \param minor_version - \c [out] Minor version of library 0520 * \param device_handle - \c [out] Pointer to opaque context which should 0521 * be passed as the first parameter on each 0522 * API call 0523 * 0524 * 0525 * \return 0 on success\n 0526 * <0 - Negative POSIX Error code 0527 * 0528 * 0529 * \sa amdgpu_device_deinitialize() 0530 */ 0531 int amdgpu_device_initialize(int fd, 0532 uint32_t *major_version, 0533 uint32_t *minor_version, 0534 amdgpu_device_handle *device_handle); 0535 0536 /** 0537 * Same as amdgpu_device_initialize() except when deduplicate_device 0538 * is false *and* fd points to a device that was already initialized. 0539 * In this case, amdgpu_device_initialize would return the same 0540 * amdgpu_device_handle while here amdgpu_device_initialize2 would 0541 * return a new handle. 0542 * amdgpu_device_initialize() should be preferred in most situations; 0543 * the only use-case where not-deduplicating devices make sense is 0544 * when one wants to have isolated device handles in the same process. 0545 */ 0546 int amdgpu_device_initialize2(int fd, bool deduplicate_device, 0547 uint32_t *major_version, 0548 uint32_t *minor_version, 0549 amdgpu_device_handle *device_handle); 0550 /** 0551 * 0552 * When access to such library does not needed any more the special 0553 * function must be call giving opportunity to clean up any 0554 * resources if needed. 0555 * 0556 * \param device_handle - \c [in] Context associated with file 0557 * descriptor for AMD GPU device 0558 * received previously as the 0559 * result e.g. of drmOpen() call. 0560 * 0561 * \return 0 on success\n 0562 * <0 - Negative POSIX Error code 0563 * 0564 * \sa amdgpu_device_initialize() 0565 * 0566 */ 0567 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 0568 0569 /** 0570 * 0571 * /param device_handle - \c [in] Device handle. 0572 * See #amdgpu_device_initialize() 0573 * 0574 * \return Returns the drm fd used for operations on this 0575 * device. This is still owned by the library and hence 0576 * should not be closed. Guaranteed to be valid until 0577 * #amdgpu_device_deinitialize gets called. 0578 * 0579 */ 0580 int amdgpu_device_get_fd(amdgpu_device_handle device_handle); 0581 0582 /* 0583 * Memory Management 0584 * 0585 */ 0586 0587 /** 0588 * Allocate memory to be used by UMD for GPU related operations 0589 * 0590 * \param dev - \c [in] Device handle. 0591 * See #amdgpu_device_initialize() 0592 * \param alloc_buffer - \c [in] Pointer to the structure describing an 0593 * allocation request 0594 * \param buf_handle - \c [out] Allocated buffer handle 0595 * 0596 * \return 0 on success\n 0597 * <0 - Negative POSIX Error code 0598 * 0599 * \sa amdgpu_bo_free() 0600 */ 0601 int amdgpu_bo_alloc(amdgpu_device_handle dev, 0602 struct amdgpu_bo_alloc_request *alloc_buffer, 0603 amdgpu_bo_handle *buf_handle); 0604 0605 /** 0606 * Associate opaque data with buffer to be queried by another UMD 0607 * 0608 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0609 * \param buf_handle - \c [in] Buffer handle 0610 * \param info - \c [in] Metadata to associated with buffer 0611 * 0612 * \return 0 on success\n 0613 * <0 - Negative POSIX Error code 0614 */ 0615 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 0616 struct amdgpu_bo_metadata *info); 0617 0618 /** 0619 * Query buffer information including metadata previusly associated with 0620 * buffer. 0621 * 0622 * \param dev - \c [in] Device handle. 0623 * See #amdgpu_device_initialize() 0624 * \param buf_handle - \c [in] Buffer handle 0625 * \param info - \c [out] Structure describing buffer 0626 * 0627 * \return 0 on success\n 0628 * <0 - Negative POSIX Error code 0629 * 0630 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 0631 */ 0632 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 0633 struct amdgpu_bo_info *info); 0634 0635 /** 0636 * Allow others to get access to buffer 0637 * 0638 * \param dev - \c [in] Device handle. 0639 * See #amdgpu_device_initialize() 0640 * \param buf_handle - \c [in] Buffer handle 0641 * \param type - \c [in] Type of handle requested 0642 * \param shared_handle - \c [out] Special "shared" handle 0643 * 0644 * \return 0 on success\n 0645 * <0 - Negative POSIX Error code 0646 * 0647 * \sa amdgpu_bo_import() 0648 * 0649 */ 0650 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 0651 enum amdgpu_bo_handle_type type, 0652 uint32_t *shared_handle); 0653 0654 /** 0655 * Request access to "shared" buffer 0656 * 0657 * \param dev - \c [in] Device handle. 0658 * See #amdgpu_device_initialize() 0659 * \param type - \c [in] Type of handle requested 0660 * \param shared_handle - \c [in] Shared handle received as result "import" 0661 * operation 0662 * \param output - \c [out] Pointer to structure with information 0663 * about imported buffer 0664 * 0665 * \return 0 on success\n 0666 * <0 - Negative POSIX Error code 0667 * 0668 * \note Buffer must be "imported" only using new "fd" (different from 0669 * one used by "exporter"). 0670 * 0671 * \sa amdgpu_bo_export() 0672 * 0673 */ 0674 int amdgpu_bo_import(amdgpu_device_handle dev, 0675 enum amdgpu_bo_handle_type type, 0676 uint32_t shared_handle, 0677 struct amdgpu_bo_import_result *output); 0678 0679 /** 0680 * Request GPU access to user allocated memory e.g. via "malloc" 0681 * 0682 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 0683 * \param cpu - [in] CPU address of user allocated memory which we 0684 * want to map to GPU address space (make GPU accessible) 0685 * (This address must be correctly aligned). 0686 * \param size - [in] Size of allocation (must be correctly aligned) 0687 * \param buf_handle - [out] Buffer handle for the userptr memory 0688 * resource on submission and be used in other operations. 0689 * 0690 * 0691 * \return 0 on success\n 0692 * <0 - Negative POSIX Error code 0693 * 0694 * \note 0695 * This call doesn't guarantee that such memory will be persistently 0696 * "locked" / make non-pageable. The purpose of this call is to provide 0697 * opportunity for GPU get access to this resource during submission. 0698 * 0699 * The maximum amount of memory which could be mapped in this call depends 0700 * if overcommit is disabled or not. If overcommit is disabled than the max. 0701 * amount of memory to be pinned will be limited by left "free" size in total 0702 * amount of memory which could be locked simultaneously ("GART" size). 0703 * 0704 * Supported (theoretical) max. size of mapping is restricted only by 0705 * "GART" size. 0706 * 0707 * It is responsibility of caller to correctly specify access rights 0708 * on VA assignment. 0709 */ 0710 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 0711 void *cpu, uint64_t size, 0712 amdgpu_bo_handle *buf_handle); 0713 0714 /** 0715 * Validate if the user memory comes from BO 0716 * 0717 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 0718 * \param cpu - [in] CPU address of user allocated memory which we 0719 * want to map to GPU address space (make GPU accessible) 0720 * (This address must be correctly aligned). 0721 * \param size - [in] Size of allocation (must be correctly aligned) 0722 * \param buf_handle - [out] Buffer handle for the userptr memory 0723 * if the user memory is not from BO, the buf_handle will be NULL. 0724 * \param offset_in_bo - [out] offset in this BO for this user memory 0725 * 0726 * 0727 * \return 0 on success\n 0728 * <0 - Negative POSIX Error code 0729 * 0730 */ 0731 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 0732 void *cpu, 0733 uint64_t size, 0734 amdgpu_bo_handle *buf_handle, 0735 uint64_t *offset_in_bo); 0736 0737 /** 0738 * Free previously allocated memory 0739 * 0740 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0741 * \param buf_handle - \c [in] Buffer handle to free 0742 * 0743 * \return 0 on success\n 0744 * <0 - Negative POSIX Error code 0745 * 0746 * \note In the case of memory shared between different applications all 0747 * resources will be “physically” freed only all such applications 0748 * will be terminated 0749 * \note If is UMD responsibility to ‘free’ buffer only when there is no 0750 * more GPU access 0751 * 0752 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 0753 * 0754 */ 0755 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 0756 0757 /** 0758 * Increase the reference count of a buffer object 0759 * 0760 * \param bo - \c [in] Buffer object handle to increase the reference count 0761 * 0762 * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 0763 * 0764 */ 0765 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 0766 0767 /** 0768 * Request CPU access to GPU accessible memory 0769 * 0770 * \param buf_handle - \c [in] Buffer handle 0771 * \param cpu - \c [out] CPU address to be used for access 0772 * 0773 * \return 0 on success\n 0774 * <0 - Negative POSIX Error code 0775 * 0776 * \sa amdgpu_bo_cpu_unmap() 0777 * 0778 */ 0779 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 0780 0781 /** 0782 * Release CPU access to GPU memory 0783 * 0784 * \param buf_handle - \c [in] Buffer handle 0785 * 0786 * \return 0 on success\n 0787 * <0 - Negative POSIX Error code 0788 * 0789 * \sa amdgpu_bo_cpu_map() 0790 * 0791 */ 0792 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 0793 0794 /** 0795 * Wait until a buffer is not used by the device. 0796 * 0797 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0798 * \param buf_handle - \c [in] Buffer handle. 0799 * \param timeout_ns - Timeout in nanoseconds. 0800 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 0801 * and no GPU access is scheduled. 0802 * 1 GPU access is in fly or scheduled 0803 * 0804 * \return 0 - on success 0805 * <0 - Negative POSIX Error code 0806 */ 0807 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 0808 uint64_t timeout_ns, 0809 bool *buffer_busy); 0810 0811 /** 0812 * Creates a BO list handle for command submission. 0813 * 0814 * \param dev - \c [in] Device handle. 0815 * See #amdgpu_device_initialize() 0816 * \param number_of_buffers - \c [in] Number of BOs in the list 0817 * \param buffers - \c [in] List of BO handles 0818 * \param result - \c [out] Created BO list handle 0819 * 0820 * \return 0 on success\n 0821 * <0 - Negative POSIX Error code 0822 * 0823 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() 0824 */ 0825 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, 0826 uint32_t number_of_buffers, 0827 struct drm_amdgpu_bo_list_entry *buffers, 0828 uint32_t *result); 0829 0830 /** 0831 * Destroys a BO list handle. 0832 * 0833 * \param bo_list - \c [in] BO list handle. 0834 * 0835 * \return 0 on success\n 0836 * <0 - Negative POSIX Error code 0837 * 0838 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() 0839 */ 0840 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); 0841 0842 /** 0843 * Creates a BO list handle for command submission. 0844 * 0845 * \param dev - \c [in] Device handle. 0846 * See #amdgpu_device_initialize() 0847 * \param number_of_resources - \c [in] Number of BOs in the list 0848 * \param resources - \c [in] List of BO handles 0849 * \param resource_prios - \c [in] Optional priority for each handle 0850 * \param result - \c [out] Created BO list handle 0851 * 0852 * \return 0 on success\n 0853 * <0 - Negative POSIX Error code 0854 * 0855 * \sa amdgpu_bo_list_destroy() 0856 */ 0857 int amdgpu_bo_list_create(amdgpu_device_handle dev, 0858 uint32_t number_of_resources, 0859 amdgpu_bo_handle *resources, 0860 uint8_t *resource_prios, 0861 amdgpu_bo_list_handle *result); 0862 0863 /** 0864 * Destroys a BO list handle. 0865 * 0866 * \param handle - \c [in] BO list handle. 0867 * 0868 * \return 0 on success\n 0869 * <0 - Negative POSIX Error code 0870 * 0871 * \sa amdgpu_bo_list_create() 0872 */ 0873 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 0874 0875 /** 0876 * Update resources for existing BO list 0877 * 0878 * \param handle - \c [in] BO list handle 0879 * \param number_of_resources - \c [in] Number of BOs in the list 0880 * \param resources - \c [in] List of BO handles 0881 * \param resource_prios - \c [in] Optional priority for each handle 0882 * 0883 * \return 0 on success\n 0884 * <0 - Negative POSIX Error code 0885 * 0886 * \sa amdgpu_bo_list_update() 0887 */ 0888 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 0889 uint32_t number_of_resources, 0890 amdgpu_bo_handle *resources, 0891 uint8_t *resource_prios); 0892 0893 /* 0894 * GPU Execution context 0895 * 0896 */ 0897 0898 /** 0899 * Create GPU execution Context 0900 * 0901 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 0902 * necessary to have information/identify rendering/compute contexts. 0903 * It also may be needed to associate some specific requirements with such 0904 * contexts. Kernel driver will guarantee that submission from the same 0905 * context will always be executed in order (first come, first serve). 0906 * 0907 * 0908 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0909 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 0910 * \param context - \c [out] GPU Context handle 0911 * 0912 * \return 0 on success\n 0913 * <0 - Negative POSIX Error code 0914 * 0915 * \sa amdgpu_cs_ctx_free() 0916 * 0917 */ 0918 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 0919 uint32_t priority, 0920 amdgpu_context_handle *context); 0921 /** 0922 * Create GPU execution Context 0923 * 0924 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 0925 * is missing the priority parameter. 0926 * 0927 * \sa amdgpu_cs_ctx_create2() 0928 * 0929 */ 0930 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 0931 amdgpu_context_handle *context); 0932 0933 /** 0934 * 0935 * Destroy GPU execution context when not needed any more 0936 * 0937 * \param context - \c [in] GPU Context handle 0938 * 0939 * \return 0 on success\n 0940 * <0 - Negative POSIX Error code 0941 * 0942 * \sa amdgpu_cs_ctx_create() 0943 * 0944 */ 0945 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 0946 0947 /** 0948 * Override the submission priority for the given context using a master fd. 0949 * 0950 * \param dev - \c [in] device handle 0951 * \param context - \c [in] context handle for context id 0952 * \param master_fd - \c [in] The master fd to authorize the override. 0953 * \param priority - \c [in] The priority to assign to the context. 0954 * 0955 * \return 0 on success or a a negative Posix error code on failure. 0956 */ 0957 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, 0958 amdgpu_context_handle context, 0959 int master_fd, 0960 unsigned priority); 0961 0962 /** 0963 * Set or query the stable power state for GPU profiling. 0964 * 0965 * \param dev - \c [in] device handle 0966 * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE 0967 * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_* 0968 * \param out_flags - \c [out] output current stable pstate 0969 * 0970 * \return 0 on success otherwise POSIX Error code. 0971 */ 0972 int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, 0973 uint32_t op, 0974 uint32_t flags, 0975 uint32_t *out_flags); 0976 0977 /** 0978 * Query reset state for the specific GPU Context 0979 * 0980 * \param context - \c [in] GPU Context handle 0981 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 0982 * \param hangs - \c [out] Number of hangs caused by the context. 0983 * 0984 * \return 0 on success\n 0985 * <0 - Negative POSIX Error code 0986 * 0987 * \sa amdgpu_cs_ctx_create() 0988 * 0989 */ 0990 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 0991 uint32_t *state, uint32_t *hangs); 0992 0993 /** 0994 * Query reset state for the specific GPU Context. 0995 * 0996 * \param context - \c [in] GPU Context handle 0997 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_* 0998 * 0999 * \return 0 on success\n 1000 * <0 - Negative POSIX Error code 1001 * 1002 * \sa amdgpu_cs_ctx_create() 1003 * 1004 */ 1005 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context, 1006 uint64_t *flags); 1007 1008 /* 1009 * Command Buffers Management 1010 * 1011 */ 1012 1013 /** 1014 * Send request to submit command buffers to hardware. 1015 * 1016 * Kernel driver could use GPU Scheduler to make decision when physically 1017 * sent this request to the hardware. Accordingly this request could be put 1018 * in queue and sent for execution later. The only guarantee is that request 1019 * from the same GPU context to the same ip:ip_instance:ring will be executed in 1020 * order. 1021 * 1022 * The caller can specify the user fence buffer/location with the fence_info in the 1023 * cs_request.The sequence number is returned via the 'seq_no' parameter 1024 * in ibs_request structure. 1025 * 1026 * 1027 * \param dev - \c [in] Device handle. 1028 * See #amdgpu_device_initialize() 1029 * \param context - \c [in] GPU Context 1030 * \param flags - \c [in] Global submission flags 1031 * \param ibs_request - \c [in/out] Pointer to submission requests. 1032 * We could submit to the several 1033 * engines/rings simulteniously as 1034 * 'atomic' operation 1035 * \param number_of_requests - \c [in] Number of submission requests 1036 * 1037 * \return 0 on success\n 1038 * <0 - Negative POSIX Error code 1039 * 1040 * \note It is required to pass correct resource list with buffer handles 1041 * which will be accessible by command buffers from submission 1042 * This will allow kernel driver to correctly implement "paging". 1043 * Failure to do so will have unpredictable results. 1044 * 1045 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 1046 * amdgpu_cs_query_fence_status() 1047 * 1048 */ 1049 int amdgpu_cs_submit(amdgpu_context_handle context, 1050 uint64_t flags, 1051 struct amdgpu_cs_request *ibs_request, 1052 uint32_t number_of_requests); 1053 1054 /** 1055 * Query status of Command Buffer Submission 1056 * 1057 * \param fence - \c [in] Structure describing fence to query 1058 * \param timeout_ns - \c [in] Timeout value to wait 1059 * \param flags - \c [in] Flags for the query 1060 * \param expired - \c [out] If fence expired or not.\n 1061 * 0 – if fence is not expired\n 1062 * !0 - otherwise 1063 * 1064 * \return 0 on success\n 1065 * <0 - Negative POSIX Error code 1066 * 1067 * \note If UMD wants only to check operation status and returned immediately 1068 * then timeout value as 0 must be passed. In this case success will be 1069 * returned in the case if submission was completed or timeout error 1070 * code. 1071 * 1072 * \sa amdgpu_cs_submit() 1073 */ 1074 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 1075 uint64_t timeout_ns, 1076 uint64_t flags, 1077 uint32_t *expired); 1078 1079 /** 1080 * Wait for multiple fences 1081 * 1082 * \param fences - \c [in] The fence array to wait 1083 * \param fence_count - \c [in] The fence count 1084 * \param wait_all - \c [in] If true, wait all fences to be signaled, 1085 * otherwise, wait at least one fence 1086 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 1087 * \param status - \c [out] '1' for signaled, '0' for timeout 1088 * \param first - \c [out] the index of the first signaled fence from @fences 1089 * 1090 * \return 0 on success 1091 * <0 - Negative POSIX Error code 1092 * 1093 * \note Currently it supports only one amdgpu_device. All fences come from 1094 * the same amdgpu_device with the same fd. 1095 */ 1096 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 1097 uint32_t fence_count, 1098 bool wait_all, 1099 uint64_t timeout_ns, 1100 uint32_t *status, uint32_t *first); 1101 1102 /* 1103 * Query / Info API 1104 * 1105 */ 1106 1107 /** 1108 * Query allocation size alignments 1109 * 1110 * UMD should query information about GPU VM MC size alignments requirements 1111 * to be able correctly choose required allocation size and implement 1112 * internal optimization if needed. 1113 * 1114 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1115 * \param info - \c [out] Pointer to structure to get size alignment 1116 * requirements 1117 * 1118 * \return 0 on success\n 1119 * <0 - Negative POSIX Error code 1120 * 1121 */ 1122 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 1123 struct amdgpu_buffer_size_alignments 1124 *info); 1125 1126 /** 1127 * Query firmware versions 1128 * 1129 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1130 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 1131 * \param ip_instance - \c [in] Index of the IP block of the same type. 1132 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 1133 * \param version - \c [out] Pointer to to the "version" return value 1134 * \param feature - \c [out] Pointer to to the "feature" return value 1135 * 1136 * \return 0 on success\n 1137 * <0 - Negative POSIX Error code 1138 * 1139 */ 1140 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 1141 unsigned ip_instance, unsigned index, 1142 uint32_t *version, uint32_t *feature); 1143 1144 /** 1145 * Query the number of HW IP instances of a certain type. 1146 * 1147 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1148 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1149 * \param count - \c [out] Pointer to structure to get information 1150 * 1151 * \return 0 on success\n 1152 * <0 - Negative POSIX Error code 1153 */ 1154 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1155 uint32_t *count); 1156 1157 /** 1158 * Query engine information 1159 * 1160 * This query allows UMD to query information different engines and their 1161 * capabilities. 1162 * 1163 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1164 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1165 * \param ip_instance - \c [in] Index of the IP block of the same type. 1166 * \param info - \c [out] Pointer to structure to get information 1167 * 1168 * \return 0 on success\n 1169 * <0 - Negative POSIX Error code 1170 */ 1171 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1172 unsigned ip_instance, 1173 struct drm_amdgpu_info_hw_ip *info); 1174 1175 /** 1176 * Query heap information 1177 * 1178 * This query allows UMD to query potentially available memory resources and 1179 * adjust their logic if necessary. 1180 * 1181 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1182 * \param heap - \c [in] Heap type 1183 * \param info - \c [in] Pointer to structure to get needed information 1184 * 1185 * \return 0 on success\n 1186 * <0 - Negative POSIX Error code 1187 * 1188 */ 1189 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1190 uint32_t flags, struct amdgpu_heap_info *info); 1191 1192 /** 1193 * Get the CRTC ID from the mode object ID 1194 * 1195 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1196 * \param id - \c [in] Mode object ID 1197 * \param result - \c [in] Pointer to the CRTC ID 1198 * 1199 * \return 0 on success\n 1200 * <0 - Negative POSIX Error code 1201 * 1202 */ 1203 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1204 int32_t *result); 1205 1206 /** 1207 * Query GPU H/w Info 1208 * 1209 * Query hardware specific information 1210 * 1211 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1212 * \param heap - \c [in] Heap type 1213 * \param info - \c [in] Pointer to structure to get needed information 1214 * 1215 * \return 0 on success\n 1216 * <0 - Negative POSIX Error code 1217 * 1218 */ 1219 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1220 struct amdgpu_gpu_info *info); 1221 1222 /** 1223 * Query hardware or driver information. 1224 * 1225 * The return size is query-specific and depends on the "info_id" parameter. 1226 * No more than "size" bytes is returned. 1227 * 1228 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1229 * \param info_id - \c [in] AMDGPU_INFO_* 1230 * \param size - \c [in] Size of the returned value. 1231 * \param value - \c [out] Pointer to the return value. 1232 * 1233 * \return 0 on success\n 1234 * <0 - Negative POSIX error code 1235 * 1236 */ 1237 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1238 unsigned size, void *value); 1239 1240 /** 1241 * Query hardware or driver information. 1242 * 1243 * The return size is query-specific and depends on the "info_id" parameter. 1244 * No more than "size" bytes is returned. 1245 * 1246 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1247 * \param info - \c [in] amdgpu_sw_info_* 1248 * \param value - \c [out] Pointer to the return value. 1249 * 1250 * \return 0 on success\n 1251 * <0 - Negative POSIX error code 1252 * 1253 */ 1254 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1255 void *value); 1256 1257 /** 1258 * Query information about GDS 1259 * 1260 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1261 * \param gds_info - \c [out] Pointer to structure to get GDS information 1262 * 1263 * \return 0 on success\n 1264 * <0 - Negative POSIX Error code 1265 * 1266 */ 1267 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1268 struct amdgpu_gds_resource_info *gds_info); 1269 1270 /** 1271 * Query information about sensor. 1272 * 1273 * The return size is query-specific and depends on the "sensor_type" 1274 * parameter. No more than "size" bytes is returned. 1275 * 1276 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1277 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1278 * \param size - \c [in] Size of the returned value. 1279 * \param value - \c [out] Pointer to the return value. 1280 * 1281 * \return 0 on success\n 1282 * <0 - Negative POSIX Error code 1283 * 1284 */ 1285 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1286 unsigned size, void *value); 1287 1288 /** 1289 * Query information about video capabilities 1290 * 1291 * The return sizeof(struct drm_amdgpu_info_video_caps) 1292 * 1293 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1294 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) 1295 * \param size - \c [in] Size of the returned value. 1296 * \param value - \c [out] Pointer to the return value. 1297 * 1298 * \return 0 on success\n 1299 * <0 - Negative POSIX Error code 1300 * 1301 */ 1302 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 1303 unsigned size, void *value); 1304 1305 /** 1306 * Query information about VM faults 1307 * 1308 * The return sizeof(struct drm_amdgpu_info_gpuvm_fault) 1309 * 1310 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1311 * \param size - \c [in] Size of the returned value. 1312 * \param value - \c [out] Pointer to the return value. 1313 * 1314 * \return 0 on success\n 1315 * <0 - Negative POSIX Error code 1316 * 1317 */ 1318 int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size, 1319 void *value); 1320 1321 /** 1322 * Read a set of consecutive memory-mapped registers. 1323 * Not all registers are allowed to be read by userspace. 1324 * 1325 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1326 * \param dword_offset - \c [in] Register offset in dwords 1327 * \param count - \c [in] The number of registers to read starting 1328 * from the offset 1329 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1330 * uses. Set it to 0xffffffff if unsure. 1331 * \param flags - \c [in] Flags with additional information. 1332 * \param values - \c [out] The pointer to return values. 1333 * 1334 * \return 0 on success\n 1335 * <0 - Negative POSIX error code 1336 * 1337 */ 1338 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1339 unsigned count, uint32_t instance, uint32_t flags, 1340 uint32_t *values); 1341 1342 /** 1343 * Flag to request VA address range in the 32bit address space 1344 */ 1345 #define AMDGPU_VA_RANGE_32_BIT 0x1 1346 #define AMDGPU_VA_RANGE_HIGH 0x2 1347 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4 1348 1349 /** 1350 * Allocate virtual address range 1351 * 1352 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1353 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1354 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1355 * It is client responsibility to correctly aligned size based on the future 1356 * usage of allocated range. 1357 * \param va_base_alignment - \c [in] Overwrite base address alignment 1358 * requirement for GPU VM MC virtual 1359 * address assignment. Must be multiple of size alignments received as 1360 * 'amdgpu_buffer_size_alignments'. 1361 * If 0 use the default one. 1362 * \param va_base_required - \c [in] Specified required va base address. 1363 * If 0 then library choose available one. 1364 * If !0 value will be passed and those value already "in use" then 1365 * corresponding error status will be returned. 1366 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1367 * by client. 1368 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1369 * \param flags - \c [in] flags for special VA range 1370 * 1371 * \return 0 on success\n 1372 * >0 - AMD specific error code\n 1373 * <0 - Negative POSIX Error code 1374 * 1375 * \notes \n 1376 * It is client responsibility to correctly handle VA assignments and usage. 1377 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1378 * detect wrong va assignment. 1379 * 1380 * It is client responsibility to correctly handle multi-GPU cases and to pass 1381 * the corresponding arrays of all devices handles where corresponding VA will 1382 * be used. 1383 * 1384 */ 1385 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1386 enum amdgpu_gpu_va_range va_range_type, 1387 uint64_t size, 1388 uint64_t va_base_alignment, 1389 uint64_t va_base_required, 1390 uint64_t *va_base_allocated, 1391 amdgpu_va_handle *va_range_handle, 1392 uint64_t flags); 1393 1394 /** 1395 * Free previously allocated virtual address range 1396 * 1397 * 1398 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1399 * 1400 * \return 0 on success\n 1401 * >0 - AMD specific error code\n 1402 * <0 - Negative POSIX Error code 1403 * 1404 */ 1405 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1406 1407 /** 1408 * Return the starting address of the allocated virtual address range. 1409 */ 1410 uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle); 1411 1412 /** 1413 * Query virtual address range 1414 * 1415 * UMD can query GPU VM range supported by each device 1416 * to initialize its own VAM accordingly. 1417 * 1418 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1419 * \param type - \c [in] Type of virtual address range 1420 * \param offset - \c [out] Start offset of virtual address range 1421 * \param size - \c [out] Size of virtual address range 1422 * 1423 * \return 0 on success\n 1424 * <0 - Negative POSIX Error code 1425 * 1426 */ 1427 1428 int amdgpu_va_range_query(amdgpu_device_handle dev, 1429 enum amdgpu_gpu_va_range type, 1430 uint64_t *start, 1431 uint64_t *end); 1432 1433 /** 1434 * Allocate a amdgpu_va_manager object. 1435 * The returned object has be initialized with the amdgpu_va_manager_init 1436 * before use. 1437 * On release, amdgpu_va_manager_deinit needs to be called, then the memory 1438 * can be released using free(). 1439 */ 1440 amdgpu_va_manager_handle amdgpu_va_manager_alloc(void); 1441 1442 void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr, 1443 uint64_t low_va_offset, uint64_t low_va_max, 1444 uint64_t high_va_offset, uint64_t high_va_max, 1445 uint32_t virtual_address_alignment); 1446 1447 void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr); 1448 1449 /** 1450 * Similar to #amdgpu_va_range_alloc() but allocates VA 1451 * directly from an amdgpu_va_manager_handle instead of using 1452 * the manager from an amdgpu_device. 1453 */ 1454 1455 int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr, 1456 enum amdgpu_gpu_va_range va_range_type, 1457 uint64_t size, 1458 uint64_t va_base_alignment, 1459 uint64_t va_base_required, 1460 uint64_t *va_base_allocated, 1461 amdgpu_va_handle *va_range_handle, 1462 uint64_t flags); 1463 1464 /** 1465 * VA mapping/unmapping for the buffer object 1466 * 1467 * \param bo - \c [in] BO handle 1468 * \param offset - \c [in] Start offset to map 1469 * \param size - \c [in] Size to map 1470 * \param addr - \c [in] Start virtual address. 1471 * \param flags - \c [in] Supported flags for mapping/unmapping 1472 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1473 * 1474 * \return 0 on success\n 1475 * <0 - Negative POSIX Error code 1476 * 1477 */ 1478 1479 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1480 uint64_t offset, 1481 uint64_t size, 1482 uint64_t addr, 1483 uint64_t flags, 1484 uint32_t ops); 1485 1486 /** 1487 * VA mapping/unmapping for a buffer object or PRT region. 1488 * 1489 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1490 * parameters are treated "raw", i.e. size is not automatically aligned, and 1491 * all flags must be specified explicitly. 1492 * 1493 * \param dev - \c [in] device handle 1494 * \param bo - \c [in] BO handle (may be NULL) 1495 * \param offset - \c [in] Start offset to map 1496 * \param size - \c [in] Size to map 1497 * \param addr - \c [in] Start virtual address. 1498 * \param flags - \c [in] Supported flags for mapping/unmapping 1499 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1500 * 1501 * \return 0 on success\n 1502 * <0 - Negative POSIX Error code 1503 * 1504 */ 1505 1506 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1507 amdgpu_bo_handle bo, 1508 uint64_t offset, 1509 uint64_t size, 1510 uint64_t addr, 1511 uint64_t flags, 1512 uint32_t ops); 1513 1514 /** 1515 * create semaphore 1516 * 1517 * \param sem - \c [out] semaphore handle 1518 * 1519 * \return 0 on success\n 1520 * <0 - Negative POSIX Error code 1521 * 1522 */ 1523 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1524 1525 /** 1526 * signal semaphore 1527 * 1528 * \param context - \c [in] GPU Context 1529 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1530 * \param ip_instance - \c [in] Index of the IP block of the same type 1531 * \param ring - \c [in] Specify ring index of the IP 1532 * \param sem - \c [in] semaphore handle 1533 * 1534 * \return 0 on success\n 1535 * <0 - Negative POSIX Error code 1536 * 1537 */ 1538 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1539 uint32_t ip_type, 1540 uint32_t ip_instance, 1541 uint32_t ring, 1542 amdgpu_semaphore_handle sem); 1543 1544 /** 1545 * wait semaphore 1546 * 1547 * \param context - \c [in] GPU Context 1548 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1549 * \param ip_instance - \c [in] Index of the IP block of the same type 1550 * \param ring - \c [in] Specify ring index of the IP 1551 * \param sem - \c [in] semaphore handle 1552 * 1553 * \return 0 on success\n 1554 * <0 - Negative POSIX Error code 1555 * 1556 */ 1557 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1558 uint32_t ip_type, 1559 uint32_t ip_instance, 1560 uint32_t ring, 1561 amdgpu_semaphore_handle sem); 1562 1563 /** 1564 * destroy semaphore 1565 * 1566 * \param sem - \c [in] semaphore handle 1567 * 1568 * \return 0 on success\n 1569 * <0 - Negative POSIX Error code 1570 * 1571 */ 1572 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1573 1574 /** 1575 * Get the ASIC marketing name 1576 * 1577 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1578 * 1579 * \return the constant string of the marketing name 1580 * "NULL" means the ASIC is not found 1581 */ 1582 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1583 1584 /** 1585 * Create kernel sync object 1586 * 1587 * \param dev - \c [in] device handle 1588 * \param flags - \c [in] flags that affect creation 1589 * \param syncobj - \c [out] sync object handle 1590 * 1591 * \return 0 on success\n 1592 * <0 - Negative POSIX Error code 1593 * 1594 */ 1595 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1596 uint32_t flags, 1597 uint32_t *syncobj); 1598 1599 /** 1600 * Create kernel sync object 1601 * 1602 * \param dev - \c [in] device handle 1603 * \param syncobj - \c [out] sync object handle 1604 * 1605 * \return 0 on success\n 1606 * <0 - Negative POSIX Error code 1607 * 1608 */ 1609 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1610 uint32_t *syncobj); 1611 /** 1612 * Destroy kernel sync object 1613 * 1614 * \param dev - \c [in] device handle 1615 * \param syncobj - \c [in] sync object handle 1616 * 1617 * \return 0 on success\n 1618 * <0 - Negative POSIX Error code 1619 * 1620 */ 1621 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1622 uint32_t syncobj); 1623 1624 /** 1625 * Reset kernel sync objects to unsignalled state. 1626 * 1627 * \param dev - \c [in] device handle 1628 * \param syncobjs - \c [in] array of sync object handles 1629 * \param syncobj_count - \c [in] number of handles in syncobjs 1630 * 1631 * \return 0 on success\n 1632 * <0 - Negative POSIX Error code 1633 * 1634 */ 1635 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1636 const uint32_t *syncobjs, uint32_t syncobj_count); 1637 1638 /** 1639 * Signal kernel sync objects. 1640 * 1641 * \param dev - \c [in] device handle 1642 * \param syncobjs - \c [in] array of sync object handles 1643 * \param syncobj_count - \c [in] number of handles in syncobjs 1644 * 1645 * \return 0 on success\n 1646 * <0 - Negative POSIX Error code 1647 * 1648 */ 1649 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1650 const uint32_t *syncobjs, uint32_t syncobj_count); 1651 1652 /** 1653 * Signal kernel timeline sync objects. 1654 * 1655 * \param dev - \c [in] device handle 1656 * \param syncobjs - \c [in] array of sync object handles 1657 * \param points - \c [in] array of timeline points 1658 * \param syncobj_count - \c [in] number of handles in syncobjs 1659 * 1660 * \return 0 on success\n 1661 * <0 - Negative POSIX Error code 1662 * 1663 */ 1664 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev, 1665 const uint32_t *syncobjs, 1666 uint64_t *points, 1667 uint32_t syncobj_count); 1668 1669 /** 1670 * Wait for one or all sync objects to signal. 1671 * 1672 * \param dev - \c [in] self-explanatory 1673 * \param handles - \c [in] array of sync object handles 1674 * \param num_handles - \c [in] self-explanatory 1675 * \param timeout_nsec - \c [in] self-explanatory 1676 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1677 * \param first_signaled - \c [in] self-explanatory 1678 * 1679 * \return 0 on success\n 1680 * -ETIME - Timeout 1681 * <0 - Negative POSIX Error code 1682 * 1683 */ 1684 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1685 uint32_t *handles, unsigned num_handles, 1686 int64_t timeout_nsec, unsigned flags, 1687 uint32_t *first_signaled); 1688 1689 /** 1690 * Wait for one or all sync objects on their points to signal. 1691 * 1692 * \param dev - \c [in] self-explanatory 1693 * \param handles - \c [in] array of sync object handles 1694 * \param points - \c [in] array of sync points to wait 1695 * \param num_handles - \c [in] self-explanatory 1696 * \param timeout_nsec - \c [in] self-explanatory 1697 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1698 * \param first_signaled - \c [in] self-explanatory 1699 * 1700 * \return 0 on success\n 1701 * -ETIME - Timeout 1702 * <0 - Negative POSIX Error code 1703 * 1704 */ 1705 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev, 1706 uint32_t *handles, uint64_t *points, 1707 unsigned num_handles, 1708 int64_t timeout_nsec, unsigned flags, 1709 uint32_t *first_signaled); 1710 /** 1711 * Query sync objects payloads. 1712 * 1713 * \param dev - \c [in] self-explanatory 1714 * \param handles - \c [in] array of sync object handles 1715 * \param points - \c [out] array of sync points returned, which presents 1716 * syncobj payload. 1717 * \param num_handles - \c [in] self-explanatory 1718 * 1719 * \return 0 on success\n 1720 * -ETIME - Timeout 1721 * <0 - Negative POSIX Error code 1722 * 1723 */ 1724 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev, 1725 uint32_t *handles, uint64_t *points, 1726 unsigned num_handles); 1727 /** 1728 * Query sync objects last signaled or submitted point. 1729 * 1730 * \param dev - \c [in] self-explanatory 1731 * \param handles - \c [in] array of sync object handles 1732 * \param points - \c [out] array of sync points returned, which presents 1733 * syncobj payload. 1734 * \param num_handles - \c [in] self-explanatory 1735 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_* 1736 * 1737 * \return 0 on success\n 1738 * -ETIME - Timeout 1739 * <0 - Negative POSIX Error code 1740 * 1741 */ 1742 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev, 1743 uint32_t *handles, uint64_t *points, 1744 unsigned num_handles, uint32_t flags); 1745 1746 /** 1747 * Export kernel sync object to shareable fd. 1748 * 1749 * \param dev - \c [in] device handle 1750 * \param syncobj - \c [in] sync object handle 1751 * \param shared_fd - \c [out] shared file descriptor. 1752 * 1753 * \return 0 on success\n 1754 * <0 - Negative POSIX Error code 1755 * 1756 */ 1757 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1758 uint32_t syncobj, 1759 int *shared_fd); 1760 /** 1761 * Import kernel sync object from shareable fd. 1762 * 1763 * \param dev - \c [in] device handle 1764 * \param shared_fd - \c [in] shared file descriptor. 1765 * \param syncobj - \c [out] sync object handle 1766 * 1767 * \return 0 on success\n 1768 * <0 - Negative POSIX Error code 1769 * 1770 */ 1771 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1772 int shared_fd, 1773 uint32_t *syncobj); 1774 1775 /** 1776 * Export kernel sync object to a sync_file. 1777 * 1778 * \param dev - \c [in] device handle 1779 * \param syncobj - \c [in] sync object handle 1780 * \param sync_file_fd - \c [out] sync_file file descriptor. 1781 * 1782 * \return 0 on success\n 1783 * <0 - Negative POSIX Error code 1784 * 1785 */ 1786 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1787 uint32_t syncobj, 1788 int *sync_file_fd); 1789 1790 /** 1791 * Import kernel sync object from a sync_file. 1792 * 1793 * \param dev - \c [in] device handle 1794 * \param syncobj - \c [in] sync object handle 1795 * \param sync_file_fd - \c [in] sync_file file descriptor. 1796 * 1797 * \return 0 on success\n 1798 * <0 - Negative POSIX Error code 1799 * 1800 */ 1801 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1802 uint32_t syncobj, 1803 int sync_file_fd); 1804 /** 1805 * Export kernel timeline sync object to a sync_file. 1806 * 1807 * \param dev - \c [in] device handle 1808 * \param syncobj - \c [in] sync object handle 1809 * \param point - \c [in] timeline point 1810 * \param flags - \c [in] flags 1811 * \param sync_file_fd - \c [out] sync_file file descriptor. 1812 * 1813 * \return 0 on success\n 1814 * <0 - Negative POSIX Error code 1815 * 1816 */ 1817 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev, 1818 uint32_t syncobj, 1819 uint64_t point, 1820 uint32_t flags, 1821 int *sync_file_fd); 1822 1823 /** 1824 * Import kernel timeline sync object from a sync_file. 1825 * 1826 * \param dev - \c [in] device handle 1827 * \param syncobj - \c [in] sync object handle 1828 * \param point - \c [in] timeline point 1829 * \param sync_file_fd - \c [in] sync_file file descriptor. 1830 * 1831 * \return 0 on success\n 1832 * <0 - Negative POSIX Error code 1833 * 1834 */ 1835 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev, 1836 uint32_t syncobj, 1837 uint64_t point, 1838 int sync_file_fd); 1839 1840 /** 1841 * transfer between syncbojs. 1842 * 1843 * \param dev - \c [in] device handle 1844 * \param dst_handle - \c [in] sync object handle 1845 * \param dst_point - \c [in] timeline point, 0 presents dst is binary 1846 * \param src_handle - \c [in] sync object handle 1847 * \param src_point - \c [in] timeline point, 0 presents src is binary 1848 * \param flags - \c [in] flags 1849 * 1850 * \return 0 on success\n 1851 * <0 - Negative POSIX Error code 1852 * 1853 */ 1854 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev, 1855 uint32_t dst_handle, 1856 uint64_t dst_point, 1857 uint32_t src_handle, 1858 uint64_t src_point, 1859 uint32_t flags); 1860 1861 /** 1862 * Export an amdgpu fence as a handle (syncobj or fd). 1863 * 1864 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1865 * \param out_handle returned handle 1866 * 1867 * \return 0 on success\n 1868 * <0 - Negative POSIX Error code 1869 */ 1870 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1871 struct amdgpu_cs_fence *fence, 1872 uint32_t what, 1873 uint32_t *out_handle); 1874 1875 /** 1876 * Submit raw command submission to kernel 1877 * 1878 * \param dev - \c [in] device handle 1879 * \param context - \c [in] context handle for context id 1880 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1881 * \param num_chunks - \c [in] number of CS chunks to submit 1882 * \param chunks - \c [in] array of CS chunks 1883 * \param seq_no - \c [out] output sequence number for submission. 1884 * 1885 * \return 0 on success\n 1886 * <0 - Negative POSIX Error code 1887 * 1888 */ 1889 struct drm_amdgpu_cs_chunk; 1890 struct drm_amdgpu_cs_chunk_dep; 1891 struct drm_amdgpu_cs_chunk_data; 1892 1893 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1894 amdgpu_context_handle context, 1895 amdgpu_bo_list_handle bo_list_handle, 1896 int num_chunks, 1897 struct drm_amdgpu_cs_chunk *chunks, 1898 uint64_t *seq_no); 1899 1900 /** 1901 * Submit raw command submission to the kernel with a raw BO list handle. 1902 * 1903 * \param dev - \c [in] device handle 1904 * \param context - \c [in] context handle for context id 1905 * \param bo_list_handle - \c [in] raw bo list handle (0 for none) 1906 * \param num_chunks - \c [in] number of CS chunks to submit 1907 * \param chunks - \c [in] array of CS chunks 1908 * \param seq_no - \c [out] output sequence number for submission. 1909 * 1910 * \return 0 on success\n 1911 * <0 - Negative POSIX Error code 1912 * 1913 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() 1914 */ 1915 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, 1916 amdgpu_context_handle context, 1917 uint32_t bo_list_handle, 1918 int num_chunks, 1919 struct drm_amdgpu_cs_chunk *chunks, 1920 uint64_t *seq_no); 1921 1922 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 1923 struct drm_amdgpu_cs_chunk_dep *dep); 1924 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 1925 struct drm_amdgpu_cs_chunk_data *data); 1926 1927 /** 1928 * Reserve VMID 1929 * \param context - \c [in] GPU Context 1930 * \param flags - \c [in] TBD 1931 * 1932 * \return 0 on success otherwise POSIX Error code 1933 */ 1934 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1935 1936 /** 1937 * Free reserved VMID 1938 * \param context - \c [in] GPU Context 1939 * \param flags - \c [in] TBD 1940 * 1941 * \return 0 on success otherwise POSIX Error code 1942 */ 1943 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1944 1945 #ifdef __cplusplus 1946 } 1947 #endif 1948 #endif /* #ifdef _AMDGPU_H_ */
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