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File indexing completed on 2026-09-10 09:14:05
0001 /* 0002 * Copyright 2014 Advanced Micro Devices, Inc. 0003 * 0004 * Permission is hereby granted, free of charge, to any person obtaining a 0005 * copy of this software and associated documentation files (the "Software"), 0006 * to deal in the Software without restriction, including without limitation 0007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 0008 * and/or sell copies of the Software, and to permit persons to whom the 0009 * Software is furnished to do so, subject to the following conditions: 0010 * 0011 * The above copyright notice and this permission notice shall be included in 0012 * all copies or substantial portions of the Software. 0013 * 0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 0017 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 0018 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 0019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 0020 * OTHER DEALINGS IN THE SOFTWARE. 0021 * 0022 */ 0023 0024 /** 0025 * \file amdgpu.h 0026 * 0027 * Declare public libdrm_amdgpu API 0028 * 0029 * This file define API exposed by libdrm_amdgpu library. 0030 * User wanted to use libdrm_amdgpu functionality must include 0031 * this file. 0032 * 0033 */ 0034 #ifndef _AMDGPU_H_ 0035 #define _AMDGPU_H_ 0036 0037 #include <stdint.h> 0038 #include <stdbool.h> 0039 0040 #ifdef __cplusplus 0041 extern "C" { 0042 #endif 0043 0044 struct drm_amdgpu_info_hw_ip; 0045 struct drm_amdgpu_info_uq_fw_areas; 0046 struct drm_amdgpu_bo_list_entry; 0047 struct drm_amdgpu_userq_signal; 0048 struct drm_amdgpu_userq_wait; 0049 0050 /*--------------------------------------------------------------------------*/ 0051 /* --------------------------- Defines ------------------------------------ */ 0052 /*--------------------------------------------------------------------------*/ 0053 0054 /** 0055 * Define max. number of Command Buffers (IB) which could be sent to the single 0056 * hardware IP to accommodate CE/DE requirements 0057 * 0058 * \sa amdgpu_cs_ib_info 0059 */ 0060 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 0061 0062 /** 0063 * Special timeout value meaning that the timeout is infinite. 0064 */ 0065 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 0066 0067 /** 0068 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 0069 * is absolute. 0070 */ 0071 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 0072 0073 /*--------------------------------------------------------------------------*/ 0074 /* ----------------------------- Enums ------------------------------------ */ 0075 /*--------------------------------------------------------------------------*/ 0076 0077 /** 0078 * Enum describing possible handle types 0079 * 0080 * \sa amdgpu_bo_import, amdgpu_bo_export 0081 * 0082 */ 0083 enum amdgpu_bo_handle_type { 0084 /** GEM flink name (needs DRM authentication, used by DRI2) */ 0085 amdgpu_bo_handle_type_gem_flink_name = 0, 0086 0087 /** KMS handle which is used by all driver ioctls */ 0088 amdgpu_bo_handle_type_kms = 1, 0089 0090 /** DMA-buf fd handle */ 0091 amdgpu_bo_handle_type_dma_buf_fd = 2, 0092 0093 /** Deprecated in favour of and same behaviour as 0094 * amdgpu_bo_handle_type_kms, use that instead of this 0095 */ 0096 amdgpu_bo_handle_type_kms_noimport = 3, 0097 }; 0098 0099 /** Define known types of GPU VM VA ranges */ 0100 enum amdgpu_gpu_va_range 0101 { 0102 /** Allocate from "normal"/general range */ 0103 amdgpu_gpu_va_range_general = 0 0104 }; 0105 0106 enum amdgpu_sw_info { 0107 amdgpu_sw_info_address32_hi = 0, 0108 }; 0109 0110 /*--------------------------------------------------------------------------*/ 0111 /* -------------------------- Datatypes ----------------------------------- */ 0112 /*--------------------------------------------------------------------------*/ 0113 0114 /** 0115 * Define opaque pointer to context associated with fd. 0116 * This context will be returned as the result of 0117 * "initialize" function and should be pass as the first 0118 * parameter to any API call 0119 */ 0120 typedef struct amdgpu_device *amdgpu_device_handle; 0121 0122 /** 0123 * Define GPU Context type as pointer to opaque structure 0124 * Example of GPU Context is the "rendering" context associated 0125 * with OpenGL context (glCreateContext) 0126 */ 0127 typedef struct amdgpu_context *amdgpu_context_handle; 0128 0129 /** 0130 * Define handle for amdgpu resources: buffer, GDS, etc. 0131 */ 0132 typedef struct amdgpu_bo *amdgpu_bo_handle; 0133 0134 /** 0135 * Define handle for list of BOs 0136 */ 0137 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 0138 0139 /** 0140 * Define handle to be used to work with VA allocated ranges 0141 */ 0142 typedef struct amdgpu_va *amdgpu_va_handle; 0143 0144 /** 0145 * Define handle dealing with VA allocation. An amdgpu_device 0146 * owns one of these, but they can also be used without a device. 0147 */ 0148 typedef struct amdgpu_va_manager *amdgpu_va_manager_handle; 0149 0150 /** 0151 * Define handle for semaphore 0152 */ 0153 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 0154 0155 /*--------------------------------------------------------------------------*/ 0156 /* -------------------------- Structures ---------------------------------- */ 0157 /*--------------------------------------------------------------------------*/ 0158 0159 /** 0160 * Structure describing memory allocation request 0161 * 0162 * \sa amdgpu_bo_alloc() 0163 * 0164 */ 0165 struct amdgpu_bo_alloc_request { 0166 /** Allocation request. It must be aligned correctly. */ 0167 uint64_t alloc_size; 0168 0169 /** 0170 * It may be required to have some specific alignment requirements 0171 * for physical back-up storage (e.g. for displayable surface). 0172 * If 0 there is no special alignment requirement 0173 */ 0174 uint64_t phys_alignment; 0175 0176 /** 0177 * UMD should specify where to allocate memory and how it 0178 * will be accessed by the CPU. 0179 */ 0180 uint32_t preferred_heap; 0181 0182 /** Additional flags passed on allocation */ 0183 uint64_t flags; 0184 }; 0185 0186 /** 0187 * Special UMD specific information associated with buffer. 0188 * 0189 * It may be need to pass some buffer charactersitic as part 0190 * of buffer sharing. Such information are defined UMD and 0191 * opaque for libdrm_amdgpu as well for kernel driver. 0192 * 0193 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 0194 * amdgpu_bo_import(), amdgpu_bo_export 0195 * 0196 */ 0197 struct amdgpu_bo_metadata { 0198 /** Special flag associated with surface */ 0199 uint64_t flags; 0200 0201 /** 0202 * ASIC-specific tiling information (also used by DCE). 0203 * The encoding is defined by the AMDGPU_TILING_* definitions. 0204 */ 0205 uint64_t tiling_info; 0206 0207 /** Size of metadata associated with the buffer, in bytes. */ 0208 uint32_t size_metadata; 0209 0210 /** UMD specific metadata. Opaque for kernel */ 0211 uint32_t umd_metadata[64]; 0212 }; 0213 0214 /** 0215 * Structure describing allocated buffer. Client may need 0216 * to query such information as part of 'sharing' buffers mechanism 0217 * 0218 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 0219 * amdgpu_bo_import(), amdgpu_bo_export() 0220 */ 0221 struct amdgpu_bo_info { 0222 /** Allocated memory size */ 0223 uint64_t alloc_size; 0224 0225 /** 0226 * It may be required to have some specific alignment requirements 0227 * for physical back-up storage. 0228 */ 0229 uint64_t phys_alignment; 0230 0231 /** Heap where to allocate memory. */ 0232 uint32_t preferred_heap; 0233 0234 /** Additional allocation flags. */ 0235 uint64_t alloc_flags; 0236 0237 /** Metadata associated with buffer if any. */ 0238 struct amdgpu_bo_metadata metadata; 0239 }; 0240 0241 /** 0242 * Structure with information about "imported" buffer 0243 * 0244 * \sa amdgpu_bo_import() 0245 * 0246 */ 0247 struct amdgpu_bo_import_result { 0248 /** Handle of memory/buffer to use */ 0249 amdgpu_bo_handle buf_handle; 0250 0251 /** Buffer size */ 0252 uint64_t alloc_size; 0253 }; 0254 0255 /** 0256 * 0257 * Structure to describe GDS partitioning information. 0258 * \note OA and GWS resources are asscoiated with GDS partition 0259 * 0260 * \sa amdgpu_gpu_resource_query_gds_info 0261 * 0262 */ 0263 struct amdgpu_gds_resource_info { 0264 uint32_t gds_gfx_partition_size; 0265 uint32_t compute_partition_size; 0266 uint32_t gds_total_size; 0267 uint32_t gws_per_gfx_partition; 0268 uint32_t gws_per_compute_partition; 0269 uint32_t oa_per_gfx_partition; 0270 uint32_t oa_per_compute_partition; 0271 }; 0272 0273 /** 0274 * Structure describing CS fence 0275 * 0276 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 0277 * 0278 */ 0279 struct amdgpu_cs_fence { 0280 0281 /** In which context IB was sent to execution */ 0282 amdgpu_context_handle context; 0283 0284 /** To which HW IP type the fence belongs */ 0285 uint32_t ip_type; 0286 0287 /** IP instance index if there are several IPs of the same type. */ 0288 uint32_t ip_instance; 0289 0290 /** Ring index of the HW IP */ 0291 uint32_t ring; 0292 0293 /** Specify fence for which we need to check submission status.*/ 0294 uint64_t fence; 0295 }; 0296 0297 /** 0298 * Structure describing IB 0299 * 0300 * \sa amdgpu_cs_request, amdgpu_cs_submit() 0301 * 0302 */ 0303 struct amdgpu_cs_ib_info { 0304 /** Special flags */ 0305 uint64_t flags; 0306 0307 /** Virtual MC address of the command buffer */ 0308 uint64_t ib_mc_address; 0309 0310 /** 0311 * Size of Command Buffer to be submitted. 0312 * - The size is in units of dwords (4 bytes). 0313 * - Could be 0 0314 */ 0315 uint32_t size; 0316 }; 0317 0318 /** 0319 * Structure describing fence information 0320 * 0321 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 0322 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 0323 */ 0324 struct amdgpu_cs_fence_info { 0325 /** buffer object for the fence */ 0326 amdgpu_bo_handle handle; 0327 0328 /** fence offset in the unit of sizeof(uint64_t) */ 0329 uint64_t offset; 0330 }; 0331 0332 /** 0333 * Structure describing submission request 0334 * 0335 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 0336 * 0337 * \sa amdgpu_cs_submit() 0338 */ 0339 struct amdgpu_cs_request { 0340 /** Specify flags with additional information */ 0341 uint64_t flags; 0342 0343 /** Specify HW IP block type to which to send the IB. */ 0344 unsigned ip_type; 0345 0346 /** IP instance index if there are several IPs of the same type. */ 0347 unsigned ip_instance; 0348 0349 /** 0350 * Specify ring index of the IP. We could have several rings 0351 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 0352 */ 0353 uint32_t ring; 0354 0355 /** 0356 * List handle with resources used by this request. 0357 */ 0358 amdgpu_bo_list_handle resources; 0359 0360 /** 0361 * Number of dependencies this Command submission needs to 0362 * wait for before starting execution. 0363 */ 0364 uint32_t number_of_dependencies; 0365 0366 /** 0367 * Array of dependencies which need to be met before 0368 * execution can start. 0369 */ 0370 struct amdgpu_cs_fence *dependencies; 0371 0372 /** Number of IBs to submit in the field ibs. */ 0373 uint32_t number_of_ibs; 0374 0375 /** 0376 * IBs to submit. Those IBs will be submit together as single entity 0377 */ 0378 struct amdgpu_cs_ib_info *ibs; 0379 0380 /** 0381 * The returned sequence number for the command submission 0382 */ 0383 uint64_t seq_no; 0384 0385 /** 0386 * The fence information 0387 */ 0388 struct amdgpu_cs_fence_info fence_info; 0389 }; 0390 0391 /** 0392 * Structure which provide information about GPU VM MC Address space 0393 * alignments requirements 0394 * 0395 * \sa amdgpu_query_buffer_size_alignment 0396 */ 0397 struct amdgpu_buffer_size_alignments { 0398 /** Size alignment requirement for allocation in 0399 * local memory */ 0400 uint64_t size_local; 0401 0402 /** 0403 * Size alignment requirement for allocation in remote memory 0404 */ 0405 uint64_t size_remote; 0406 }; 0407 0408 /** 0409 * Structure which provide information about heap 0410 * 0411 * \sa amdgpu_query_heap_info() 0412 * 0413 */ 0414 struct amdgpu_heap_info { 0415 /** Theoretical max. available memory in the given heap */ 0416 uint64_t heap_size; 0417 0418 /** 0419 * Number of bytes allocated in the heap. This includes all processes 0420 * and private allocations in the kernel. It changes when new buffers 0421 * are allocated, freed, and moved. It cannot be larger than 0422 * heap_size. 0423 */ 0424 uint64_t heap_usage; 0425 0426 /** 0427 * Theoretical possible max. size of buffer which 0428 * could be allocated in the given heap 0429 */ 0430 uint64_t max_allocation; 0431 }; 0432 0433 /** 0434 * Describe GPU h/w info needed for UMD correct initialization 0435 * 0436 * \sa amdgpu_query_gpu_info() 0437 */ 0438 struct amdgpu_gpu_info { 0439 /** Asic id */ 0440 uint32_t asic_id; 0441 /** Chip revision */ 0442 uint32_t chip_rev; 0443 /** Chip external revision */ 0444 uint32_t chip_external_rev; 0445 /** Family ID */ 0446 uint32_t family_id; 0447 /** Special flags */ 0448 uint64_t ids_flags; 0449 /** max engine clock*/ 0450 uint64_t max_engine_clk; 0451 /** max memory clock */ 0452 uint64_t max_memory_clk; 0453 /** number of shader engines */ 0454 uint32_t num_shader_engines; 0455 /** number of shader arrays per engine */ 0456 uint32_t num_shader_arrays_per_engine; 0457 /** Number of available good shader pipes */ 0458 uint32_t avail_quad_shader_pipes; 0459 /** Max. number of shader pipes.(including good and bad pipes */ 0460 uint32_t max_quad_shader_pipes; 0461 /** Number of parameter cache entries per shader quad pipe */ 0462 uint32_t cache_entries_per_quad_pipe; 0463 /** Number of available graphics context */ 0464 uint32_t num_hw_gfx_contexts; 0465 /** Number of render backend pipes */ 0466 uint32_t rb_pipes; 0467 /** Enabled render backend pipe mask */ 0468 uint32_t enabled_rb_pipes_mask; 0469 /** Frequency of GPU Counter */ 0470 uint32_t gpu_counter_freq; 0471 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 0472 uint32_t backend_disable[4]; 0473 /** Value of MC_ARB_RAMCFG register*/ 0474 uint32_t mc_arb_ramcfg; 0475 /** Value of GB_ADDR_CONFIG */ 0476 uint32_t gb_addr_cfg; 0477 /** Values of the GB_TILE_MODE0..31 registers */ 0478 uint32_t gb_tile_mode[32]; 0479 /** Values of GB_MACROTILE_MODE0..15 registers */ 0480 uint32_t gb_macro_tile_mode[16]; 0481 /** Value of PA_SC_RASTER_CONFIG register per SE */ 0482 uint32_t pa_sc_raster_cfg[4]; 0483 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 0484 uint32_t pa_sc_raster_cfg1[4]; 0485 /* CU info */ 0486 uint32_t cu_active_number; 0487 uint32_t cu_ao_mask; 0488 uint32_t cu_bitmap[4][4]; 0489 /* video memory type info*/ 0490 uint32_t vram_type; 0491 /* video memory bit width*/ 0492 uint32_t vram_bit_width; 0493 /** constant engine ram size*/ 0494 uint32_t ce_ram_size; 0495 /* vce harvesting instance */ 0496 uint32_t vce_harvest_config; 0497 /* PCI revision ID */ 0498 uint32_t pci_rev_id; 0499 }; 0500 0501 0502 /*--------------------------------------------------------------------------*/ 0503 /*------------------------- Functions --------------------------------------*/ 0504 /*--------------------------------------------------------------------------*/ 0505 0506 /* 0507 * Initialization / Cleanup 0508 * 0509 */ 0510 0511 /** 0512 * 0513 * \param fd - \c [in] File descriptor for AMD GPU device 0514 * received previously as the result of 0515 * e.g. drmOpen() call. 0516 * For legacy fd type, the DRI2/DRI3 0517 * authentication should be done before 0518 * calling this function. 0519 * \param major_version - \c [out] Major version of library. It is assumed 0520 * that adding new functionality will cause 0521 * increase in major version 0522 * \param minor_version - \c [out] Minor version of library 0523 * \param device_handle - \c [out] Pointer to opaque context which should 0524 * be passed as the first parameter on each 0525 * API call 0526 * 0527 * 0528 * \return 0 on success\n 0529 * <0 - Negative POSIX Error code 0530 * 0531 * 0532 * \sa amdgpu_device_deinitialize() 0533 */ 0534 int amdgpu_device_initialize(int fd, 0535 uint32_t *major_version, 0536 uint32_t *minor_version, 0537 amdgpu_device_handle *device_handle); 0538 0539 /** 0540 * Same as amdgpu_device_initialize() except when deduplicate_device 0541 * is false *and* fd points to a device that was already initialized. 0542 * In this case, amdgpu_device_initialize would return the same 0543 * amdgpu_device_handle while here amdgpu_device_initialize2 would 0544 * return a new handle. 0545 * amdgpu_device_initialize() should be preferred in most situations; 0546 * the only use-case where not-deduplicating devices make sense is 0547 * when one wants to have isolated device handles in the same process. 0548 */ 0549 int amdgpu_device_initialize2(int fd, bool deduplicate_device, 0550 uint32_t *major_version, 0551 uint32_t *minor_version, 0552 amdgpu_device_handle *device_handle); 0553 /** 0554 * 0555 * When access to such library does not needed any more the special 0556 * function must be call giving opportunity to clean up any 0557 * resources if needed. 0558 * 0559 * \param device_handle - \c [in] Context associated with file 0560 * descriptor for AMD GPU device 0561 * received previously as the 0562 * result e.g. of drmOpen() call. 0563 * 0564 * \return 0 on success\n 0565 * <0 - Negative POSIX Error code 0566 * 0567 * \sa amdgpu_device_initialize() 0568 * 0569 */ 0570 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 0571 0572 /** 0573 * 0574 * /param device_handle - \c [in] Device handle. 0575 * See #amdgpu_device_initialize() 0576 * 0577 * \return Returns the drm fd used for operations on this 0578 * device. This is still owned by the library and hence 0579 * should not be closed. Guaranteed to be valid until 0580 * #amdgpu_device_deinitialize gets called. 0581 * 0582 */ 0583 int amdgpu_device_get_fd(amdgpu_device_handle device_handle); 0584 0585 /* 0586 * Memory Management 0587 * 0588 */ 0589 0590 /** 0591 * Allocate memory to be used by UMD for GPU related operations 0592 * 0593 * \param dev - \c [in] Device handle. 0594 * See #amdgpu_device_initialize() 0595 * \param alloc_buffer - \c [in] Pointer to the structure describing an 0596 * allocation request 0597 * \param buf_handle - \c [out] Allocated buffer handle 0598 * 0599 * \return 0 on success\n 0600 * <0 - Negative POSIX Error code 0601 * 0602 * \sa amdgpu_bo_free() 0603 */ 0604 int amdgpu_bo_alloc(amdgpu_device_handle dev, 0605 struct amdgpu_bo_alloc_request *alloc_buffer, 0606 amdgpu_bo_handle *buf_handle); 0607 0608 /** 0609 * Associate opaque data with buffer to be queried by another UMD 0610 * 0611 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0612 * \param buf_handle - \c [in] Buffer handle 0613 * \param info - \c [in] Metadata to associated with buffer 0614 * 0615 * \return 0 on success\n 0616 * <0 - Negative POSIX Error code 0617 */ 0618 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 0619 struct amdgpu_bo_metadata *info); 0620 0621 /** 0622 * Query buffer information including metadata previusly associated with 0623 * buffer. 0624 * 0625 * \param dev - \c [in] Device handle. 0626 * See #amdgpu_device_initialize() 0627 * \param buf_handle - \c [in] Buffer handle 0628 * \param info - \c [out] Structure describing buffer 0629 * 0630 * \return 0 on success\n 0631 * <0 - Negative POSIX Error code 0632 * 0633 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 0634 */ 0635 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 0636 struct amdgpu_bo_info *info); 0637 0638 /** 0639 * Allow others to get access to buffer 0640 * 0641 * \param dev - \c [in] Device handle. 0642 * See #amdgpu_device_initialize() 0643 * \param buf_handle - \c [in] Buffer handle 0644 * \param type - \c [in] Type of handle requested 0645 * \param shared_handle - \c [out] Special "shared" handle 0646 * 0647 * \return 0 on success\n 0648 * <0 - Negative POSIX Error code 0649 * 0650 * \sa amdgpu_bo_import() 0651 * 0652 */ 0653 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 0654 enum amdgpu_bo_handle_type type, 0655 uint32_t *shared_handle); 0656 0657 /** 0658 * Request access to "shared" buffer 0659 * 0660 * \param dev - \c [in] Device handle. 0661 * See #amdgpu_device_initialize() 0662 * \param type - \c [in] Type of handle requested 0663 * \param shared_handle - \c [in] Shared handle received as result "import" 0664 * operation 0665 * \param output - \c [out] Pointer to structure with information 0666 * about imported buffer 0667 * 0668 * \return 0 on success\n 0669 * <0 - Negative POSIX Error code 0670 * 0671 * \note Buffer must be "imported" only using new "fd" (different from 0672 * one used by "exporter"). 0673 * 0674 * \sa amdgpu_bo_export() 0675 * 0676 */ 0677 int amdgpu_bo_import(amdgpu_device_handle dev, 0678 enum amdgpu_bo_handle_type type, 0679 uint32_t shared_handle, 0680 struct amdgpu_bo_import_result *output); 0681 0682 /** 0683 * Request GPU access to user allocated memory e.g. via "malloc" 0684 * 0685 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 0686 * \param cpu - [in] CPU address of user allocated memory which we 0687 * want to map to GPU address space (make GPU accessible) 0688 * (This address must be correctly aligned). 0689 * \param size - [in] Size of allocation (must be correctly aligned) 0690 * \param buf_handle - [out] Buffer handle for the userptr memory 0691 * resource on submission and be used in other operations. 0692 * 0693 * 0694 * \return 0 on success\n 0695 * <0 - Negative POSIX Error code 0696 * 0697 * \note 0698 * This call doesn't guarantee that such memory will be persistently 0699 * "locked" / make non-pageable. The purpose of this call is to provide 0700 * opportunity for GPU get access to this resource during submission. 0701 * 0702 * The maximum amount of memory which could be mapped in this call depends 0703 * if overcommit is disabled or not. If overcommit is disabled than the max. 0704 * amount of memory to be pinned will be limited by left "free" size in total 0705 * amount of memory which could be locked simultaneously ("GART" size). 0706 * 0707 * Supported (theoretical) max. size of mapping is restricted only by 0708 * "GART" size. 0709 * 0710 * It is responsibility of caller to correctly specify access rights 0711 * on VA assignment. 0712 */ 0713 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 0714 void *cpu, uint64_t size, 0715 amdgpu_bo_handle *buf_handle); 0716 0717 /** 0718 * Validate if the user memory comes from BO 0719 * 0720 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 0721 * \param cpu - [in] CPU address of user allocated memory which we 0722 * want to map to GPU address space (make GPU accessible) 0723 * (This address must be correctly aligned). 0724 * \param size - [in] Size of allocation (must be correctly aligned) 0725 * \param buf_handle - [out] Buffer handle for the userptr memory 0726 * if the user memory is not from BO, the buf_handle will be NULL. 0727 * \param offset_in_bo - [out] offset in this BO for this user memory 0728 * 0729 * 0730 * \return 0 on success\n 0731 * <0 - Negative POSIX Error code 0732 * 0733 */ 0734 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 0735 void *cpu, 0736 uint64_t size, 0737 amdgpu_bo_handle *buf_handle, 0738 uint64_t *offset_in_bo); 0739 0740 /** 0741 * Free previously allocated memory 0742 * 0743 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0744 * \param buf_handle - \c [in] Buffer handle to free 0745 * 0746 * \return 0 on success\n 0747 * <0 - Negative POSIX Error code 0748 * 0749 * \note In the case of memory shared between different applications all 0750 * resources will be “physically” freed only all such applications 0751 * will be terminated 0752 * \note If is UMD responsibility to ‘free’ buffer only when there is no 0753 * more GPU access 0754 * 0755 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 0756 * 0757 */ 0758 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 0759 0760 /** 0761 * Increase the reference count of a buffer object 0762 * 0763 * \param bo - \c [in] Buffer object handle to increase the reference count 0764 * 0765 * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 0766 * 0767 */ 0768 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 0769 0770 /** 0771 * Request CPU access to GPU accessible memory 0772 * 0773 * \param buf_handle - \c [in] Buffer handle 0774 * \param cpu - \c [out] CPU address to be used for access 0775 * 0776 * \return 0 on success\n 0777 * <0 - Negative POSIX Error code 0778 * 0779 * \sa amdgpu_bo_cpu_unmap() 0780 * 0781 */ 0782 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 0783 0784 /** 0785 * Release CPU access to GPU memory 0786 * 0787 * \param buf_handle - \c [in] Buffer handle 0788 * 0789 * \return 0 on success\n 0790 * <0 - Negative POSIX Error code 0791 * 0792 * \sa amdgpu_bo_cpu_map() 0793 * 0794 */ 0795 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 0796 0797 /** 0798 * Wait until a buffer is not used by the device. 0799 * 0800 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0801 * \param buf_handle - \c [in] Buffer handle. 0802 * \param timeout_ns - Timeout in nanoseconds. 0803 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 0804 * and no GPU access is scheduled. 0805 * 1 GPU access is in fly or scheduled 0806 * 0807 * \return 0 - on success 0808 * <0 - Negative POSIX Error code 0809 */ 0810 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 0811 uint64_t timeout_ns, 0812 bool *buffer_busy); 0813 0814 /** 0815 * Creates a BO list handle for command submission. 0816 * 0817 * \param dev - \c [in] Device handle. 0818 * See #amdgpu_device_initialize() 0819 * \param number_of_buffers - \c [in] Number of BOs in the list 0820 * \param buffers - \c [in] List of BO handles 0821 * \param result - \c [out] Created BO list handle 0822 * 0823 * \return 0 on success\n 0824 * <0 - Negative POSIX Error code 0825 * 0826 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() 0827 */ 0828 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, 0829 uint32_t number_of_buffers, 0830 struct drm_amdgpu_bo_list_entry *buffers, 0831 uint32_t *result); 0832 0833 /** 0834 * Destroys a BO list handle. 0835 * 0836 * \param bo_list - \c [in] BO list handle. 0837 * 0838 * \return 0 on success\n 0839 * <0 - Negative POSIX Error code 0840 * 0841 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() 0842 */ 0843 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); 0844 0845 /** 0846 * Creates a BO list handle for command submission. 0847 * 0848 * \param dev - \c [in] Device handle. 0849 * See #amdgpu_device_initialize() 0850 * \param number_of_resources - \c [in] Number of BOs in the list 0851 * \param resources - \c [in] List of BO handles 0852 * \param resource_prios - \c [in] Optional priority for each handle 0853 * \param result - \c [out] Created BO list handle 0854 * 0855 * \return 0 on success\n 0856 * <0 - Negative POSIX Error code 0857 * 0858 * \sa amdgpu_bo_list_destroy() 0859 */ 0860 int amdgpu_bo_list_create(amdgpu_device_handle dev, 0861 uint32_t number_of_resources, 0862 amdgpu_bo_handle *resources, 0863 uint8_t *resource_prios, 0864 amdgpu_bo_list_handle *result); 0865 0866 /** 0867 * Destroys a BO list handle. 0868 * 0869 * \param handle - \c [in] BO list handle. 0870 * 0871 * \return 0 on success\n 0872 * <0 - Negative POSIX Error code 0873 * 0874 * \sa amdgpu_bo_list_create() 0875 */ 0876 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 0877 0878 /** 0879 * Update resources for existing BO list 0880 * 0881 * \param handle - \c [in] BO list handle 0882 * \param number_of_resources - \c [in] Number of BOs in the list 0883 * \param resources - \c [in] List of BO handles 0884 * \param resource_prios - \c [in] Optional priority for each handle 0885 * 0886 * \return 0 on success\n 0887 * <0 - Negative POSIX Error code 0888 * 0889 * \sa amdgpu_bo_list_update() 0890 */ 0891 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 0892 uint32_t number_of_resources, 0893 amdgpu_bo_handle *resources, 0894 uint8_t *resource_prios); 0895 0896 /* 0897 * GPU Execution context 0898 * 0899 */ 0900 0901 /** 0902 * Create GPU execution Context 0903 * 0904 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 0905 * necessary to have information/identify rendering/compute contexts. 0906 * It also may be needed to associate some specific requirements with such 0907 * contexts. Kernel driver will guarantee that submission from the same 0908 * context will always be executed in order (first come, first serve). 0909 * 0910 * 0911 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 0912 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 0913 * \param context - \c [out] GPU Context handle 0914 * 0915 * \return 0 on success\n 0916 * <0 - Negative POSIX Error code 0917 * 0918 * \sa amdgpu_cs_ctx_free() 0919 * 0920 */ 0921 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 0922 uint32_t priority, 0923 amdgpu_context_handle *context); 0924 /** 0925 * Create GPU execution Context 0926 * 0927 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 0928 * is missing the priority parameter. 0929 * 0930 * \sa amdgpu_cs_ctx_create2() 0931 * 0932 */ 0933 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 0934 amdgpu_context_handle *context); 0935 0936 /** 0937 * 0938 * Destroy GPU execution context when not needed any more 0939 * 0940 * \param context - \c [in] GPU Context handle 0941 * 0942 * \return 0 on success\n 0943 * <0 - Negative POSIX Error code 0944 * 0945 * \sa amdgpu_cs_ctx_create() 0946 * 0947 */ 0948 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 0949 0950 /** 0951 * Override the submission priority for the given context using a master fd. 0952 * 0953 * \param dev - \c [in] device handle 0954 * \param context - \c [in] context handle for context id 0955 * \param master_fd - \c [in] The master fd to authorize the override. 0956 * \param priority - \c [in] The priority to assign to the context. 0957 * 0958 * \return 0 on success or a a negative Posix error code on failure. 0959 */ 0960 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, 0961 amdgpu_context_handle context, 0962 int master_fd, 0963 unsigned priority); 0964 0965 /** 0966 * Set or query the stable power state for GPU profiling. 0967 * 0968 * \param dev - \c [in] device handle 0969 * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE 0970 * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_* 0971 * \param out_flags - \c [out] output current stable pstate 0972 * 0973 * \return 0 on success otherwise POSIX Error code. 0974 */ 0975 int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, 0976 uint32_t op, 0977 uint32_t flags, 0978 uint32_t *out_flags); 0979 0980 /** 0981 * Query reset state for the specific GPU Context 0982 * 0983 * \param context - \c [in] GPU Context handle 0984 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 0985 * \param hangs - \c [out] Number of hangs caused by the context. 0986 * 0987 * \return 0 on success\n 0988 * <0 - Negative POSIX Error code 0989 * 0990 * \sa amdgpu_cs_ctx_create() 0991 * 0992 */ 0993 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 0994 uint32_t *state, uint32_t *hangs); 0995 0996 /** 0997 * Query reset state for the specific GPU Context. 0998 * 0999 * \param context - \c [in] GPU Context handle 1000 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_* 1001 * 1002 * \return 0 on success\n 1003 * <0 - Negative POSIX Error code 1004 * 1005 * \sa amdgpu_cs_ctx_create() 1006 * 1007 */ 1008 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context, 1009 uint64_t *flags); 1010 1011 /* 1012 * Command Buffers Management 1013 * 1014 */ 1015 1016 /** 1017 * Send request to submit command buffers to hardware. 1018 * 1019 * Kernel driver could use GPU Scheduler to make decision when physically 1020 * sent this request to the hardware. Accordingly this request could be put 1021 * in queue and sent for execution later. The only guarantee is that request 1022 * from the same GPU context to the same ip:ip_instance:ring will be executed in 1023 * order. 1024 * 1025 * The caller can specify the user fence buffer/location with the fence_info in the 1026 * cs_request.The sequence number is returned via the 'seq_no' parameter 1027 * in ibs_request structure. 1028 * 1029 * 1030 * \param dev - \c [in] Device handle. 1031 * See #amdgpu_device_initialize() 1032 * \param context - \c [in] GPU Context 1033 * \param flags - \c [in] Global submission flags 1034 * \param ibs_request - \c [in/out] Pointer to submission requests. 1035 * We could submit to the several 1036 * engines/rings simulteniously as 1037 * 'atomic' operation 1038 * \param number_of_requests - \c [in] Number of submission requests 1039 * 1040 * \return 0 on success\n 1041 * <0 - Negative POSIX Error code 1042 * 1043 * \note It is required to pass correct resource list with buffer handles 1044 * which will be accessible by command buffers from submission 1045 * This will allow kernel driver to correctly implement "paging". 1046 * Failure to do so will have unpredictable results. 1047 * 1048 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 1049 * amdgpu_cs_query_fence_status() 1050 * 1051 */ 1052 int amdgpu_cs_submit(amdgpu_context_handle context, 1053 uint64_t flags, 1054 struct amdgpu_cs_request *ibs_request, 1055 uint32_t number_of_requests); 1056 1057 /** 1058 * Query status of Command Buffer Submission 1059 * 1060 * \param fence - \c [in] Structure describing fence to query 1061 * \param timeout_ns - \c [in] Timeout value to wait 1062 * \param flags - \c [in] Flags for the query 1063 * \param expired - \c [out] If fence expired or not.\n 1064 * 0 – if fence is not expired\n 1065 * !0 - otherwise 1066 * 1067 * \return 0 on success\n 1068 * <0 - Negative POSIX Error code 1069 * 1070 * \note If UMD wants only to check operation status and returned immediately 1071 * then timeout value as 0 must be passed. In this case success will be 1072 * returned in the case if submission was completed or timeout error 1073 * code. 1074 * 1075 * \sa amdgpu_cs_submit() 1076 */ 1077 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 1078 uint64_t timeout_ns, 1079 uint64_t flags, 1080 uint32_t *expired); 1081 1082 /** 1083 * Wait for multiple fences 1084 * 1085 * \param fences - \c [in] The fence array to wait 1086 * \param fence_count - \c [in] The fence count 1087 * \param wait_all - \c [in] If true, wait all fences to be signaled, 1088 * otherwise, wait at least one fence 1089 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 1090 * \param status - \c [out] '1' for signaled, '0' for timeout 1091 * \param first - \c [out] the index of the first signaled fence from @fences 1092 * 1093 * \return 0 on success 1094 * <0 - Negative POSIX Error code 1095 * 1096 * \note Currently it supports only one amdgpu_device. All fences come from 1097 * the same amdgpu_device with the same fd. 1098 */ 1099 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 1100 uint32_t fence_count, 1101 bool wait_all, 1102 uint64_t timeout_ns, 1103 uint32_t *status, uint32_t *first); 1104 1105 /* 1106 * Query / Info API 1107 * 1108 */ 1109 1110 /** 1111 * Query allocation size alignments 1112 * 1113 * UMD should query information about GPU VM MC size alignments requirements 1114 * to be able correctly choose required allocation size and implement 1115 * internal optimization if needed. 1116 * 1117 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1118 * \param info - \c [out] Pointer to structure to get size alignment 1119 * requirements 1120 * 1121 * \return 0 on success\n 1122 * <0 - Negative POSIX Error code 1123 * 1124 */ 1125 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 1126 struct amdgpu_buffer_size_alignments 1127 *info); 1128 1129 /** 1130 * Query firmware versions 1131 * 1132 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1133 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 1134 * \param ip_instance - \c [in] Index of the IP block of the same type. 1135 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 1136 * \param version - \c [out] Pointer to to the "version" return value 1137 * \param feature - \c [out] Pointer to to the "feature" return value 1138 * 1139 * \return 0 on success\n 1140 * <0 - Negative POSIX Error code 1141 * 1142 */ 1143 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 1144 unsigned ip_instance, unsigned index, 1145 uint32_t *version, uint32_t *feature); 1146 1147 /** 1148 * Query the number of HW IP instances of a certain type. 1149 * 1150 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1151 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1152 * \param count - \c [out] Pointer to structure to get information 1153 * 1154 * \return 0 on success\n 1155 * <0 - Negative POSIX Error code 1156 */ 1157 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1158 uint32_t *count); 1159 1160 /** 1161 * Query engine information 1162 * 1163 * This query allows UMD to query information different engines and their 1164 * capabilities. 1165 * 1166 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1167 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1168 * \param ip_instance - \c [in] Index of the IP block of the same type. 1169 * \param info - \c [out] Pointer to structure to get information 1170 * 1171 * \return 0 on success\n 1172 * <0 - Negative POSIX Error code 1173 */ 1174 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1175 unsigned ip_instance, 1176 struct drm_amdgpu_info_hw_ip *info); 1177 1178 /** 1179 * Query FW area related information. 1180 * 1181 * The return size is query-specific and depends on the "type" parameter. 1182 * No more than "size" bytes is returned. 1183 * 1184 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1185 * \param type - \c [in] AMDGPU_HW_IP_* 1186 * \param ip_instance - \c [in] HW IP index. 1187 * \param info - \c [out] The pointer to return value 1188 * 1189 * \return 0 on success\n 1190 * <0 - Negative POSIX error code 1191 * 1192 */ 1193 int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev, 1194 unsigned type, 1195 unsigned ip_instance, 1196 struct drm_amdgpu_info_uq_fw_areas *info); 1197 1198 /** 1199 * Query heap information 1200 * 1201 * This query allows UMD to query potentially available memory resources and 1202 * adjust their logic if necessary. 1203 * 1204 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1205 * \param heap - \c [in] Heap type 1206 * \param info - \c [in] Pointer to structure to get needed information 1207 * 1208 * \return 0 on success\n 1209 * <0 - Negative POSIX Error code 1210 * 1211 */ 1212 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1213 uint32_t flags, struct amdgpu_heap_info *info); 1214 1215 /** 1216 * Get the CRTC ID from the mode object ID 1217 * 1218 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1219 * \param id - \c [in] Mode object ID 1220 * \param result - \c [in] Pointer to the CRTC ID 1221 * 1222 * \return 0 on success\n 1223 * <0 - Negative POSIX Error code 1224 * 1225 */ 1226 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1227 int32_t *result); 1228 1229 /** 1230 * Query GPU H/w Info 1231 * 1232 * Query hardware specific information 1233 * 1234 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1235 * \param heap - \c [in] Heap type 1236 * \param info - \c [in] Pointer to structure to get needed information 1237 * 1238 * \return 0 on success\n 1239 * <0 - Negative POSIX Error code 1240 * 1241 */ 1242 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1243 struct amdgpu_gpu_info *info); 1244 1245 /** 1246 * Query hardware or driver information. 1247 * 1248 * The return size is query-specific and depends on the "info_id" parameter. 1249 * No more than "size" bytes is returned. 1250 * 1251 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1252 * \param info_id - \c [in] AMDGPU_INFO_* 1253 * \param size - \c [in] Size of the returned value. 1254 * \param value - \c [out] Pointer to the return value. 1255 * 1256 * \return 0 on success\n 1257 * <0 - Negative POSIX error code 1258 * 1259 */ 1260 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1261 unsigned size, void *value); 1262 1263 /** 1264 * Query hardware or driver information. 1265 * 1266 * The return size is query-specific and depends on the "info_id" parameter. 1267 * No more than "size" bytes is returned. 1268 * 1269 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1270 * \param info - \c [in] amdgpu_sw_info_* 1271 * \param value - \c [out] Pointer to the return value. 1272 * 1273 * \return 0 on success\n 1274 * <0 - Negative POSIX error code 1275 * 1276 */ 1277 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1278 void *value); 1279 1280 /** 1281 * Query information about GDS 1282 * 1283 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1284 * \param gds_info - \c [out] Pointer to structure to get GDS information 1285 * 1286 * \return 0 on success\n 1287 * <0 - Negative POSIX Error code 1288 * 1289 */ 1290 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1291 struct amdgpu_gds_resource_info *gds_info); 1292 1293 /** 1294 * Query information about sensor. 1295 * 1296 * The return size is query-specific and depends on the "sensor_type" 1297 * parameter. No more than "size" bytes is returned. 1298 * 1299 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1300 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1301 * \param size - \c [in] Size of the returned value. 1302 * \param value - \c [out] Pointer to the return value. 1303 * 1304 * \return 0 on success\n 1305 * <0 - Negative POSIX Error code 1306 * 1307 */ 1308 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1309 unsigned size, void *value); 1310 1311 /** 1312 * Query information about video capabilities 1313 * 1314 * The return sizeof(struct drm_amdgpu_info_video_caps) 1315 * 1316 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1317 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) 1318 * \param size - \c [in] Size of the returned value. 1319 * \param value - \c [out] Pointer to the return value. 1320 * 1321 * \return 0 on success\n 1322 * <0 - Negative POSIX Error code 1323 * 1324 */ 1325 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 1326 unsigned size, void *value); 1327 1328 /** 1329 * Query information about VM faults 1330 * 1331 * The return sizeof(struct drm_amdgpu_info_gpuvm_fault) 1332 * 1333 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1334 * \param size - \c [in] Size of the returned value. 1335 * \param value - \c [out] Pointer to the return value. 1336 * 1337 * \return 0 on success\n 1338 * <0 - Negative POSIX Error code 1339 * 1340 */ 1341 int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size, 1342 void *value); 1343 1344 /** 1345 * Read a set of consecutive memory-mapped registers. 1346 * Not all registers are allowed to be read by userspace. 1347 * 1348 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1349 * \param dword_offset - \c [in] Register offset in dwords 1350 * \param count - \c [in] The number of registers to read starting 1351 * from the offset 1352 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1353 * uses. Set it to 0xffffffff if unsure. 1354 * \param flags - \c [in] Flags with additional information. 1355 * \param values - \c [out] The pointer to return values. 1356 * 1357 * \return 0 on success\n 1358 * <0 - Negative POSIX error code 1359 * 1360 */ 1361 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1362 unsigned count, uint32_t instance, uint32_t flags, 1363 uint32_t *values); 1364 1365 /** 1366 * Flag to request VA address range in the 32bit address space 1367 */ 1368 #define AMDGPU_VA_RANGE_32_BIT 0x1 1369 #define AMDGPU_VA_RANGE_HIGH 0x2 1370 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4 1371 1372 /** 1373 * Allocate virtual address range 1374 * 1375 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1376 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1377 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1378 * It is client responsibility to correctly aligned size based on the future 1379 * usage of allocated range. 1380 * \param va_base_alignment - \c [in] Overwrite base address alignment 1381 * requirement for GPU VM MC virtual 1382 * address assignment. Must be multiple of size alignments received as 1383 * 'amdgpu_buffer_size_alignments'. 1384 * If 0 use the default one. 1385 * \param va_base_required - \c [in] Specified required va base address. 1386 * If 0 then library choose available one. 1387 * If !0 value will be passed and those value already "in use" then 1388 * corresponding error status will be returned. 1389 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1390 * by client. 1391 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1392 * \param flags - \c [in] flags for special VA range 1393 * 1394 * \return 0 on success\n 1395 * >0 - AMD specific error code\n 1396 * <0 - Negative POSIX Error code 1397 * 1398 * \notes \n 1399 * It is client responsibility to correctly handle VA assignments and usage. 1400 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1401 * detect wrong va assignment. 1402 * 1403 * It is client responsibility to correctly handle multi-GPU cases and to pass 1404 * the corresponding arrays of all devices handles where corresponding VA will 1405 * be used. 1406 * 1407 */ 1408 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1409 enum amdgpu_gpu_va_range va_range_type, 1410 uint64_t size, 1411 uint64_t va_base_alignment, 1412 uint64_t va_base_required, 1413 uint64_t *va_base_allocated, 1414 amdgpu_va_handle *va_range_handle, 1415 uint64_t flags); 1416 1417 /** 1418 * Free previously allocated virtual address range 1419 * 1420 * 1421 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1422 * 1423 * \return 0 on success\n 1424 * >0 - AMD specific error code\n 1425 * <0 - Negative POSIX Error code 1426 * 1427 */ 1428 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1429 1430 /** 1431 * Return the starting address of the allocated virtual address range. 1432 */ 1433 uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle); 1434 1435 /** 1436 * Query virtual address range 1437 * 1438 * UMD can query GPU VM range supported by each device 1439 * to initialize its own VAM accordingly. 1440 * 1441 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1442 * \param type - \c [in] Type of virtual address range 1443 * \param offset - \c [out] Start offset of virtual address range 1444 * \param size - \c [out] Size of virtual address range 1445 * 1446 * \return 0 on success\n 1447 * <0 - Negative POSIX Error code 1448 * 1449 */ 1450 1451 int amdgpu_va_range_query(amdgpu_device_handle dev, 1452 enum amdgpu_gpu_va_range type, 1453 uint64_t *start, 1454 uint64_t *end); 1455 1456 /** 1457 * Allocate a amdgpu_va_manager object. 1458 * The returned object has be initialized with the amdgpu_va_manager_init 1459 * before use. 1460 * On release, amdgpu_va_manager_deinit needs to be called, then the memory 1461 * can be released using free(). 1462 */ 1463 amdgpu_va_manager_handle amdgpu_va_manager_alloc(void); 1464 1465 void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr, 1466 uint64_t low_va_offset, uint64_t low_va_max, 1467 uint64_t high_va_offset, uint64_t high_va_max, 1468 uint32_t virtual_address_alignment); 1469 1470 void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr); 1471 1472 /** 1473 * Similar to #amdgpu_va_range_alloc() but allocates VA 1474 * directly from an amdgpu_va_manager_handle instead of using 1475 * the manager from an amdgpu_device. 1476 */ 1477 1478 int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr, 1479 enum amdgpu_gpu_va_range va_range_type, 1480 uint64_t size, 1481 uint64_t va_base_alignment, 1482 uint64_t va_base_required, 1483 uint64_t *va_base_allocated, 1484 amdgpu_va_handle *va_range_handle, 1485 uint64_t flags); 1486 1487 /** 1488 * VA mapping/unmapping for the buffer object 1489 * 1490 * \param bo - \c [in] BO handle 1491 * \param offset - \c [in] Start offset to map 1492 * \param size - \c [in] Size to map 1493 * \param addr - \c [in] Start virtual address. 1494 * \param flags - \c [in] Supported flags for mapping/unmapping 1495 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1496 * 1497 * \return 0 on success\n 1498 * <0 - Negative POSIX Error code 1499 * 1500 */ 1501 1502 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1503 uint64_t offset, 1504 uint64_t size, 1505 uint64_t addr, 1506 uint64_t flags, 1507 uint32_t ops); 1508 1509 /** 1510 * VA mapping/unmapping for a buffer object or PRT region. 1511 * 1512 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1513 * parameters are treated "raw", i.e. size is not automatically aligned, and 1514 * all flags must be specified explicitly. 1515 * 1516 * \param dev - \c [in] device handle 1517 * \param bo - \c [in] BO handle (may be NULL) 1518 * \param offset - \c [in] Start offset to map 1519 * \param size - \c [in] Size to map 1520 * \param addr - \c [in] Start virtual address. 1521 * \param flags - \c [in] Supported flags for mapping/unmapping 1522 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1523 * 1524 * \return 0 on success\n 1525 * <0 - Negative POSIX Error code 1526 * 1527 */ 1528 1529 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1530 amdgpu_bo_handle bo, 1531 uint64_t offset, 1532 uint64_t size, 1533 uint64_t addr, 1534 uint64_t flags, 1535 uint32_t ops); 1536 1537 /** 1538 * VA mapping/unmapping of buffer object for usermode queue. 1539 * 1540 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1541 * parameters are treated "raw2", i.e. size is not automatically aligned, and 1542 * all flags must be specified explicitly. 1543 * 1544 * \param dev - \c [in] device handle 1545 * \param bo - \c [in] BO handle (may be NULL) 1546 * \param offset - \c [in] Start offset to map 1547 * \param size - \c [in] Size to map 1548 * \param addr - \c [in] Start virtual address. 1549 * \param flags - \c [in] Supported flags for mapping/unmapping 1550 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1551 * \param vm_timeline_syncobj_out - \c [out] syncobj handle for PT update fence 1552 * \param vm_timeline_point - \c [in] input timeline point 1553 * \param input_fence_syncobj_handles - \c [in] Array of syncobj handles for bo unmap, 1554 * clear and replace 1555 * \param num_syncobj_handles - \c [in] Number of syncobj handles 1556 * 1557 * \return 0 on success\n 1558 * <0 - Negative POSIX Error code 1559 * 1560 */ 1561 int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev, 1562 amdgpu_bo_handle bo, 1563 uint64_t offset, 1564 uint64_t size, 1565 uint64_t addr, 1566 uint64_t flags, 1567 uint32_t ops, 1568 uint32_t vm_timeline_syncobj_out, 1569 uint64_t vm_timeline_point, 1570 uint64_t input_fence_syncobj_array_in, 1571 uint32_t num_syncobj_handles_in); 1572 1573 /** 1574 * create semaphore 1575 * 1576 * \param sem - \c [out] semaphore handle 1577 * 1578 * \return 0 on success\n 1579 * <0 - Negative POSIX Error code 1580 * 1581 */ 1582 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1583 1584 /** 1585 * signal semaphore 1586 * 1587 * \param context - \c [in] GPU Context 1588 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1589 * \param ip_instance - \c [in] Index of the IP block of the same type 1590 * \param ring - \c [in] Specify ring index of the IP 1591 * \param sem - \c [in] semaphore handle 1592 * 1593 * \return 0 on success\n 1594 * <0 - Negative POSIX Error code 1595 * 1596 */ 1597 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1598 uint32_t ip_type, 1599 uint32_t ip_instance, 1600 uint32_t ring, 1601 amdgpu_semaphore_handle sem); 1602 1603 /** 1604 * wait semaphore 1605 * 1606 * \param context - \c [in] GPU Context 1607 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1608 * \param ip_instance - \c [in] Index of the IP block of the same type 1609 * \param ring - \c [in] Specify ring index of the IP 1610 * \param sem - \c [in] semaphore handle 1611 * 1612 * \return 0 on success\n 1613 * <0 - Negative POSIX Error code 1614 * 1615 */ 1616 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1617 uint32_t ip_type, 1618 uint32_t ip_instance, 1619 uint32_t ring, 1620 amdgpu_semaphore_handle sem); 1621 1622 /** 1623 * destroy semaphore 1624 * 1625 * \param sem - \c [in] semaphore handle 1626 * 1627 * \return 0 on success\n 1628 * <0 - Negative POSIX Error code 1629 * 1630 */ 1631 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1632 1633 /** 1634 * Get the ASIC marketing name 1635 * 1636 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1637 * 1638 * \return the constant string of the marketing name 1639 * "NULL" means the ASIC is not found 1640 */ 1641 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1642 1643 /** 1644 * Create kernel sync object 1645 * 1646 * \param dev - \c [in] device handle 1647 * \param flags - \c [in] flags that affect creation 1648 * \param syncobj - \c [out] sync object handle 1649 * 1650 * \return 0 on success\n 1651 * <0 - Negative POSIX Error code 1652 * 1653 */ 1654 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1655 uint32_t flags, 1656 uint32_t *syncobj); 1657 1658 /** 1659 * Create kernel sync object 1660 * 1661 * \param dev - \c [in] device handle 1662 * \param syncobj - \c [out] sync object handle 1663 * 1664 * \return 0 on success\n 1665 * <0 - Negative POSIX Error code 1666 * 1667 */ 1668 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1669 uint32_t *syncobj); 1670 /** 1671 * Destroy kernel sync object 1672 * 1673 * \param dev - \c [in] device handle 1674 * \param syncobj - \c [in] sync object handle 1675 * 1676 * \return 0 on success\n 1677 * <0 - Negative POSIX Error code 1678 * 1679 */ 1680 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1681 uint32_t syncobj); 1682 1683 /** 1684 * Reset kernel sync objects to unsignalled state. 1685 * 1686 * \param dev - \c [in] device handle 1687 * \param syncobjs - \c [in] array of sync object handles 1688 * \param syncobj_count - \c [in] number of handles in syncobjs 1689 * 1690 * \return 0 on success\n 1691 * <0 - Negative POSIX Error code 1692 * 1693 */ 1694 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1695 const uint32_t *syncobjs, uint32_t syncobj_count); 1696 1697 /** 1698 * Signal kernel sync objects. 1699 * 1700 * \param dev - \c [in] device handle 1701 * \param syncobjs - \c [in] array of sync object handles 1702 * \param syncobj_count - \c [in] number of handles in syncobjs 1703 * 1704 * \return 0 on success\n 1705 * <0 - Negative POSIX Error code 1706 * 1707 */ 1708 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1709 const uint32_t *syncobjs, uint32_t syncobj_count); 1710 1711 /** 1712 * Signal kernel timeline sync objects. 1713 * 1714 * \param dev - \c [in] device handle 1715 * \param syncobjs - \c [in] array of sync object handles 1716 * \param points - \c [in] array of timeline points 1717 * \param syncobj_count - \c [in] number of handles in syncobjs 1718 * 1719 * \return 0 on success\n 1720 * <0 - Negative POSIX Error code 1721 * 1722 */ 1723 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev, 1724 const uint32_t *syncobjs, 1725 uint64_t *points, 1726 uint32_t syncobj_count); 1727 1728 /** 1729 * Wait for one or all sync objects to signal. 1730 * 1731 * \param dev - \c [in] self-explanatory 1732 * \param handles - \c [in] array of sync object handles 1733 * \param num_handles - \c [in] self-explanatory 1734 * \param timeout_nsec - \c [in] self-explanatory 1735 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1736 * \param first_signaled - \c [in] self-explanatory 1737 * 1738 * \return 0 on success\n 1739 * -ETIME - Timeout 1740 * <0 - Negative POSIX Error code 1741 * 1742 */ 1743 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1744 uint32_t *handles, unsigned num_handles, 1745 int64_t timeout_nsec, unsigned flags, 1746 uint32_t *first_signaled); 1747 1748 /** 1749 * Wait for one or all sync objects on their points to signal. 1750 * 1751 * \param dev - \c [in] self-explanatory 1752 * \param handles - \c [in] array of sync object handles 1753 * \param points - \c [in] array of sync points to wait 1754 * \param num_handles - \c [in] self-explanatory 1755 * \param timeout_nsec - \c [in] self-explanatory 1756 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1757 * \param first_signaled - \c [in] self-explanatory 1758 * 1759 * \return 0 on success\n 1760 * -ETIME - Timeout 1761 * <0 - Negative POSIX Error code 1762 * 1763 */ 1764 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev, 1765 uint32_t *handles, uint64_t *points, 1766 unsigned num_handles, 1767 int64_t timeout_nsec, unsigned flags, 1768 uint32_t *first_signaled); 1769 /** 1770 * Query sync objects payloads. 1771 * 1772 * \param dev - \c [in] self-explanatory 1773 * \param handles - \c [in] array of sync object handles 1774 * \param points - \c [out] array of sync points returned, which presents 1775 * syncobj payload. 1776 * \param num_handles - \c [in] self-explanatory 1777 * 1778 * \return 0 on success\n 1779 * -ETIME - Timeout 1780 * <0 - Negative POSIX Error code 1781 * 1782 */ 1783 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev, 1784 uint32_t *handles, uint64_t *points, 1785 unsigned num_handles); 1786 /** 1787 * Query sync objects last signaled or submitted point. 1788 * 1789 * \param dev - \c [in] self-explanatory 1790 * \param handles - \c [in] array of sync object handles 1791 * \param points - \c [out] array of sync points returned, which presents 1792 * syncobj payload. 1793 * \param num_handles - \c [in] self-explanatory 1794 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_* 1795 * 1796 * \return 0 on success\n 1797 * -ETIME - Timeout 1798 * <0 - Negative POSIX Error code 1799 * 1800 */ 1801 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev, 1802 uint32_t *handles, uint64_t *points, 1803 unsigned num_handles, uint32_t flags); 1804 1805 /** 1806 * Export kernel sync object to shareable fd. 1807 * 1808 * \param dev - \c [in] device handle 1809 * \param syncobj - \c [in] sync object handle 1810 * \param shared_fd - \c [out] shared file descriptor. 1811 * 1812 * \return 0 on success\n 1813 * <0 - Negative POSIX Error code 1814 * 1815 */ 1816 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1817 uint32_t syncobj, 1818 int *shared_fd); 1819 /** 1820 * Import kernel sync object from shareable fd. 1821 * 1822 * \param dev - \c [in] device handle 1823 * \param shared_fd - \c [in] shared file descriptor. 1824 * \param syncobj - \c [out] sync object handle 1825 * 1826 * \return 0 on success\n 1827 * <0 - Negative POSIX Error code 1828 * 1829 */ 1830 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1831 int shared_fd, 1832 uint32_t *syncobj); 1833 1834 /** 1835 * Export kernel sync object to a sync_file. 1836 * 1837 * \param dev - \c [in] device handle 1838 * \param syncobj - \c [in] sync object handle 1839 * \param sync_file_fd - \c [out] sync_file file descriptor. 1840 * 1841 * \return 0 on success\n 1842 * <0 - Negative POSIX Error code 1843 * 1844 */ 1845 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1846 uint32_t syncobj, 1847 int *sync_file_fd); 1848 1849 /** 1850 * Import kernel sync object from a sync_file. 1851 * 1852 * \param dev - \c [in] device handle 1853 * \param syncobj - \c [in] sync object handle 1854 * \param sync_file_fd - \c [in] sync_file file descriptor. 1855 * 1856 * \return 0 on success\n 1857 * <0 - Negative POSIX Error code 1858 * 1859 */ 1860 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1861 uint32_t syncobj, 1862 int sync_file_fd); 1863 /** 1864 * Export kernel timeline sync object to a sync_file. 1865 * 1866 * \param dev - \c [in] device handle 1867 * \param syncobj - \c [in] sync object handle 1868 * \param point - \c [in] timeline point 1869 * \param flags - \c [in] flags 1870 * \param sync_file_fd - \c [out] sync_file file descriptor. 1871 * 1872 * \return 0 on success\n 1873 * <0 - Negative POSIX Error code 1874 * 1875 */ 1876 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev, 1877 uint32_t syncobj, 1878 uint64_t point, 1879 uint32_t flags, 1880 int *sync_file_fd); 1881 1882 /** 1883 * Import kernel timeline sync object from a sync_file. 1884 * 1885 * \param dev - \c [in] device handle 1886 * \param syncobj - \c [in] sync object handle 1887 * \param point - \c [in] timeline point 1888 * \param sync_file_fd - \c [in] sync_file file descriptor. 1889 * 1890 * \return 0 on success\n 1891 * <0 - Negative POSIX Error code 1892 * 1893 */ 1894 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev, 1895 uint32_t syncobj, 1896 uint64_t point, 1897 int sync_file_fd); 1898 1899 /** 1900 * transfer between syncbojs. 1901 * 1902 * \param dev - \c [in] device handle 1903 * \param dst_handle - \c [in] sync object handle 1904 * \param dst_point - \c [in] timeline point, 0 presents dst is binary 1905 * \param src_handle - \c [in] sync object handle 1906 * \param src_point - \c [in] timeline point, 0 presents src is binary 1907 * \param flags - \c [in] flags 1908 * 1909 * \return 0 on success\n 1910 * <0 - Negative POSIX Error code 1911 * 1912 */ 1913 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev, 1914 uint32_t dst_handle, 1915 uint64_t dst_point, 1916 uint32_t src_handle, 1917 uint64_t src_point, 1918 uint32_t flags); 1919 1920 /** 1921 * Export an amdgpu fence as a handle (syncobj or fd). 1922 * 1923 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1924 * \param out_handle returned handle 1925 * 1926 * \return 0 on success\n 1927 * <0 - Negative POSIX Error code 1928 */ 1929 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1930 struct amdgpu_cs_fence *fence, 1931 uint32_t what, 1932 uint32_t *out_handle); 1933 1934 /** 1935 * Submit raw command submission to kernel 1936 * 1937 * \param dev - \c [in] device handle 1938 * \param context - \c [in] context handle for context id 1939 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1940 * \param num_chunks - \c [in] number of CS chunks to submit 1941 * \param chunks - \c [in] array of CS chunks 1942 * \param seq_no - \c [out] output sequence number for submission. 1943 * 1944 * \return 0 on success\n 1945 * <0 - Negative POSIX Error code 1946 * 1947 */ 1948 struct drm_amdgpu_cs_chunk; 1949 struct drm_amdgpu_cs_chunk_dep; 1950 struct drm_amdgpu_cs_chunk_data; 1951 1952 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1953 amdgpu_context_handle context, 1954 amdgpu_bo_list_handle bo_list_handle, 1955 int num_chunks, 1956 struct drm_amdgpu_cs_chunk *chunks, 1957 uint64_t *seq_no); 1958 1959 /** 1960 * Submit raw command submission to the kernel with a raw BO list handle. 1961 * 1962 * \param dev - \c [in] device handle 1963 * \param context - \c [in] context handle for context id 1964 * \param bo_list_handle - \c [in] raw bo list handle (0 for none) 1965 * \param num_chunks - \c [in] number of CS chunks to submit 1966 * \param chunks - \c [in] array of CS chunks 1967 * \param seq_no - \c [out] output sequence number for submission. 1968 * 1969 * \return 0 on success\n 1970 * <0 - Negative POSIX Error code 1971 * 1972 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() 1973 */ 1974 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, 1975 amdgpu_context_handle context, 1976 uint32_t bo_list_handle, 1977 int num_chunks, 1978 struct drm_amdgpu_cs_chunk *chunks, 1979 uint64_t *seq_no); 1980 1981 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 1982 struct drm_amdgpu_cs_chunk_dep *dep); 1983 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 1984 struct drm_amdgpu_cs_chunk_data *data); 1985 1986 /** 1987 * Reserve VMID 1988 * \param context - \c [in] GPU Context 1989 * \param flags - \c [in] TBD 1990 * 1991 * \return 0 on success otherwise POSIX Error code 1992 */ 1993 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1994 1995 /** 1996 * Free reserved VMID 1997 * \param context - \c [in] GPU Context 1998 * \param flags - \c [in] TBD 1999 * 2000 * \return 0 on success otherwise POSIX Error code 2001 */ 2002 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 2003 2004 /** 2005 * Create USERQUEUE 2006 * \param dev - \c [in] device handle 2007 * \param ip_type - \c [in] ip type 2008 * \param doorbell_handle - \c [in] doorbell handle 2009 * \param doorbell_offset - \c [in] doorbell index 2010 * \param mqd_in - \c [in] MQD data 2011 * \param queue_va - \c [in] Virtual address of queue 2012 * \param queue_size - \c [in] userqueue size 2013 * \param wptr_va - \c [in] Virtual address of wptr 2014 * \param rptr_va - \c [in] Virtual address of rptr 2015 * \param queue_id - \c [out] queue id 2016 * 2017 * \return 0 on success otherwise POSIX Error code 2018 */ 2019 2020 int amdgpu_create_userqueue(amdgpu_device_handle dev, 2021 uint32_t ip_type, 2022 uint32_t doorbell_handle, 2023 uint32_t doorbell_offset, 2024 uint64_t queue_va, 2025 uint64_t queue_size, 2026 uint64_t wptr_va, 2027 uint64_t rptr_va, 2028 void *mqd_in, 2029 uint32_t flags, 2030 uint32_t *queue_id); 2031 2032 /** 2033 * Free USERQUEUE 2034 * \param dev - \c [in] device handle 2035 * \param queue_id - \c [in] queue id 2036 * 2037 * \return 0 on success otherwise POSIX Error code 2038 */ 2039 int amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id); 2040 2041 /** 2042 * Signal USERQUEUE 2043 * \param dev - \c [in] device handle 2044 * \param signal_data - \c [in] pointer to struct drm_amdgpu_userq_signal 2045 * to be filled by the caller 2046 * 2047 * \return 0 on success otherwise POSIX Error code 2048 */ 2049 int amdgpu_userq_signal(amdgpu_device_handle dev, 2050 struct drm_amdgpu_userq_signal *signal_data); 2051 2052 /** 2053 * Wait USERQUEUE 2054 * \param dev - \c [in] device handle 2055 * \param wait_data - \c [in/out] pointer to struct drm_amdgpu_userq_wait 2056 * to be filled by the caller 2057 * 2058 * \return 0 on success otherwise POSIX Error code 2059 */ 2060 int amdgpu_userq_wait(amdgpu_device_handle dev, 2061 struct drm_amdgpu_userq_wait *wait_data); 2062 2063 #ifdef __cplusplus 2064 } 2065 #endif 2066 #endif /* #ifdef _AMDGPU_H_ */
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