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File indexing completed on 2025-01-18 09:54:55
0001 // cpu.h - originally written and placed in the public domain by Wei Dai 0002 // updated for ARM and PowerPC by Jeffrey Walton. 0003 // updated to split CPU_Query() and CPU_Probe() by Jeffrey Walton. 0004 0005 /// \file cpu.h 0006 /// \brief Functions for CPU features and intrinsics 0007 /// \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The 0008 /// functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines. 0009 /// \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms 0010 /// a two-part strategy is used. First, the library attempts to *Query* the OS for a feature, 0011 /// like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe* 0012 /// the cpu executing an instruction and an observe a SIGILL if unsupported. The general 0013 /// pattern used by the library is: 0014 /// <pre> 0015 /// g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32(); 0016 /// g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL(); 0017 /// g_hasAES = CPU_QueryAES() || CPU_ProbeAES(); 0018 /// </pre> 0019 /// \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it 0020 /// does not require special architectural flags. CPU_Probe() is in a source file that receives 0021 /// architectural flags, like <tt>sse_simd.cpp</tt>, <tt>neon_simd.cpp</tt> and 0022 /// <tt>ppc_simd.cpp</tt>. For example, compiling <tt>neon_simd.cpp</tt> on an ARM64 machine will 0023 /// have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture 0024 /// (ISA) available. 0025 /// \details The cpu probes are expensive when compared to a standard OS feature query. The library 0026 /// also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to 0027 /// corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL 0028 /// experienced the same problem and moved away from SIGILL probes on Apple. 0029 0030 #ifndef CRYPTOPP_CPU_H 0031 #define CRYPTOPP_CPU_H 0032 0033 #include "config.h" 0034 0035 // Issue 340 0036 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE 0037 # pragma GCC diagnostic push 0038 # pragma GCC diagnostic ignored "-Wconversion" 0039 # pragma GCC diagnostic ignored "-Wsign-conversion" 0040 #endif 0041 0042 // Applies to both X86/X32/X64 and ARM32/ARM64 0043 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION) 0044 #define NEW_LINE "\n" 0045 #define INTEL_PREFIX ".intel_syntax;" 0046 #define INTEL_NOPREFIX ".intel_syntax;" 0047 #define ATT_PREFIX ".att_syntax;" 0048 #define ATT_NOPREFIX ".att_syntax;" 0049 #elif defined(CRYPTOPP_GCC_VERSION) 0050 #define NEW_LINE 0051 #define INTEL_PREFIX ".intel_syntax prefix;" 0052 #define INTEL_NOPREFIX ".intel_syntax noprefix;" 0053 #define ATT_PREFIX ".att_syntax prefix;" 0054 #define ATT_NOPREFIX ".att_syntax noprefix;" 0055 #else 0056 #define NEW_LINE 0057 #define INTEL_PREFIX 0058 #define INTEL_NOPREFIX 0059 #define ATT_PREFIX 0060 #define ATT_NOPREFIX 0061 #endif 0062 0063 // Thanks to v1ne at https://github.com/weidai11/cryptopp/pull/1133 0064 #define PERCENT_PASTE(x) "%" #x 0065 #define PERCENT_REG(x) PERCENT_PASTE(x) 0066 0067 #ifdef CRYPTOPP_GENERATE_X64_MASM 0068 0069 #define CRYPTOPP_X86_ASM_AVAILABLE 0070 #define CRYPTOPP_BOOL_X64 1 0071 #define CRYPTOPP_SSE2_ASM_AVAILABLE 1 0072 #define NAMESPACE_END 0073 0074 #else 0075 0076 NAMESPACE_BEGIN(CryptoPP) 0077 0078 // ***************************** IA-32 ***************************** // 0079 0080 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING 0081 0082 #define CRYPTOPP_CPUID_AVAILABLE 1 0083 0084 // Hide from Doxygen 0085 #ifndef CRYPTOPP_DOXYGEN_PROCESSING 0086 // These should not be used directly 0087 extern CRYPTOPP_DLL bool g_x86DetectionDone; 0088 extern CRYPTOPP_DLL bool g_hasSSE2; 0089 extern CRYPTOPP_DLL bool g_hasSSSE3; 0090 extern CRYPTOPP_DLL bool g_hasSSE41; 0091 extern CRYPTOPP_DLL bool g_hasSSE42; 0092 extern CRYPTOPP_DLL bool g_hasMOVBE; 0093 extern CRYPTOPP_DLL bool g_hasAESNI; 0094 extern CRYPTOPP_DLL bool g_hasCLMUL; 0095 extern CRYPTOPP_DLL bool g_hasAVX; 0096 extern CRYPTOPP_DLL bool g_hasAVX2; 0097 extern CRYPTOPP_DLL bool g_hasSHA; 0098 extern CRYPTOPP_DLL bool g_hasADX; 0099 extern CRYPTOPP_DLL bool g_isP4; 0100 extern CRYPTOPP_DLL bool g_hasRDRAND; 0101 extern CRYPTOPP_DLL bool g_hasRDSEED; 0102 extern CRYPTOPP_DLL bool g_hasPadlockRNG; 0103 extern CRYPTOPP_DLL bool g_hasPadlockACE; 0104 extern CRYPTOPP_DLL bool g_hasPadlockACE2; 0105 extern CRYPTOPP_DLL bool g_hasPadlockPHE; 0106 extern CRYPTOPP_DLL bool g_hasPadlockPMM; 0107 extern CRYPTOPP_DLL word32 g_cacheLineSize; 0108 0109 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features(); 0110 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[4]); 0111 #endif // CRYPTOPP_DOXYGEN_PROCESSING 0112 0113 /// \name IA-32 CPU FEATURES 0114 //@{ 0115 0116 /// \brief Determine SSE2 availability 0117 /// \return true if SSE2 is determined to be available, false otherwise 0118 /// \details MMX, SSE and SSE2 are core processor features for x86_64, and 0119 /// the function return value is based on OSXSAVE. On i386 both 0120 /// SSE2 and OSXSAVE are used for the return value. 0121 /// \note This function is only available on Intel IA-32 platforms 0122 inline bool HasSSE2() 0123 { 0124 #if (CRYPTOPP_SSE2_ASM_AVAILABLE || CRYPTOPP_SSE2_INTRIN_AVAILABLE) 0125 if (!g_x86DetectionDone) 0126 DetectX86Features(); 0127 return g_hasSSE2; 0128 #else 0129 return false; 0130 #endif 0131 } 0132 0133 /// \brief Determine SSSE3 availability 0134 /// \return true if SSSE3 is determined to be available, false otherwise 0135 /// \details HasSSSE3() is a runtime check performed using CPUID 0136 /// \note This function is only available on Intel IA-32 platforms 0137 inline bool HasSSSE3() 0138 { 0139 #if CRYPTOPP_SSSE3_AVAILABLE 0140 if (!g_x86DetectionDone) 0141 DetectX86Features(); 0142 return g_hasSSSE3; 0143 #else 0144 return false; 0145 #endif 0146 } 0147 0148 /// \brief Determine SSE4.1 availability 0149 /// \return true if SSE4.1 is determined to be available, false otherwise 0150 /// \details HasSSE41() is a runtime check performed using CPUID 0151 /// \note This function is only available on Intel IA-32 platforms 0152 inline bool HasSSE41() 0153 { 0154 #if CRYPTOPP_SSE41_AVAILABLE 0155 if (!g_x86DetectionDone) 0156 DetectX86Features(); 0157 return g_hasSSE41; 0158 #else 0159 return false; 0160 #endif 0161 } 0162 0163 /// \brief Determine SSE4.2 availability 0164 /// \return true if SSE4.2 is determined to be available, false otherwise 0165 /// \details HasSSE42() is a runtime check performed using CPUID 0166 /// \note This function is only available on Intel IA-32 platforms 0167 inline bool HasSSE42() 0168 { 0169 #if CRYPTOPP_SSE42_AVAILABLE 0170 if (!g_x86DetectionDone) 0171 DetectX86Features(); 0172 return g_hasSSE42; 0173 #else 0174 return false; 0175 #endif 0176 } 0177 0178 /// \brief Determine MOVBE availability 0179 /// \return true if MOVBE is determined to be available, false otherwise 0180 /// \details HasMOVBE() is a runtime check performed using CPUID 0181 /// \since Crypto++ 8.3 0182 /// \note This function is only available on Intel IA-32 platforms 0183 inline bool HasMOVBE() 0184 { 0185 #if CRYPTOPP_SSE42_AVAILABLE 0186 if (!g_x86DetectionDone) 0187 DetectX86Features(); 0188 return g_hasMOVBE; 0189 #else 0190 return false; 0191 #endif 0192 } 0193 0194 /// \brief Determine AES-NI availability 0195 /// \return true if AES-NI is determined to be available, false otherwise 0196 /// \details HasAESNI() is a runtime check performed using CPUID 0197 /// \since Crypto++ 5.6.1 0198 /// \note This function is only available on Intel IA-32 platforms 0199 inline bool HasAESNI() 0200 { 0201 #if CRYPTOPP_AESNI_AVAILABLE 0202 if (!g_x86DetectionDone) 0203 DetectX86Features(); 0204 return g_hasAESNI; 0205 #else 0206 return false; 0207 #endif 0208 } 0209 0210 /// \brief Determine Carryless Multiply availability 0211 /// \return true if pclmulqdq is determined to be available, false otherwise 0212 /// \details HasCLMUL() is a runtime check performed using CPUID 0213 /// \since Crypto++ 5.6.1 0214 /// \note This function is only available on Intel IA-32 platforms 0215 inline bool HasCLMUL() 0216 { 0217 #if CRYPTOPP_CLMUL_AVAILABLE 0218 if (!g_x86DetectionDone) 0219 DetectX86Features(); 0220 return g_hasCLMUL; 0221 #else 0222 return false; 0223 #endif 0224 } 0225 0226 /// \brief Determine SHA availability 0227 /// \return true if SHA is determined to be available, false otherwise 0228 /// \details HasSHA() is a runtime check performed using CPUID 0229 /// \since Crypto++ 6.0 0230 /// \note This function is only available on Intel IA-32 platforms 0231 inline bool HasSHA() 0232 { 0233 #if CRYPTOPP_SHANI_AVAILABLE 0234 if (!g_x86DetectionDone) 0235 DetectX86Features(); 0236 return g_hasSHA; 0237 #else 0238 return false; 0239 #endif 0240 } 0241 0242 /// \brief Determine ADX availability 0243 /// \return true if ADX is determined to be available, false otherwise 0244 /// \details HasADX() is a runtime check performed using CPUID 0245 /// \since Crypto++ 7.0 0246 /// \note This function is only available on Intel IA-32 platforms 0247 inline bool HasADX() 0248 { 0249 #if CRYPTOPP_ADX_AVAILABLE 0250 if (!g_x86DetectionDone) 0251 DetectX86Features(); 0252 return g_hasADX; 0253 #else 0254 return false; 0255 #endif 0256 } 0257 0258 /// \brief Determine AVX availability 0259 /// \return true if AVX is determined to be available, false otherwise 0260 /// \details HasAVX() is a runtime check performed using CPUID 0261 /// \since Crypto++ 8.0 0262 /// \note This function is only available on Intel IA-32 platforms 0263 inline bool HasAVX() 0264 { 0265 #if CRYPTOPP_AVX_AVAILABLE 0266 if (!g_x86DetectionDone) 0267 DetectX86Features(); 0268 return g_hasAVX; 0269 #else 0270 return false; 0271 #endif 0272 } 0273 0274 /// \brief Determine AVX2 availability 0275 /// \return true if AVX2 is determined to be available, false otherwise 0276 /// \details HasAVX2() is a runtime check performed using CPUID 0277 /// \since Crypto++ 8.0 0278 /// \note This function is only available on Intel IA-32 platforms 0279 inline bool HasAVX2() 0280 { 0281 #if CRYPTOPP_AVX2_AVAILABLE 0282 if (!g_x86DetectionDone) 0283 DetectX86Features(); 0284 return g_hasAVX2; 0285 #else 0286 return false; 0287 #endif 0288 } 0289 0290 /// \brief Determine RDRAND availability 0291 /// \return true if RDRAND is determined to be available, false otherwise 0292 /// \details HasRDRAND() is a runtime check performed using CPUID 0293 /// \note This function is only available on Intel IA-32 platforms 0294 inline bool HasRDRAND() 0295 { 0296 #if CRYPTOPP_RDRAND_AVAILABLE 0297 if (!g_x86DetectionDone) 0298 DetectX86Features(); 0299 return g_hasRDRAND; 0300 #else 0301 return false; 0302 #endif 0303 } 0304 0305 /// \brief Determine RDSEED availability 0306 /// \return true if RDSEED is determined to be available, false otherwise 0307 /// \details HasRDSEED() is a runtime check performed using CPUID 0308 /// \note This function is only available on Intel IA-32 platforms 0309 inline bool HasRDSEED() 0310 { 0311 #if CRYPTOPP_RDSEED_AVAILABLE 0312 if (!g_x86DetectionDone) 0313 DetectX86Features(); 0314 return g_hasRDSEED; 0315 #else 0316 return false; 0317 #endif 0318 } 0319 0320 /// \brief Determine Padlock RNG availability 0321 /// \return true if VIA Padlock RNG is determined to be available, false otherwise 0322 /// \details HasPadlockRNG() is a runtime check performed using CPUID 0323 /// \note This function is only available on Intel IA-32 platforms 0324 inline bool HasPadlockRNG() 0325 { 0326 #if CRYPTOPP_PADLOCK_RNG_AVAILABLE 0327 if (!g_x86DetectionDone) 0328 DetectX86Features(); 0329 return g_hasPadlockRNG; 0330 #else 0331 return false; 0332 #endif 0333 } 0334 0335 /// \brief Determine Padlock ACE availability 0336 /// \return true if VIA Padlock ACE is determined to be available, false otherwise 0337 /// \details HasPadlockACE() is a runtime check performed using CPUID 0338 /// \note This function is only available on Intel IA-32 platforms 0339 inline bool HasPadlockACE() 0340 { 0341 #if CRYPTOPP_PADLOCK_ACE_AVAILABLE 0342 if (!g_x86DetectionDone) 0343 DetectX86Features(); 0344 return g_hasPadlockACE; 0345 #else 0346 return false; 0347 #endif 0348 } 0349 0350 /// \brief Determine Padlock ACE2 availability 0351 /// \return true if VIA Padlock ACE2 is determined to be available, false otherwise 0352 /// \details HasPadlockACE2() is a runtime check performed using CPUID 0353 /// \note This function is only available on Intel IA-32 platforms 0354 inline bool HasPadlockACE2() 0355 { 0356 #if CRYPTOPP_PADLOCK_ACE2_AVAILABLE 0357 if (!g_x86DetectionDone) 0358 DetectX86Features(); 0359 return g_hasPadlockACE2; 0360 #else 0361 return false; 0362 #endif 0363 } 0364 0365 /// \brief Determine Padlock PHE availability 0366 /// \return true if VIA Padlock PHE is determined to be available, false otherwise 0367 /// \details HasPadlockPHE() is a runtime check performed using CPUID 0368 /// \note This function is only available on Intel IA-32 platforms 0369 inline bool HasPadlockPHE() 0370 { 0371 #if CRYPTOPP_PADLOCK_PHE_AVAILABLE 0372 if (!g_x86DetectionDone) 0373 DetectX86Features(); 0374 return g_hasPadlockPHE; 0375 #else 0376 return false; 0377 #endif 0378 } 0379 0380 /// \brief Determine Padlock PMM availability 0381 /// \return true if VIA Padlock PMM is determined to be available, false otherwise 0382 /// \details HasPadlockPMM() is a runtime check performed using CPUID 0383 /// \note This function is only available on Intel IA-32 platforms 0384 inline bool HasPadlockPMM() 0385 { 0386 #if CRYPTOPP_PADLOCK_PMM_AVAILABLE 0387 if (!g_x86DetectionDone) 0388 DetectX86Features(); 0389 return g_hasPadlockPMM; 0390 #else 0391 return false; 0392 #endif 0393 } 0394 0395 /// \brief Determine if the CPU is an Intel P4 0396 /// \return true if the CPU is a P4, false otherwise 0397 /// \details IsP4() is a runtime check performed using CPUID 0398 /// \note This function is only available on Intel IA-32 platforms 0399 inline bool IsP4() 0400 { 0401 if (!g_x86DetectionDone) 0402 DetectX86Features(); 0403 return g_isP4; 0404 } 0405 0406 /// \brief Provides the cache line size 0407 /// \return lower bound on the size of a cache line in bytes, if available 0408 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it 0409 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit 0410 /// processor and 64 is returned for a 64-bit processor. 0411 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC 0412 /// and AIX also makes the value available to user space and it is also usually accurate. The 0413 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned. 0414 inline int GetCacheLineSize() 0415 { 0416 if (!g_x86DetectionDone) 0417 DetectX86Features(); 0418 return g_cacheLineSize; 0419 } 0420 //@} 0421 0422 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 0423 0424 // ***************************** ARM-32, Aarch32 and Aarch64 ***************************** // 0425 0426 #if CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8 || CRYPTOPP_DOXYGEN_PROCESSING 0427 0428 // Hide from Doxygen 0429 #ifndef CRYPTOPP_DOXYGEN_PROCESSING 0430 extern bool g_ArmDetectionDone; 0431 extern bool g_hasARMv7; 0432 extern bool g_hasNEON; 0433 extern bool g_hasPMULL; 0434 extern bool g_hasCRC32; 0435 extern bool g_hasAES; 0436 extern bool g_hasSHA1; 0437 extern bool g_hasSHA2; 0438 extern bool g_hasSHA512; 0439 extern bool g_hasSHA3; 0440 extern bool g_hasSM3; 0441 extern bool g_hasSM4; 0442 void CRYPTOPP_API DetectArmFeatures(); 0443 #endif // CRYPTOPP_DOXYGEN_PROCESSING 0444 0445 /// \name ARM A-32, Aarch32 and AArch64 CPU FEATURES 0446 //@{ 0447 0448 /// \brief Determine if an ARM processor is ARMv7 or above 0449 /// \return true if the hardware is ARMv7 or above, false otherwise. 0450 /// \details Some AES code requires ARMv7 or above 0451 /// \since Crypto++ 8.0 0452 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms 0453 inline bool HasARMv7() 0454 { 0455 // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64 0456 #if defined(__aarch32__) || defined(__aarch64__) 0457 return true; 0458 #else 0459 if (!g_ArmDetectionDone) 0460 DetectArmFeatures(); 0461 return g_hasARMv7; 0462 #endif 0463 } 0464 0465 /// \brief Determine if an ARM processor has Advanced SIMD available 0466 /// \return true if the hardware is capable of Advanced SIMD at runtime, false otherwise. 0467 /// \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64. 0468 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0469 /// need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt> 0470 /// (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro. 0471 /// \since Crypto++ 5.6.4 0472 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms 0473 inline bool HasNEON() 0474 { 0475 // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64 0476 #if defined(CRYPTOPP_ARM_ASIMD_AVAILABLE) 0477 return true; 0478 #elif defined(CRYPTOPP_ARM_NEON_AVAILABLE) 0479 if (!g_ArmDetectionDone) 0480 DetectArmFeatures(); 0481 return g_hasNEON; 0482 #else 0483 return false; 0484 #endif 0485 } 0486 0487 /// \brief Determine if an ARM processor has CRC32 available 0488 /// \return true if the hardware is capable of CRC32 at runtime, false otherwise. 0489 /// \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C 0490 /// instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and 0491 /// available under Aarch32 and Aarch64. 0492 /// \details Runtime support requires compile time support. When compiling with GCC, 0493 /// you may need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires 0494 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro. 0495 /// \since Crypto++ 5.6.4 0496 /// \note This function is only available on Aarch32 and Aarch64 platforms 0497 inline bool HasCRC32() 0498 { 0499 #if defined(CRYPTOPP_ARM_CRC32_AVAILABLE) 0500 if (!g_ArmDetectionDone) 0501 DetectArmFeatures(); 0502 return g_hasCRC32; 0503 #else 0504 return false; 0505 #endif 0506 } 0507 0508 /// \brief Determine if an ARM processor has AES available 0509 /// \return true if the hardware is capable of AES at runtime, false otherwise. 0510 /// \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are 0511 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0512 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0513 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires 0514 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0515 /// \since Crypto++ 5.6.4 0516 /// \note This function is only available on Aarch32 and Aarch64 platforms 0517 inline bool HasAES() 0518 { 0519 #if defined(CRYPTOPP_ARM_AES_AVAILABLE) 0520 if (!g_ArmDetectionDone) 0521 DetectArmFeatures(); 0522 return g_hasAES; 0523 #else 0524 return false; 0525 #endif 0526 } 0527 0528 /// \brief Determine if an ARM processor provides Polynomial Multiplication 0529 /// \return true if the hardware is capable of polynomial multiplications at runtime, 0530 /// false otherwise. 0531 /// \details The multiplication instructions are available under Aarch32 and Aarch64. 0532 /// \details Runtime support requires compile time support. When compiling with GCC, 0533 /// you may need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires 0534 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0535 /// \since Crypto++ 5.6.4 0536 /// \note This function is only available on Aarch32 and Aarch64 platforms 0537 inline bool HasPMULL() 0538 { 0539 #if defined(CRYPTOPP_ARM_PMULL_AVAILABLE) 0540 if (!g_ArmDetectionDone) 0541 DetectArmFeatures(); 0542 return g_hasPMULL; 0543 #else 0544 return false; 0545 #endif 0546 } 0547 0548 /// \brief Determine if an ARM processor has SHA1 available 0549 /// \return true if the hardware is capable of SHA1 at runtime, false otherwise. 0550 /// \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are 0551 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0552 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0553 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires 0554 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0555 /// \since Crypto++ 5.6.4 0556 /// \note This function is only available on Aarch32 and Aarch64 platforms 0557 inline bool HasSHA1() 0558 { 0559 #if defined(CRYPTOPP_ARM_SHA1_AVAILABLE) 0560 if (!g_ArmDetectionDone) 0561 DetectArmFeatures(); 0562 return g_hasSHA1; 0563 #else 0564 return false; 0565 #endif 0566 } 0567 0568 /// \brief Determine if an ARM processor has SHA256 available 0569 /// \return true if the hardware is capable of SHA256 at runtime, false otherwise. 0570 /// \details SHA256 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are 0571 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0572 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0573 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires 0574 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0575 /// \since Crypto++ 5.6.4 0576 /// \note This function is only available on Aarch32 and Aarch64 platforms 0577 inline bool HasSHA2() 0578 { 0579 #if defined(CRYPTOPP_ARM_SHA2_AVAILABLE) 0580 if (!g_ArmDetectionDone) 0581 DetectArmFeatures(); 0582 return g_hasSHA2; 0583 #else 0584 return false; 0585 #endif 0586 } 0587 0588 /// \brief Determine if an ARM processor has SHA3 available 0589 /// \return true if the hardware is capable of SHA3 at runtime, false otherwise. 0590 /// \details SHA3 is part of the ARMv8.2 Crypto extensions on Aarch32 and Aarch64. They 0591 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0592 /// \details Runtime support requires compile time support. When compiling with GCC, you 0593 /// may need to compile with <tt>-march=armv8.2-a+crypto</tt>; while Apple requires 0594 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0595 /// \since Crypto++ 8.0 0596 /// \note This function is only available on Aarch32 and Aarch64 platforms 0597 inline bool HasSHA3() 0598 { 0599 #if defined(CRYPTOPP_ARM_SHA3_AVAILABLE) 0600 if (!g_ArmDetectionDone) 0601 DetectArmFeatures(); 0602 return g_hasSHA3; 0603 #else 0604 return false; 0605 #endif 0606 } 0607 0608 /// \brief Determine if an ARM processor has SHA512 available 0609 /// \return true if the hardware is capable of SHA512 at runtime, false otherwise. 0610 /// \details SHA512 is part of the ARMv8.2 Crypto extensions on Aarch32 and Aarch64. They 0611 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0612 /// \details Runtime support requires compile time support. When compiling with GCC, you 0613 /// may need to compile with <tt>-march=armv8.2-a+crypto</tt>; while Apple requires 0614 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0615 /// \since Crypto++ 8.0 0616 /// \note This function is only available on Aarch32 and Aarch64 platforms 0617 inline bool HasSHA512() 0618 { 0619 #if defined(CRYPTOPP_ARM_SHA512_AVAILABLE) 0620 if (!g_ArmDetectionDone) 0621 DetectArmFeatures(); 0622 return g_hasSHA512; 0623 #else 0624 return false; 0625 #endif 0626 } 0627 0628 /// \brief Determine if an ARM processor has SM3 available 0629 /// \return true if the hardware is capable of SM3 at runtime, false otherwise. 0630 /// \details SM3 is part of the ARMv8.2 Crypto extensions on Aarch32 and Aarch64. They 0631 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0632 /// \details Runtime support requires compile time support. When compiling with GCC, you 0633 /// may need to compile with <tt>-march=armv8.2-a+crypto</tt>; while Apple requires 0634 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0635 /// \since Crypto++ 8.0 0636 /// \note This function is only available on Aarch32 and Aarch64 platforms 0637 inline bool HasSM3() 0638 { 0639 #if defined(CRYPTOPP_ARM_SM3_AVAILABLE) 0640 if (!g_ArmDetectionDone) 0641 DetectArmFeatures(); 0642 return g_hasSM3; 0643 #else 0644 return false; 0645 #endif 0646 } 0647 0648 /// \brief Determine if an ARM processor has SM4 available 0649 /// \return true if the hardware is capable of SM4 at runtime, false otherwise. 0650 /// \details SM4 is part of the ARMv8.2 Crypto extensions on Aarch32 and Aarch64. They 0651 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0). 0652 /// \details Runtime support requires compile time support. When compiling with GCC, you 0653 /// may need to compile with <tt>-march=armv8.2-a+crypto</tt>; while Apple requires 0654 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro. 0655 /// \since Crypto++ 8.0 0656 /// \note This function is only available on Aarch32 and Aarch64 platforms 0657 inline bool HasSM4() 0658 { 0659 #if defined(CRYPTOPP_ARM_SM4_AVAILABLE) 0660 if (!g_ArmDetectionDone) 0661 DetectArmFeatures(); 0662 return g_hasSM4; 0663 #else 0664 return false; 0665 #endif 0666 } 0667 0668 //@} 0669 0670 #endif // CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8 0671 0672 // ***************************** PowerPC ***************************** // 0673 0674 #if CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64 || CRYPTOPP_DOXYGEN_PROCESSING 0675 0676 // Hide from Doxygen 0677 #ifndef CRYPTOPP_DOXYGEN_PROCESSING 0678 extern bool g_PowerPcDetectionDone; 0679 extern bool g_hasAltivec; 0680 extern bool g_hasPower7; 0681 extern bool g_hasPower8; 0682 extern bool g_hasPower9; 0683 extern bool g_hasAES; 0684 extern bool g_hasPMULL; 0685 extern bool g_hasSHA256; 0686 extern bool g_hasSHA512; 0687 extern bool g_hasDARN; 0688 extern word32 g_cacheLineSize; 0689 void CRYPTOPP_API DetectPowerPcFeatures(); 0690 #endif // CRYPTOPP_DOXYGEN_PROCESSING 0691 0692 /// \name POWERPC CPU FEATURES 0693 //@{ 0694 0695 /// \brief Determine if a PowerPC processor has Altivec available 0696 /// \return true if the hardware is capable of Altivec at runtime, false otherwise. 0697 /// \details Altivec instructions are available on modern PowerPCs. 0698 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0699 /// need to compile with <tt>-mcpu=power4</tt>; while IBM XL C/C++ compilers require 0700 /// <tt>-qarch=pwr6 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro. 0701 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0702 inline bool HasAltivec() 0703 { 0704 #if CRYPTOPP_ALTIVEC_AVAILABLE 0705 if (!g_PowerPcDetectionDone) 0706 DetectPowerPcFeatures(); 0707 return g_hasAltivec; 0708 #else 0709 return false; 0710 #endif 0711 } 0712 0713 /// \brief Determine if a PowerPC processor has Power7 available 0714 /// \return true if the hardware is capable of Power7 at runtime, false otherwise. 0715 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0716 /// need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require 0717 /// <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro. 0718 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0719 inline bool HasPower7() 0720 { 0721 #if CRYPTOPP_POWER7_AVAILABLE 0722 if (!g_PowerPcDetectionDone) 0723 DetectPowerPcFeatures(); 0724 return g_hasPower7; 0725 #else 0726 return false; 0727 #endif 0728 } 0729 0730 /// \brief Determine if a PowerPC processor has Power8 available 0731 /// \return true if the hardware is capable of Power8 at runtime, false otherwise. 0732 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0733 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require 0734 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro. 0735 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0736 inline bool HasPower8() 0737 { 0738 #if CRYPTOPP_POWER8_AVAILABLE 0739 if (!g_PowerPcDetectionDone) 0740 DetectPowerPcFeatures(); 0741 return g_hasPower8; 0742 #else 0743 return false; 0744 #endif 0745 } 0746 0747 /// \brief Determine if a PowerPC processor has Power9 available 0748 /// \return true if the hardware is capable of Power9 at runtime, false otherwise. 0749 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0750 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require 0751 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro. 0752 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0753 inline bool HasPower9() 0754 { 0755 #if CRYPTOPP_POWER9_AVAILABLE 0756 if (!g_PowerPcDetectionDone) 0757 DetectPowerPcFeatures(); 0758 return g_hasPower9; 0759 #else 0760 return false; 0761 #endif 0762 } 0763 0764 /// \brief Determine if a PowerPC processor has AES available 0765 /// \return true if the hardware is capable of AES at runtime, false otherwise. 0766 /// \details AES is part of the in-crypto extensions on Power8 and Power9. 0767 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0768 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require 0769 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro. 0770 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0771 inline bool HasAES() 0772 { 0773 #if CRYPTOPP_POWER8_AES_AVAILABLE 0774 if (!g_PowerPcDetectionDone) 0775 DetectPowerPcFeatures(); 0776 return g_hasAES; 0777 #else 0778 return false; 0779 #endif 0780 } 0781 0782 /// \brief Determine if a PowerPC processor has Polynomial Multiply available 0783 /// \return true if the hardware is capable of PMULL at runtime, false otherwise. 0784 /// \details PMULL is part of the in-crypto extensions on Power8 and Power9. 0785 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0786 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require 0787 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro. 0788 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0789 inline bool HasPMULL() 0790 { 0791 #if CRYPTOPP_POWER8_VMULL_AVAILABLE 0792 if (!g_PowerPcDetectionDone) 0793 DetectPowerPcFeatures(); 0794 return g_hasPMULL; 0795 #else 0796 return false; 0797 #endif 0798 } 0799 0800 /// \brief Determine if a PowerPC processor has SHA256 available 0801 /// \return true if the hardware is capable of SHA256 at runtime, false otherwise. 0802 /// \details SHA is part of the in-crypto extensions on Power8 and Power9. 0803 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0804 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require 0805 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro. 0806 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0807 inline bool HasSHA256() 0808 { 0809 #if CRYPTOPP_POWER8_SHA_AVAILABLE 0810 if (!g_PowerPcDetectionDone) 0811 DetectPowerPcFeatures(); 0812 return g_hasSHA256; 0813 #else 0814 return false; 0815 #endif 0816 } 0817 0818 /// \brief Determine if a PowerPC processor has SHA512 available 0819 /// \return true if the hardware is capable of SHA512 at runtime, false otherwise. 0820 /// \details SHA is part of the in-crypto extensions on Power8 and Power9. 0821 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0822 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require 0823 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro. 0824 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0825 inline bool HasSHA512() 0826 { 0827 #if CRYPTOPP_POWER8_SHA_AVAILABLE 0828 if (!g_PowerPcDetectionDone) 0829 DetectPowerPcFeatures(); 0830 return g_hasSHA512; 0831 #else 0832 return false; 0833 #endif 0834 } 0835 0836 /// \brief Determine if a PowerPC processor has DARN available 0837 /// \return true if the hardware is capable of DARN at runtime, false otherwise. 0838 /// \details Runtime support requires compile time support. When compiling with GCC, you may 0839 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require 0840 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro. 0841 /// \note This function is only available on PowerPC and PowerPC-64 platforms 0842 inline bool HasDARN() 0843 { 0844 #if CRYPTOPP_POWER9_AVAILABLE 0845 if (!g_PowerPcDetectionDone) 0846 DetectPowerPcFeatures(); 0847 // see comments in cpu.cpp 0848 # if defined(__ibmxl__) && defined(__linux__) 0849 return false; 0850 # else 0851 return g_hasDARN; 0852 # endif 0853 #else 0854 return false; 0855 #endif 0856 } 0857 0858 /// \brief Provides the cache line size 0859 /// \return lower bound on the size of a cache line in bytes, if available 0860 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it 0861 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit 0862 /// processor and 64 is returned for a 64-bit processor. 0863 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC 0864 /// and AIX also makes the value available to user space and it is also usually accurate. The 0865 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned. 0866 inline int GetCacheLineSize() 0867 { 0868 if (!g_PowerPcDetectionDone) 0869 DetectPowerPcFeatures(); 0870 return g_cacheLineSize; 0871 } 0872 0873 //@} 0874 0875 #endif // CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64 0876 0877 // ***************************** L1 cache line ***************************** // 0878 0879 // Non-Intel systems 0880 #if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64) 0881 /// \brief Provides the cache line size 0882 /// \return lower bound on the size of a cache line in bytes, if available 0883 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it 0884 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit 0885 /// processor and 64 is returned for a 64-bit processor. 0886 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC 0887 /// and AIX also makes the value available to user space and it is also usually accurate. The 0888 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned. 0889 inline int GetCacheLineSize() 0890 { 0891 return CRYPTOPP_L1_CACHE_LINE_SIZE; 0892 } 0893 #endif // Non-Intel systems 0894 0895 #endif // CRYPTOPP_GENERATE_X64_MASM 0896 0897 // ***************************** Inline ASM Helper ***************************** // 0898 0899 #ifndef CRYPTOPP_DOXYGEN_PROCESSING 0900 0901 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 0902 0903 #ifdef CRYPTOPP_GENERATE_X64_MASM 0904 #define AS1(x) x*newline* 0905 #define AS2(x, y) x, y*newline* 0906 #define AS3(x, y, z) x, y, z*newline* 0907 #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline* 0908 #define ASL(x) label##x:*newline* 0909 #define ASJ(x, y, z) x label##y*newline* 0910 #define ASC(x, y) x label##y*newline* 0911 #define AS_HEX(y) 0##y##h 0912 #elif defined(CRYPTOPP_MSC_VERSION) || defined(__BORLANDC__) 0913 #define AS1(x) __asm {x} 0914 #define AS2(x, y) __asm {x, y} 0915 #define AS3(x, y, z) __asm {x, y, z} 0916 #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)} 0917 #define ASL(x) __asm {label##x:} 0918 #define ASJ(x, y, z) __asm {x label##y} 0919 #define ASC(x, y) __asm {x label##y} 0920 #define CRYPTOPP_NAKED __declspec(naked) 0921 #define AS_HEX(y) 0x##y 0922 #else 0923 // define these in two steps to allow arguments to be expanded 0924 #define GNU_AS1(x) #x ";" NEW_LINE 0925 #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE 0926 #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE 0927 #define GNU_ASL(x) "\n" #x ":" NEW_LINE 0928 // clang 5.0.0 and apple clang 9.0.0 don't support numerical backward jumps 0929 #if (CRYPTOPP_LLVM_CLANG_VERSION >= 50000) || (CRYPTOPP_APPLE_CLANG_VERSION >= 90000) 0930 #define GNU_ASJ(x, y, z) ATT_PREFIX ";" NEW_LINE #x " " #y #z ";" NEW_LINE INTEL_PREFIX ";" NEW_LINE 0931 #else 0932 #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE 0933 #endif 0934 #define AS1(x) GNU_AS1(x) 0935 #define AS2(x, y) GNU_AS2(x, y) 0936 #define AS3(x, y, z) GNU_AS3(x, y, z) 0937 #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";" 0938 #define ASL(x) GNU_ASL(x) 0939 #define ASJ(x, y, z) GNU_ASJ(x, y, z) 0940 #define ASC(x, y) #x " " #y ";" 0941 #define CRYPTOPP_NAKED 0942 #define AS_HEX(y) 0x##y 0943 #endif 0944 0945 #define IF0(y) 0946 #define IF1(y) y 0947 0948 #ifdef CRYPTOPP_GENERATE_X64_MASM 0949 #define ASM_MOD(x, y) ((x) MOD (y)) 0950 #define XMMWORD_PTR XMMWORD PTR 0951 #else 0952 // GNU assembler doesn't seem to have mod operator 0953 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y)) 0954 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM 0955 #define XMMWORD_PTR 0956 #endif 0957 0958 #if CRYPTOPP_BOOL_X86 0959 #define AS_REG_1 ecx 0960 #define AS_REG_2 edx 0961 #define AS_REG_3 esi 0962 #define AS_REG_4 edi 0963 #define AS_REG_5 eax 0964 #define AS_REG_6 ebx 0965 #define AS_REG_7 ebp 0966 #define AS_REG_1d ecx 0967 #define AS_REG_2d edx 0968 #define AS_REG_3d esi 0969 #define AS_REG_4d edi 0970 #define AS_REG_5d eax 0971 #define AS_REG_6d ebx 0972 #define AS_REG_7d ebp 0973 #define WORD_SZ 4 0974 #define WORD_REG(x) e##x 0975 #define WORD_PTR DWORD PTR 0976 #define AS_PUSH_IF86(x) AS1(push e##x) 0977 #define AS_POP_IF86(x) AS1(pop e##x) 0978 #define AS_JCXZ jecxz 0979 #elif CRYPTOPP_BOOL_X32 0980 #define AS_REG_1 ecx 0981 #define AS_REG_2 edx 0982 #define AS_REG_3 r8d 0983 #define AS_REG_4 r9d 0984 #define AS_REG_5 eax 0985 #define AS_REG_6 r10d 0986 #define AS_REG_7 r11d 0987 #define AS_REG_1d ecx 0988 #define AS_REG_2d edx 0989 #define AS_REG_3d r8d 0990 #define AS_REG_4d r9d 0991 #define AS_REG_5d eax 0992 #define AS_REG_6d r10d 0993 #define AS_REG_7d r11d 0994 #define WORD_SZ 4 0995 #define WORD_REG(x) e##x 0996 #define WORD_PTR DWORD PTR 0997 #define AS_PUSH_IF86(x) AS1(push r##x) 0998 #define AS_POP_IF86(x) AS1(pop r##x) 0999 #define AS_JCXZ jecxz 1000 #elif CRYPTOPP_BOOL_X64 1001 #ifdef CRYPTOPP_GENERATE_X64_MASM 1002 #define AS_REG_1 rcx 1003 #define AS_REG_2 rdx 1004 #define AS_REG_3 r8 1005 #define AS_REG_4 r9 1006 #define AS_REG_5 rax 1007 #define AS_REG_6 r10 1008 #define AS_REG_7 r11 1009 #define AS_REG_1d ecx 1010 #define AS_REG_2d edx 1011 #define AS_REG_3d r8d 1012 #define AS_REG_4d r9d 1013 #define AS_REG_5d eax 1014 #define AS_REG_6d r10d 1015 #define AS_REG_7d r11d 1016 #else 1017 #define AS_REG_1 rdi 1018 #define AS_REG_2 rsi 1019 #define AS_REG_3 rdx 1020 #define AS_REG_4 rcx 1021 #define AS_REG_5 r8 1022 #define AS_REG_6 r9 1023 #define AS_REG_7 r10 1024 #define AS_REG_1d edi 1025 #define AS_REG_2d esi 1026 #define AS_REG_3d edx 1027 #define AS_REG_4d ecx 1028 #define AS_REG_5d r8d 1029 #define AS_REG_6d r9d 1030 #define AS_REG_7d r10d 1031 #endif 1032 #define WORD_SZ 8 1033 #define WORD_REG(x) r##x 1034 #define WORD_PTR QWORD PTR 1035 #define AS_PUSH_IF86(x) 1036 #define AS_POP_IF86(x) 1037 #define AS_JCXZ jrcxz 1038 #endif 1039 1040 // helper macro for stream cipher output 1041 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\ 1042 AS2( test inputPtr, inputPtr)\ 1043 ASC( jz, labelPrefix##3)\ 1044 AS2( test inputPtr, 15)\ 1045 ASC( jnz, labelPrefix##7)\ 1046 AS2( pxor xmm##x0, [inputPtr+p0*16])\ 1047 AS2( pxor xmm##x1, [inputPtr+p1*16])\ 1048 AS2( pxor xmm##x2, [inputPtr+p2*16])\ 1049 AS2( pxor xmm##x3, [inputPtr+p3*16])\ 1050 AS2( add inputPtr, increment*16)\ 1051 ASC( jmp, labelPrefix##3)\ 1052 ASL(labelPrefix##7)\ 1053 AS2( movdqu xmm##t, [inputPtr+p0*16])\ 1054 AS2( pxor xmm##x0, xmm##t)\ 1055 AS2( movdqu xmm##t, [inputPtr+p1*16])\ 1056 AS2( pxor xmm##x1, xmm##t)\ 1057 AS2( movdqu xmm##t, [inputPtr+p2*16])\ 1058 AS2( pxor xmm##x2, xmm##t)\ 1059 AS2( movdqu xmm##t, [inputPtr+p3*16])\ 1060 AS2( pxor xmm##x3, xmm##t)\ 1061 AS2( add inputPtr, increment*16)\ 1062 ASL(labelPrefix##3)\ 1063 AS2( test outputPtr, 15)\ 1064 ASC( jnz, labelPrefix##8)\ 1065 AS2( movdqa [outputPtr+p0*16], xmm##x0)\ 1066 AS2( movdqa [outputPtr+p1*16], xmm##x1)\ 1067 AS2( movdqa [outputPtr+p2*16], xmm##x2)\ 1068 AS2( movdqa [outputPtr+p3*16], xmm##x3)\ 1069 ASC( jmp, labelPrefix##9)\ 1070 ASL(labelPrefix##8)\ 1071 AS2( movdqu [outputPtr+p0*16], xmm##x0)\ 1072 AS2( movdqu [outputPtr+p1*16], xmm##x1)\ 1073 AS2( movdqu [outputPtr+p2*16], xmm##x2)\ 1074 AS2( movdqu [outputPtr+p3*16], xmm##x3)\ 1075 ASL(labelPrefix##9)\ 1076 AS2( add outputPtr, increment*16) 1077 1078 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 1079 1080 #endif // Not CRYPTOPP_DOXYGEN_PROCESSING 1081 1082 NAMESPACE_END 1083 1084 // Issue 340 1085 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE 1086 # pragma GCC diagnostic pop 1087 #endif 1088 1089 #endif // CRYPTOPP_CPU_H
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