include/corecel/DeviceRuntimeApi.hh

0001 /*-----------------------------------*-C++-*-----------------------------------
0002  * Copyright 2022-2024 UT-Battelle, LLC, and other Celeritas developers.
0003  * See the top-level COPYRIGHT file for details.
0004  * SPDX-License-Identifier: (Apache-2.0 OR MIT)
0005  *---------------------------------------------------------------------------*/
0006 //! \file corecel/DeviceRuntimeApi.hh
0007 //! \brief Include CUDA or HIP runtime APIs for compiling with host/cc
0008 //! compiler.
0009 //---------------------------------------------------------------------------//
0010 #pragma once
0011
0012 #include "corecel/Config.hh"
0013
0014 #if CELERITAS_USE_HIP && !defined(__HIPCC__)
0015 /* Assume we're on an AMD system but not being invoked by the rocm compiler */
0016 #    define __HIP_PLATFORM_AMD__ 1
0017 #    define __HIP_PLATFORM_HCC__ 1
0018 #endif
0019
0020 #if CELERITAS_USE_CUDA
0021 #    include <cuda_runtime_api.h>
0022 #    define THRUST_DEVICE_SYSTEM THRUST_DEVICE_SYSTEM_CUDA
0023 #elif CELERITAS_USE_HIP
0024 #    include <hip/hip_runtime.h>
0025 #    define THRUST_DEVICE_SYSTEM THRUST_DEVICE_SYSTEM_HIP
0026 #endif
0027
0028 #if CELERITAS_USE_CUDA || CELERITAS_USE_HIP
0029 #    include <thrust/mr/memory_resource.h>
0030 #endif
0031
0032 /*!
0033  * \def CELER_EU_PER_CU
0034  *
0035  * Execution units per compute unit.  AMD multiprocessors each have 4 SIMD
0036  * units per compute unit, but there is no device attribute or
0037  * compiler definition that provides this information.
0038  * For CUDA, each streaming multiprocessor (MP) is a single "execution unit"
0039  * and a "compute unit".
0040  */
0041 #if CELERITAS_USE_CUDA
0042 #    define CELER_EU_PER_CU 1
0043 #elif CELERITAS_USE_HIP
0044 #    if defined(__HIP_PLATFORM_AMD__) || defined(__HIP_PLATFORM_HCC__)
0045 #        define CELER_EU_PER_CU 4
0046 #    elif defined(__HIP_PLATFORM_NVIDIA__) || defined(__HIP_PLATFORM_NVCC__)
0047 #        define CELER_EU_PER_CU 1
0048 #    else
0049 #        warning "Unknown HIP device configuration"
0050 #        define CELER_EU_PER_CU 0
0051 #    endif
0052 #else
0053 /* HIP and CUDA are disabled */
0054 #    define CELER_EU_PER_CU 0
0055 #endif
0056
0057 /*!
0058  * Declare a dummy variable to be referenced in disabled \c CELER_BLAH calls.
0059  *
0060  * With this declaration, the build will fail if this include is missing.
0061  * (Unfortunately, since the use of this symbol is embedded in a macro, IWYU
0062  * won't include this file automatically.)
0063  */
0064 extern int CorecelDeviceRuntimeApiHh;