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0014 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_SPARC_HPP_INCLUDED_
0015 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_SPARC_HPP_INCLUDED_
0016
0017 #include <boost/memory_order.hpp>
0018 #include <boost/atomic/detail/config.hpp>
0019 #include <boost/atomic/detail/header.hpp>
0020
0021 #ifdef BOOST_HAS_PRAGMA_ONCE
0022 #pragma once
0023 #endif
0024
0025 namespace boost {
0026 namespace atomics {
0027 namespace detail {
0028
0029
0030 struct fence_arch_operations_gcc_sparc
0031 {
0032 static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
0033 {
0034 switch (order)
0035 {
0036 case memory_order_release:
0037 __asm__ __volatile__ ("membar #StoreStore | #LoadStore" ::: "memory");
0038 break;
0039 case memory_order_consume:
0040 case memory_order_acquire:
0041 __asm__ __volatile__ ("membar #LoadLoad | #LoadStore" ::: "memory");
0042 break;
0043 case memory_order_acq_rel:
0044 __asm__ __volatile__ ("membar #LoadLoad | #LoadStore | #StoreStore" ::: "memory");
0045 break;
0046 case memory_order_seq_cst:
0047 __asm__ __volatile__ ("membar #Sync" ::: "memory");
0048 break;
0049 case memory_order_relaxed:
0050 default:
0051 break;
0052 }
0053 }
0054
0055 static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
0056 {
0057 if (order != memory_order_relaxed)
0058 __asm__ __volatile__ ("" ::: "memory");
0059 }
0060 };
0061
0062 typedef fence_arch_operations_gcc_sparc fence_arch_operations;
0063
0064 }
0065 }
0066 }
0067
0068 #include <boost/atomic/detail/footer.hpp>
0069
0070 #endif