atomic/detail/fence_arch_ops_gcc_arm.hpp

0001 /*
0002  * Distributed under the Boost Software License, Version 1.0.
0003  * (See accompanying file LICENSE_1_0.txt or copy at
0004  * http://www.boost.org/LICENSE_1_0.txt)
0005  *
0006  * Copyright (c) 2020 Andrey Semashev
0007  */
0008 /*!
0009  * \file   atomic/detail/fence_arch_ops_gcc_arm.hpp
0010  *
0011  * This header contains implementation of the \c fence_arch_operations struct.
0012  */
0013
0014 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
0015 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
0016
0017 #include <boost/cstdint.hpp>
0018 #include <boost/memory_order.hpp>
0019 #include <boost/atomic/detail/config.hpp>
0020 #include <boost/atomic/detail/capabilities.hpp>
0021 #include <boost/atomic/detail/gcc_arm_asm_common.hpp>
0022 #include <boost/atomic/detail/header.hpp>
0023
0024 #ifdef BOOST_HAS_PRAGMA_ONCE
0025 #pragma once
0026 #endif
0027
0028 namespace boost {
0029 namespace atomics {
0030 namespace detail {
0031
0032 //! Fence operations for legacy ARM
0033 struct fence_arch_operations_gcc_arm
0034 {
0035     static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
0036     {
0037         if (order != memory_order_relaxed)
0038             hardware_full_fence();
0039     }
0040
0041     static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
0042     {
0043         if (order != memory_order_relaxed)
0044             __asm__ __volatile__ ("" ::: "memory");
0045     }
0046
0047     static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
0048     {
0049         // A memory barrier is effected using a "co-processor 15" instruction,
0050         // though a separate assembler mnemonic is available for it in v7.
0051
0052 #if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
0053         // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
0054         // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
0055         // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
0056         __asm__ __volatile__
0057         (
0058 #if defined(__thumb2__)
0059             ".short 0xF3BF, 0x8F5B\n\t" // dmb ish
0060 #else
0061             ".word 0xF57FF05B\n\t" // dmb ish
0062 #endif
0063             :
0064             :
0065             : "memory"
0066         );
0067 #else
0068         uint32_t tmp;
0069         __asm__ __volatile__
0070         (
0071             BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
0072             "mcr p15, 0, r0, c7, c10, 5\n\t"
0073             BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
0074             : "=&l" (tmp)
0075             :
0076             : "memory"
0077         );
0078 #endif
0079     }
0080 };
0081
0082 typedef fence_arch_operations_gcc_arm fence_arch_operations;
0083
0084 } // namespace detail
0085 } // namespace atomics
0086 } // namespace boost
0087
0088 #include <boost/atomic/detail/footer.hpp>
0089
0090 #endif // BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_